[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / clock.c

/*
 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>

enum pll_clocks {
	PLL_SYS,	/* System PLL */
	PLL_BUS,	/* System Bus PLL*/
	PLL_USBOTG,	/* OTG USB PLL */
	PLL_ENET,	/* ENET PLL */
};

struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
{
	u32 reg;

	reg = __raw_readl(&imx_ccm->CCGR2);
	if (enable)
		reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
	else
		reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
	__raw_writel(reg, &imx_ccm->CCGR2);
}
#endif

void enable_usboh3_clk(unsigned char enable)
{
	u32 reg;

	reg = __raw_readl(&imx_ccm->CCGR6);
	if (enable)
		reg |= MXC_CCM_CCGR6_USBOH3_MASK;
	else
		reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
	__raw_writel(reg, &imx_ccm->CCGR6);

}

#ifdef CONFIG_SYS_I2C_MXC
/* i2c_num can be from 0 - 2 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
	u32 reg;
	u32 mask;

	if (i2c_num > 2)
		return -EINVAL;

	mask = MXC_CCM_CCGR_CG_MASK
		<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
	reg = __raw_readl(&imx_ccm->CCGR2);
	if (enable)
		reg |= mask;
	else
		reg &= ~mask;
	__raw_writel(reg, &imx_ccm->CCGR2);
	return 0;
}
#endif

/* spi_num can be from 0 - SPI_MAX_NUM */
int enable_spi_clk(unsigned char enable, unsigned spi_num)
{
	u32 reg;
	u32 mask;

	if (spi_num > SPI_MAX_NUM)
		return -EINVAL;

	mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
	reg = __raw_readl(&imx_ccm->CCGR1);
	if (enable)
		reg |= mask;
	else
		reg &= ~mask;
	__raw_writel(reg, &imx_ccm->CCGR1);
	return 0;
}
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
	u32 div;

	switch (pll) {
	case PLL_SYS:
		div = __raw_readl(&imx_ccm->analog_pll_sys);
		div &= BM_ANADIG_PLL_SYS_DIV_SELECT;

		return (infreq * div) >> 1;
	case PLL_BUS:
		div = __raw_readl(&imx_ccm->analog_pll_528);
		div &= BM_ANADIG_PLL_528_DIV_SELECT;

		return infreq * (20 + (div << 1));
	case PLL_USBOTG:
		div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
		div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;

		return infreq * (20 + (div << 1));
	case PLL_ENET:
		div = __raw_readl(&imx_ccm->analog_pll_enet);
		div &= BM_ANADIG_PLL_ENET_DIV_SELECT;

		return 25000000 * (div + (div >> 1) + 1);
	default:
		return 0;
	}
	/* NOTREACHED */
}
static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
{
	u32 div;
	u64 freq;

	switch (pll) {
	case PLL_BUS:
		if (pfd_num == 3) {
			/* No PFD3 on PPL2 */
			return 0;
		}
		div = __raw_readl(&imx_ccm->analog_pfd_528);
		freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
		break;
	case PLL_USBOTG:
		div = __raw_readl(&imx_ccm->analog_pfd_480);
		freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
		break;
	default:
		/* No PFD on other PLL					     */
		return 0;
	}

	return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
			      ANATOP_PFD_FRAC_SHIFT(pfd_num));
}

static u32 get_mcu_main_clk(void)
{
	u32 reg, freq;

	reg = __raw_readl(&imx_ccm->cacrr);
	reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
	reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
	freq = decode_pll(PLL_SYS, MXC_HCLK);

	return freq / (reg + 1);
}

u32 get_periph_clk(void)
{
	u32 reg, freq = 0;

	reg = __raw_readl(&imx_ccm->cbcdr);
	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
		reg = __raw_readl(&imx_ccm->cbcmr);
		reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
		reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;

		switch (reg) {
		case 0:
			freq = decode_pll(PLL_USBOTG, MXC_HCLK);
			break;
		case 1:
		case 2:
			freq = MXC_HCLK;
			break;
		default:
			break;
		}
	} else {
		reg = __raw_readl(&imx_ccm->cbcmr);
		reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
		reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;

		switch (reg) {
		case 0:
			freq = decode_pll(PLL_BUS, MXC_HCLK);
			break;
		case 1:
			freq = mxc_get_pll_pfd(PLL_BUS, 2);
			break;
		case 2:
			freq = mxc_get_pll_pfd(PLL_BUS, 0);
			break;
		case 3:
			/* static / 2 divider */
			freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
			break;
		default:
			break;
		}
	}

	return freq;
}

static u32 get_ipg_clk(void)
{
	u32 reg, ipg_podf;

	reg = __raw_readl(&imx_ccm->cbcdr);
	reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
	ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;

	return get_ahb_clk() / (ipg_podf + 1);
}

static u32 get_ipg_per_clk(void)
{
	u32 reg, perclk_podf;

	reg = __raw_readl(&imx_ccm->cscmr1);
	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;

	return get_ipg_clk() / (perclk_podf + 1);
}

static u32 get_uart_clk(void)
{
	u32 reg, uart_podf;
	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
	reg = __raw_readl(&imx_ccm->cscdr1);
#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
		freq = MXC_HCLK;
#endif
	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;

	return freq / (uart_podf + 1);
}

static u32 get_cspi_clk(void)
{
	u32 reg, cspi_podf;

	reg = __raw_readl(&imx_ccm->cscdr2);
	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;

	return	decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
}

static u32 get_axi_clk(void)
{
	u32 root_freq, axi_podf;
	u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);

	axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
	axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;

	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
		if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
			root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
		else
			root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
	} else
		root_freq = get_periph_clk();

	return  root_freq / (axi_podf + 1);
}

static u32 get_emi_slow_clk(void)
{
	u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;

	cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
	emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
	emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
	emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
	emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;

	switch (emi_clk_sel) {
	case 0:
		root_freq = get_axi_clk();
		break;
	case 1:
		root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
		break;
	case 2:
		root_freq =  mxc_get_pll_pfd(PLL_BUS, 2);
		break;
	case 3:
		root_freq =  mxc_get_pll_pfd(PLL_BUS, 0);
		break;
	}

	return root_freq / (emi_slow_podf + 1);
}

#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	u32 freq, podf;

	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
			>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;

	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
		MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
	case 0:
		freq = decode_pll(PLL_BUS, MXC_HCLK);
		break;
	case 1:
		freq = mxc_get_pll_pfd(PLL_BUS, 2);
		break;
	case 2:
		freq = mxc_get_pll_pfd(PLL_BUS, 0);
		break;
	case 3:
		/* static / 2 divider */
		freq =  mxc_get_pll_pfd(PLL_BUS, 2) / 2;
	}

	return freq / (podf + 1);

}
#else
static u32 get_mmdc_ch0_clk(void)
{
	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;

	return get_periph_clk() / (mmdc_ch0_podf + 1);
}
#endif

#ifdef CONFIG_FEC_MXC
int enable_fec_anatop_clock(enum enet_freq freq)
{
	u32 reg = 0;
	s32 timeout = 100000;

	struct anatop_regs __iomem *anatop =
		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;

	if (freq < ENET_25MHz || freq > ENET_125MHz)
		return -EINVAL;

	reg = readl(&anatop->pll_enet);
	reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
	reg |= freq;

	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
		reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
		writel(reg, &anatop->pll_enet);
		while (timeout--) {
			if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
				break;
		}
		if (timeout < 0)
			return -ETIMEDOUT;
	}

	/* Enable FEC clock */
	reg |= BM_ANADIG_PLL_ENET_ENABLE;
	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
	writel(reg, &anatop->pll_enet);

#ifdef CONFIG_MX6SX
	/*
	 * Set enet ahb clock to 200MHz
	 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
	 */
	reg = readl(&imx_ccm->chsccdr);
	reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
		 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
		 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
	/* PLL2 PFD2 */
	reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
	/* Div = 2*/
	reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
	reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
	writel(reg, &imx_ccm->chsccdr);

	/* Enable enet system clock */
	reg = readl(&imx_ccm->CCGR3);
	reg |= MXC_CCM_CCGR3_ENET_MASK;
	writel(reg, &imx_ccm->CCGR3);
#endif
	return 0;
}
#endif

static u32 get_usdhc_clk(u32 port)
{
	u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);

	switch (port) {
	case 0:
		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
					MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;

		break;
	case 1:
		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
					MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;

		break;
	case 2:
		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
					MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;

		break;
	case 3:
		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
					MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;

		break;
	default:
		break;
	}

	if (clk_sel)
		root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
	else
		root_freq = mxc_get_pll_pfd(PLL_BUS, 2);

	return root_freq / (usdhc_podf + 1);
}

u32 imx_get_uartclk(void)
{
	return get_uart_clk();
}

u32 imx_get_fecclk(void)
{
	return mxc_get_clock(MXC_IPG_CLK);
}

static int enable_enet_pll(uint32_t en)
{
	struct mxc_ccm_reg *const imx_ccm
		= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
	s32 timeout = 100000;
	u32 reg = 0;

	/* Enable PLLs */
	reg = readl(&imx_ccm->analog_pll_enet);
	reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
	writel(reg, &imx_ccm->analog_pll_enet);
	reg |= BM_ANADIG_PLL_SYS_ENABLE;
	while (timeout--) {
		if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
			break;
	}
	if (timeout <= 0)
		return -EIO;
	reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
	writel(reg, &imx_ccm->analog_pll_enet);
	reg |= en;
	writel(reg, &imx_ccm->analog_pll_enet);
	return 0;
}

#ifndef CONFIG_MX6SX
static void ungate_sata_clock(void)
{
	struct mxc_ccm_reg *const imx_ccm =
		(struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* Enable SATA clock. */
	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
#endif

static void ungate_pcie_clock(void)
{
	struct mxc_ccm_reg *const imx_ccm =
		(struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* Enable PCIe clock. */
	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
}

#ifndef CONFIG_MX6SX
int enable_sata_clock(void)
{
	ungate_sata_clock();
	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
#endif

int enable_pcie_clock(void)
{
	struct anatop_regs *anatop_regs =
		(struct anatop_regs *)ANATOP_BASE_ADDR;
	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/*
	 * Here be dragons!
	 *
	 * The register ANATOP_MISC1 is not documented in the Freescale
	 * MX6RM. The register that is mapped in the ANATOP space and
	 * marked as ANATOP_MISC1 is actually documented in the PMU section
	 * of the datasheet as PMU_MISC1.
	 *
	 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
	 * enable clock OUTPUT. This is important for PCI express link that
	 * is clocked from the i.MX6.
	 */
#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN		(1 << 12)
#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN		(1 << 10)
#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK	0x0000001F
	clrsetbits_le32(&anatop_regs->ana_misc1,
			ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
			ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
			ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);

	/* PCIe reference clock sourced from AXI. */
	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);

	/* Party time! Ungate the clock to the PCIe. */
#ifndef CONFIG_MX6SX
	ungate_sata_clock();
#endif
	ungate_pcie_clock();

	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
			       BM_ANADIG_PLL_ENET_ENABLE_PCIE);
}

unsigned int mxc_get_clock(enum mxc_clock clk)
{
	switch (clk) {
	case MXC_ARM_CLK:
		return get_mcu_main_clk();
	case MXC_PER_CLK:
		return get_periph_clk();
	case MXC_AHB_CLK:
		return get_ahb_clk();
	case MXC_IPG_CLK:
		return get_ipg_clk();
	case MXC_IPG_PERCLK:
	case MXC_I2C_CLK:
		return get_ipg_per_clk();
	case MXC_UART_CLK:
		return get_uart_clk();
	case MXC_CSPI_CLK:
		return get_cspi_clk();
	case MXC_AXI_CLK:
		return get_axi_clk();
	case MXC_EMI_SLOW_CLK:
		return get_emi_slow_clk();
	case MXC_DDR_CLK:
		return get_mmdc_ch0_clk();
	case MXC_ESDHC_CLK:
		return get_usdhc_clk(0);
	case MXC_ESDHC2_CLK:
		return get_usdhc_clk(1);
	case MXC_ESDHC3_CLK:
		return get_usdhc_clk(2);
	case MXC_ESDHC4_CLK:
		return get_usdhc_clk(3);
	case MXC_SATA_CLK:
		return get_ahb_clk();
	default:
		break;
	}

	return -1;
}

/*
 * Dump some core clockes.
 */
int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	u32 freq;
	freq = decode_pll(PLL_SYS, MXC_HCLK);
	printf("PLL_SYS    %8d MHz\n", freq / 1000000);
	freq = decode_pll(PLL_BUS, MXC_HCLK);
	printf("PLL_BUS    %8d MHz\n", freq / 1000000);
	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
	printf("PLL_OTG    %8d MHz\n", freq / 1000000);
	freq = decode_pll(PLL_ENET, MXC_HCLK);
	printf("PLL_NET    %8d MHz\n", freq / 1000000);

	printf("\n");
	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
	printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
#ifdef CONFIG_MXC_SPI
	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
#endif
	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
	printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
	printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
	printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
	printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
	printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
	printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);

	return 0;
}

#ifndef CONFIG_MX6SX
void enable_ipu_clock(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	int reg;
	reg = readl(&mxc_ccm->CCGR3);
	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
	writel(reg, &mxc_ccm->CCGR3);
}
#endif
/***************************************************/

U_BOOT_CMD(
	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
	"display clocks",
	""
);
Commit	Line	Data
23608e23 JL	1	/*
	2	* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	5	*/
	6
	7	#include <common.h>
5a660169	8	#include <div64.h>
23608e23 JL	9	#include <asm/io.h>
	10	#include <asm/errno.h>
	11	#include <asm/arch/imx-regs.h>
6a376046	12	#include <asm/arch/crm_regs.h>
23608e23	13	#include <asm/arch/clock.h>
6a376046	14	#include <asm/arch/sys_proto.h>
23608e23 JL	15
	16	enum pll_clocks {
	17	PLL_SYS, /* System PLL */
	18	PLL_BUS, /* System Bus PLL*/
	19	PLL_USBOTG, /* OTG USB PLL */
	20	PLL_ENET, /* ENET PLL */
	21	};
	22
6a376046	23	struct mxc_ccm_reg imx_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
23608e23	24
112fd2ec BT	25	#ifdef CONFIG_MXC_OCOTP
	26	void enable_ocotp_clk(unsigned char enable)
	27	{
	28	u32 reg;
	29
	30	reg = __raw_readl(&imx_ccm->CCGR2);
	31	if (enable)
	32	reg \|= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
	33	else
	34	reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
	35	__raw_writel(reg, &imx_ccm->CCGR2);
	36	}
	37	#endif
	38
3f467529 WG	39	void enable_usboh3_clk(unsigned char enable)
	40	{
	41	u32 reg;
	42
	43	reg = __raw_readl(&imx_ccm->CCGR6);
	44	if (enable)
0bb7e316	45	reg \|= MXC_CCM_CCGR6_USBOH3_MASK;
3f467529	46	else
0bb7e316	47	reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
3f467529 WG	48	__raw_writel(reg, &imx_ccm->CCGR6);
	49
	50	}
	51
fac96408	52	#ifdef CONFIG_SYS_I2C_MXC
cc54a0f7 TK	53	/* i2c_num can be from 0 - 2 */
	54	int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
	55	{
	56	u32 reg;
	57	u32 mask;
	58
	59	if (i2c_num > 2)
	60	return -EINVAL;
0bb7e316 EN	61
	62	mask = MXC_CCM_CCGR_CG_MASK
	63	<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
cc54a0f7 TK	64	reg = __raw_readl(&imx_ccm->CCGR2);
	65	if (enable)
	66	reg \|= mask;
	67	else
	68	reg &= ~mask;
	69	__raw_writel(reg, &imx_ccm->CCGR2);
	70	return 0;
	71	}
	72	#endif
	73
a0ae0091 HS	74	/* spi_num can be from 0 - SPI_MAX_NUM */
	75	int enable_spi_clk(unsigned char enable, unsigned spi_num)
	76	{
	77	u32 reg;
	78	u32 mask;
	79
	80	if (spi_num > SPI_MAX_NUM)
	81	return -EINVAL;
	82
	83	mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
	84	reg = __raw_readl(&imx_ccm->CCGR1);
	85	if (enable)
	86	reg \|= mask;
	87	else
	88	reg &= ~mask;
	89	__raw_writel(reg, &imx_ccm->CCGR1);
	90	return 0;
	91	}
23608e23 JL	92	static u32 decode_pll(enum pll_clocks pll, u32 infreq)
	93	{
	94	u32 div;
	95
	96	switch (pll) {
	97	case PLL_SYS:
	98	div = __raw_readl(&imx_ccm->analog_pll_sys);
	99	div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
	100
2eb268f6	101	return (infreq * div) >> 1;
23608e23 JL	102	case PLL_BUS:
	103	div = __raw_readl(&imx_ccm->analog_pll_528);
	104	div &= BM_ANADIG_PLL_528_DIV_SELECT;
	105
	106	return infreq * (20 + (div << 1));
	107	case PLL_USBOTG:
	108	div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
	109	div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
	110
	111	return infreq * (20 + (div << 1));
	112	case PLL_ENET:
	113	div = __raw_readl(&imx_ccm->analog_pll_enet);
	114	div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
	115
89cfd0f5	116	return 25000000 * (div + (div >> 1) + 1);
23608e23 JL	117	default:
	118	return 0;
	119	}
	120	/* NOTREACHED */
	121	}
762a88cc PA	122	static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
	123	{
	124	u32 div;
	125	u64 freq;
	126
	127	switch (pll) {
	128	case PLL_BUS:
	129	if (pfd_num == 3) {
	130	/* No PFD3 on PPL2 */
	131	return 0;
	132	}
	133	div = __raw_readl(&imx_ccm->analog_pfd_528);
	134	freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
	135	break;
	136	case PLL_USBOTG:
	137	div = __raw_readl(&imx_ccm->analog_pfd_480);
	138	freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
	139	break;
	140	default:
	141	/* No PFD on other PLL */
	142	return 0;
	143	}
	144
5a660169	145	return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
762a88cc PA	146	ANATOP_PFD_FRAC_SHIFT(pfd_num));
762a88cc PA	147	}
23608e23 JL	148
	149	static u32 get_mcu_main_clk(void)
	150	{
	151	u32 reg, freq;
	152
	153	reg = __raw_readl(&imx_ccm->cacrr);
	154	reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
	155	reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
833b6435	156	freq = decode_pll(PLL_SYS, MXC_HCLK);
23608e23 JL	157
	158	return freq / (reg + 1);
	159	}
	160
6a376046	161	u32 get_periph_clk(void)
23608e23 JL	162	{
	163	u32 reg, freq = 0;
	164
	165	reg = __raw_readl(&imx_ccm->cbcdr);
	166	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
	167	reg = __raw_readl(&imx_ccm->cbcmr);
	168	reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
	169	reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
	170
	171	switch (reg) {
	172	case 0:
833b6435	173	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23 JL	174	break;
	175	case 1:
	176	case 2:
833b6435	177	freq = MXC_HCLK;
23608e23 JL	178	break;
	179	default:
	180	break;
	181	}
	182	} else {
	183	reg = __raw_readl(&imx_ccm->cbcmr);
	184	reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
	185	reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
	186
	187	switch (reg) {
	188	case 0:
833b6435	189	freq = decode_pll(PLL_BUS, MXC_HCLK);
23608e23 JL	190	break;
23608e23 JL	191	case 1:
762a88cc	192	freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23 JL	193	break;
23608e23 JL	194	case 2:
762a88cc	195	freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23 JL	196	break;
23608e23 JL	197	case 3:
762a88cc PA	198	/* static / 2 divider */
762a88cc PA	199	freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
23608e23 JL	200	break;
	201	default:
	202	break;
	203	}
	204	}
	205
	206	return freq;
	207	}
	208
23608e23 JL	209	static u32 get_ipg_clk(void)
	210	{
	211	u32 reg, ipg_podf;
	212
	213	reg = __raw_readl(&imx_ccm->cbcdr);
	214	reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
	215	ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
	216
	217	return get_ahb_clk() / (ipg_podf + 1);
	218	}
	219
	220	static u32 get_ipg_per_clk(void)
	221	{
	222	u32 reg, perclk_podf;
	223
	224	reg = __raw_readl(&imx_ccm->cscmr1);
	225	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
	226
	227	return get_ipg_clk() / (perclk_podf + 1);
	228	}
	229
	230	static u32 get_uart_clk(void)
	231	{
	232	u32 reg, uart_podf;
762a88cc	233	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
23608e23	234	reg = __raw_readl(&imx_ccm->cscdr1);
05d54b82	235	#if (defined(CONFIG_MX6SL) \|\| defined(CONFIG_MX6SX))
25b4aa14 FE	236	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
	237	freq = MXC_HCLK;
	238	#endif
23608e23 JL	239	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
	240	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
	241
25b4aa14	242	return freq / (uart_podf + 1);
23608e23 JL	243	}
	244
	245	static u32 get_cspi_clk(void)
	246	{
	247	u32 reg, cspi_podf;
	248
	249	reg = __raw_readl(&imx_ccm->cscdr2);
	250	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
	251	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
	252
762a88cc	253	return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
23608e23 JL	254	}
	255
	256	static u32 get_axi_clk(void)
	257	{
	258	u32 root_freq, axi_podf;
	259	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	260
	261	axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
	262	axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
	263
	264	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
	265	if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
762a88cc	266	root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23	267	else
762a88cc	268	root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
23608e23 JL	269	} else
	270	root_freq = get_periph_clk();
	271
	272	return root_freq / (axi_podf + 1);
	273	}
	274
	275	static u32 get_emi_slow_clk(void)
	276	{
d55e0dab	277	u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
23608e23 JL	278
	279	cscmr1 = __raw_readl(&imx_ccm->cscmr1);
	280	emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
	281	emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
d55e0dab AG	282	emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
d55e0dab AG	283	emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
23608e23 JL	284
	285	switch (emi_clk_sel) {
	286	case 0:
	287	root_freq = get_axi_clk();
	288	break;
	289	case 1:
833b6435	290	root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23 JL	291	break;
23608e23 JL	292	case 2:
762a88cc	293	root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23 JL	294	break;
23608e23 JL	295	case 3:
762a88cc	296	root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23 JL	297	break;
	298	}
	299
d55e0dab	300	return root_freq / (emi_slow_podf + 1);
23608e23 JL	301	}
23608e23 JL	302
05d54b82	303	#if (defined(CONFIG_MX6SL) \|\| defined(CONFIG_MX6SX))
25b4aa14 FE	304	static u32 get_mmdc_ch0_clk(void)
	305	{
	306	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
	307	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	308	u32 freq, podf;
	309
	310	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
	311	>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
	312
	313	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
	314	MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
	315	case 0:
	316	freq = decode_pll(PLL_BUS, MXC_HCLK);
	317	break;
	318	case 1:
762a88cc	319	freq = mxc_get_pll_pfd(PLL_BUS, 2);
25b4aa14 FE	320	break;
25b4aa14 FE	321	case 2:
762a88cc	322	freq = mxc_get_pll_pfd(PLL_BUS, 0);
25b4aa14 FE	323	break;
25b4aa14 FE	324	case 3:
762a88cc PA	325	/* static / 2 divider */
762a88cc PA	326	freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
25b4aa14 FE	327	}
	328
	329	return freq / (podf + 1);
	330
	331	}
c655b816 OS	332	#else
	333	static u32 get_mmdc_ch0_clk(void)
	334	{
	335	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	336	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
	337	MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
	338
	339	return get_periph_clk() / (mmdc_ch0_podf + 1);
	340	}
	341	#endif
31f07964	342
c655b816	343	#ifdef CONFIG_FEC_MXC
5f98d0b5	344	int enable_fec_anatop_clock(enum enet_freq freq)
31f07964 FE	345	{
	346	u32 reg = 0;
	347	s32 timeout = 100000;
	348
	349	struct anatop_regs __iomem *anatop =
	350	(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
	351
5f98d0b5 FE	352	if (freq < ENET_25MHz \|\| freq > ENET_125MHz)
	353	return -EINVAL;
	354
31f07964	355	reg = readl(&anatop->pll_enet);
5f98d0b5 FE	356	reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
	357	reg \|= freq;
	358
31f07964 FE	359	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) \|\|
	360	(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
	361	reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
	362	writel(reg, &anatop->pll_enet);
	363	while (timeout--) {
	364	if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
	365	break;
	366	}
	367	if (timeout < 0)
	368	return -ETIMEDOUT;
	369	}
	370
	371	/* Enable FEC clock */
	372	reg \|= BM_ANADIG_PLL_ENET_ENABLE;
	373	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
	374	writel(reg, &anatop->pll_enet);
	375
5c045cdd FE	376	#ifdef CONFIG_MX6SX
	377	/*
	378	* Set enet ahb clock to 200MHz
	379	* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
	380	*/
	381	reg = readl(&imx_ccm->chsccdr);
	382	reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
	383	\| MXC_CCM_CHSCCDR_ENET_PODF_MASK
	384	\| MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
	385	/* PLL2 PFD2 */
	386	reg \|= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
	387	/* Div = 2*/
	388	reg \|= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
	389	reg \|= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
	390	writel(reg, &imx_ccm->chsccdr);
	391
	392	/* Enable enet system clock */
	393	reg = readl(&imx_ccm->CCGR3);
	394	reg \|= MXC_CCM_CCGR3_ENET_MASK;
	395	writel(reg, &imx_ccm->CCGR3);
	396	#endif
31f07964 FE	397	return 0;
31f07964 FE	398	}
25b4aa14	399	#endif
23608e23 JL	400
	401	static u32 get_usdhc_clk(u32 port)
	402	{
	403	u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
	404	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
	405	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
	406
	407	switch (port) {
	408	case 0:
	409	usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
	410	MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
	411	clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
	412
	413	break;
	414	case 1:
	415	usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
	416	MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
	417	clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
	418
	419	break;
	420	case 2:
	421	usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
	422	MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
	423	clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
	424
	425	break;
	426	case 3:
	427	usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
	428	MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
	429	clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
	430
	431	break;
	432	default:
	433	break;
	434	}
	435
	436	if (clk_sel)
762a88cc	437	root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
23608e23	438	else
762a88cc	439	root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
23608e23 JL	440
	441	return root_freq / (usdhc_podf + 1);
	442	}
	443
	444	u32 imx_get_uartclk(void)
	445	{
	446	return get_uart_clk();
	447	}
	448
ff167df5 JL	449	u32 imx_get_fecclk(void)
ff167df5 JL	450	{
adadc915	451	return mxc_get_clock(MXC_IPG_CLK);
ff167df5 JL	452	}
ff167df5 JL	453
79814492	454	static int enable_enet_pll(uint32_t en)
64e7cdb5	455	{
64e7cdb5 EN	456	struct mxc_ccm_reg *const imx_ccm
64e7cdb5 EN	457	= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
79814492 MV	458	s32 timeout = 100000;
79814492 MV	459	u32 reg = 0;
64e7cdb5 EN	460
	461	/* Enable PLLs */
	462	reg = readl(&imx_ccm->analog_pll_enet);
	463	reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
	464	writel(reg, &imx_ccm->analog_pll_enet);
	465	reg \|= BM_ANADIG_PLL_SYS_ENABLE;
	466	while (timeout--) {
	467	if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
	468	break;
	469	}
	470	if (timeout <= 0)
	471	return -EIO;
	472	reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
	473	writel(reg, &imx_ccm->analog_pll_enet);
79814492	474	reg \|= en;
64e7cdb5	475	writel(reg, &imx_ccm->analog_pll_enet);
79814492 MV	476	return 0;
79814492 MV	477	}
64e7cdb5	478
d95b6ab8	479	#ifndef CONFIG_MX6SX
79814492 MV	480	static void ungate_sata_clock(void)
	481	{
	482	struct mxc_ccm_reg *const imx_ccm =
	483	(struct mxc_ccm_reg *)CCM_BASE_ADDR;
	484
	485	/* Enable SATA clock. */
	486	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
	487	}
d95b6ab8	488	#endif
79814492 MV	489
	490	static void ungate_pcie_clock(void)
	491	{
	492	struct mxc_ccm_reg *const imx_ccm =
	493	(struct mxc_ccm_reg *)CCM_BASE_ADDR;
	494
	495	/* Enable PCIe clock. */
	496	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
	497	}
	498
d95b6ab8	499	#ifndef CONFIG_MX6SX
79814492 MV	500	int enable_sata_clock(void)
	501	{
	502	ungate_sata_clock();
	503	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
	504	}
d95b6ab8	505	#endif
79814492 MV	506
	507	int enable_pcie_clock(void)
	508	{
	509	struct anatop_regs *anatop_regs =
	510	(struct anatop_regs *)ANATOP_BASE_ADDR;
	511	struct mxc_ccm_reg ccm_regs = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	512
	513	/*
	514	* Here be dragons!
	515	*
	516	* The register ANATOP_MISC1 is not documented in the Freescale
	517	* MX6RM. The register that is mapped in the ANATOP space and
	518	* marked as ANATOP_MISC1 is actually documented in the PMU section
	519	* of the datasheet as PMU_MISC1.
	520	*
	521	* Switch LVDS clock source to SATA (0xb), disable clock INPUT and
	522	* enable clock OUTPUT. This is important for PCI express link that
	523	* is clocked from the i.MX6.
	524	*/
	525	#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
	526	#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
	527	#define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
	528	clrsetbits_le32(&anatop_regs->ana_misc1,
	529	ANADIG_ANA_MISC1_LVDSCLK1_IBEN \|
	530	ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
	531	ANADIG_ANA_MISC1_LVDSCLK1_OBEN \| 0xb);
	532
	533	/* PCIe reference clock sourced from AXI. */
	534	clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
	535
	536	/* Party time! Ungate the clock to the PCIe. */
d95b6ab8	537	#ifndef CONFIG_MX6SX
79814492	538	ungate_sata_clock();
d95b6ab8	539	#endif
79814492 MV	540	ungate_pcie_clock();
	541
	542	return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA \|
	543	BM_ANADIG_PLL_ENET_ENABLE_PCIE);
64e7cdb5 EN	544	}
64e7cdb5 EN	545
23608e23 JL	546	unsigned int mxc_get_clock(enum mxc_clock clk)
	547	{
	548	switch (clk) {
	549	case MXC_ARM_CLK:
	550	return get_mcu_main_clk();
	551	case MXC_PER_CLK:
	552	return get_periph_clk();
	553	case MXC_AHB_CLK:
	554	return get_ahb_clk();
	555	case MXC_IPG_CLK:
	556	return get_ipg_clk();
	557	case MXC_IPG_PERCLK:
e7bed5c2	558	case MXC_I2C_CLK:
23608e23 JL	559	return get_ipg_per_clk();
	560	case MXC_UART_CLK:
	561	return get_uart_clk();
	562	case MXC_CSPI_CLK:
	563	return get_cspi_clk();
	564	case MXC_AXI_CLK:
	565	return get_axi_clk();
	566	case MXC_EMI_SLOW_CLK:
	567	return get_emi_slow_clk();
	568	case MXC_DDR_CLK:
	569	return get_mmdc_ch0_clk();
	570	case MXC_ESDHC_CLK:
	571	return get_usdhc_clk(0);
	572	case MXC_ESDHC2_CLK:
	573	return get_usdhc_clk(1);
	574	case MXC_ESDHC3_CLK:
	575	return get_usdhc_clk(2);
	576	case MXC_ESDHC4_CLK:
	577	return get_usdhc_clk(3);
	578	case MXC_SATA_CLK:
	579	return get_ahb_clk();
	580	default:
	581	break;
	582	}
	583
	584	return -1;
	585	}
	586
	587	/*
	588	* Dump some core clockes.
	589	*/
	590	int do_mx6_showclocks(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	591	{
	592	u32 freq;
833b6435	593	freq = decode_pll(PLL_SYS, MXC_HCLK);
23608e23	594	printf("PLL_SYS %8d MHz\n", freq / 1000000);
833b6435	595	freq = decode_pll(PLL_BUS, MXC_HCLK);
23608e23	596	printf("PLL_BUS %8d MHz\n", freq / 1000000);
833b6435	597	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23	598	printf("PLL_OTG %8d MHz\n", freq / 1000000);
833b6435	599	freq = decode_pll(PLL_ENET, MXC_HCLK);
23608e23 JL	600	printf("PLL_NET %8d MHz\n", freq / 1000000);
	601
	602	printf("\n");
	603	printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
	604	printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
cc446726	605	#ifdef CONFIG_MXC_SPI
23608e23	606	printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
cc446726	607	#endif
23608e23 JL	608	printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
	609	printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
	610	printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
	611	printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
	612	printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
	613	printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
	614	printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
	615	printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
	616	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
	617
	618	return 0;
	619	}
	620
d95b6ab8	621	#ifndef CONFIG_MX6SX
5ea7f0e3 PKS	622	void enable_ipu_clock(void)
	623	{
	624	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	625	int reg;
	626	reg = readl(&mxc_ccm->CCGR3);
a0a0dacf	627	reg \|= MXC_CCM_CCGR3_IPU1_IPU_MASK;
5ea7f0e3 PKS	628	writel(reg, &mxc_ccm->CCGR3);
5ea7f0e3 PKS	629	}
d95b6ab8	630	#endif
23608e23 JL	631	/***************************************************/
	632
	633	U_BOOT_CMD(
	634	clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
	635	"display clocks",
	636	""
	637	);