[people/ms/u-boot.git] / arch / arm / cpu / armv7 / mx6 / clock.c

/*
 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>

enum pll_clocks {
	PLL_SYS,	/* System PLL */
	PLL_BUS,	/* System Bus PLL*/
	PLL_USBOTG,	/* OTG USB PLL */
	PLL_ENET,	/* ENET PLL */
};

struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable)
{
	u32 reg;

	reg = __raw_readl(&imx_ccm->CCGR2);
	if (enable)
		reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
	else
		reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
	__raw_writel(reg, &imx_ccm->CCGR2);
}
#endif

void enable_usboh3_clk(unsigned char enable)
{
	u32 reg;

	reg = __raw_readl(&imx_ccm->CCGR6);
	if (enable)
		reg |= MXC_CCM_CCGR6_USBOH3_MASK;
	else
		reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
	__raw_writel(reg, &imx_ccm->CCGR6);

}

#ifdef CONFIG_SYS_I2C_MXC
/* i2c_num can be from 0 - 2 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
	u32 reg;
	u32 mask;

	if (i2c_num > 2)
		return -EINVAL;

	mask = MXC_CCM_CCGR_CG_MASK
		<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
	reg = __raw_readl(&imx_ccm->CCGR2);
	if (enable)
		reg |= mask;
	else
		reg &= ~mask;
	__raw_writel(reg, &imx_ccm->CCGR2);
	return 0;
}
#endif

static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
	u32 div;

	switch (pll) {
	case PLL_SYS:
		div = __raw_readl(&imx_ccm->analog_pll_sys);
		div &= BM_ANADIG_PLL_SYS_DIV_SELECT;

		return infreq * (div >> 1);
	case PLL_BUS:
		div = __raw_readl(&imx_ccm->analog_pll_528);
		div &= BM_ANADIG_PLL_528_DIV_SELECT;

		return infreq * (20 + (div << 1));
	case PLL_USBOTG:
		div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
		div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;

		return infreq * (20 + (div << 1));
	case PLL_ENET:
		div = __raw_readl(&imx_ccm->analog_pll_enet);
		div &= BM_ANADIG_PLL_ENET_DIV_SELECT;

		return (div == 3 ? 125000000 : 25000000 * (div << 1));
	default:
		return 0;
	}
	/* NOTREACHED */
}

static u32 get_mcu_main_clk(void)
{
	u32 reg, freq;

	reg = __raw_readl(&imx_ccm->cacrr);
	reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
	reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
	freq = decode_pll(PLL_SYS, MXC_HCLK);

	return freq / (reg + 1);
}

u32 get_periph_clk(void)
{
	u32 reg, freq = 0;

	reg = __raw_readl(&imx_ccm->cbcdr);
	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
		reg = __raw_readl(&imx_ccm->cbcmr);
		reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
		reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;

		switch (reg) {
		case 0:
			freq = decode_pll(PLL_USBOTG, MXC_HCLK);
			break;
		case 1:
		case 2:
			freq = MXC_HCLK;
			break;
		default:
			break;
		}
	} else {
		reg = __raw_readl(&imx_ccm->cbcmr);
		reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
		reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;

		switch (reg) {
		case 0:
			freq = decode_pll(PLL_BUS, MXC_HCLK);
			break;
		case 1:
			freq = PLL2_PFD2_FREQ;
			break;
		case 2:
			freq = PLL2_PFD0_FREQ;
			break;
		case 3:
			freq = PLL2_PFD2_DIV_FREQ;
			break;
		default:
			break;
		}
	}

	return freq;
}

static u32 get_ipg_clk(void)
{
	u32 reg, ipg_podf;

	reg = __raw_readl(&imx_ccm->cbcdr);
	reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
	ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;

	return get_ahb_clk() / (ipg_podf + 1);
}

static u32 get_ipg_per_clk(void)
{
	u32 reg, perclk_podf;

	reg = __raw_readl(&imx_ccm->cscmr1);
	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;

	return get_ipg_clk() / (perclk_podf + 1);
}

static u32 get_uart_clk(void)
{
	u32 reg, uart_podf;
	u32 freq = PLL3_80M;
	reg = __raw_readl(&imx_ccm->cscdr1);
#ifdef CONFIG_MX6SL
	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
		freq = MXC_HCLK;
#endif
	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;

	return freq / (uart_podf + 1);
}

static u32 get_cspi_clk(void)
{
	u32 reg, cspi_podf;

	reg = __raw_readl(&imx_ccm->cscdr2);
	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;

	return	PLL3_60M / (cspi_podf + 1);
}

static u32 get_axi_clk(void)
{
	u32 root_freq, axi_podf;
	u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);

	axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
	axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;

	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
		if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
			root_freq = PLL2_PFD2_FREQ;
		else
			root_freq = PLL3_PFD1_FREQ;
	} else
		root_freq = get_periph_clk();

	return  root_freq / (axi_podf + 1);
}

static u32 get_emi_slow_clk(void)
{
	u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;

	cscmr1 =  __raw_readl(&imx_ccm->cscmr1);
	emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
	emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
	emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
	emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;

	switch (emi_clk_sel) {
	case 0:
		root_freq = get_axi_clk();
		break;
	case 1:
		root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
		break;
	case 2:
		root_freq = PLL2_PFD2_FREQ;
		break;
	case 3:
		root_freq = PLL2_PFD0_FREQ;
		break;
	}

	return root_freq / (emi_slow_podf + 1);
}

#ifdef CONFIG_MX6SL
static u32 get_mmdc_ch0_clk(void)
{
	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	u32 freq, podf;

	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
			>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;

	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
		MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
	case 0:
		freq = decode_pll(PLL_BUS, MXC_HCLK);
		break;
	case 1:
		freq = PLL2_PFD2_FREQ;
		break;
	case 2:
		freq = PLL2_PFD0_FREQ;
		break;
	case 3:
		freq = PLL2_PFD2_DIV_FREQ;
	}

	return freq / (podf + 1);

}

int enable_fec_anatop_clock(void)
{
	u32 reg = 0;
	s32 timeout = 100000;

	struct anatop_regs __iomem *anatop =
		(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;

	reg = readl(&anatop->pll_enet);
	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
		reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
		writel(reg, &anatop->pll_enet);
		while (timeout--) {
			if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
				break;
		}
		if (timeout < 0)
			return -ETIMEDOUT;
	}

	/* Enable FEC clock */
	reg |= BM_ANADIG_PLL_ENET_ENABLE;
	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
	writel(reg, &anatop->pll_enet);

	return 0;
}

#else
static u32 get_mmdc_ch0_clk(void)
{
	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
				MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;

	return get_periph_clk() / (mmdc_ch0_podf + 1);
}
#endif

static u32 get_usdhc_clk(u32 port)
{
	u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);

	switch (port) {
	case 0:
		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
					MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;

		break;
	case 1:
		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
					MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;

		break;
	case 2:
		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
					MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;

		break;
	case 3:
		usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
					MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
		clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;

		break;
	default:
		break;
	}

	if (clk_sel)
		root_freq = PLL2_PFD0_FREQ;
	else
		root_freq = PLL2_PFD2_FREQ;

	return root_freq / (usdhc_podf + 1);
}

u32 imx_get_uartclk(void)
{
	return get_uart_clk();
}

u32 imx_get_fecclk(void)
{
	return decode_pll(PLL_ENET, MXC_HCLK);
}

int enable_sata_clock(void)
{
	u32 reg = 0;
	s32 timeout = 100000;
	struct mxc_ccm_reg *const imx_ccm
		= (struct mxc_ccm_reg *) CCM_BASE_ADDR;

	/* Enable sata clock */
	reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
	reg |= MXC_CCM_CCGR5_SATA_MASK;
	writel(reg, &imx_ccm->CCGR5);

	/* Enable PLLs */
	reg = readl(&imx_ccm->analog_pll_enet);
	reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
	writel(reg, &imx_ccm->analog_pll_enet);
	reg |= BM_ANADIG_PLL_SYS_ENABLE;
	while (timeout--) {
		if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
			break;
	}
	if (timeout <= 0)
		return -EIO;
	reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
	writel(reg, &imx_ccm->analog_pll_enet);
	reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
	writel(reg, &imx_ccm->analog_pll_enet);

	return 0 ;
}

unsigned int mxc_get_clock(enum mxc_clock clk)
{
	switch (clk) {
	case MXC_ARM_CLK:
		return get_mcu_main_clk();
	case MXC_PER_CLK:
		return get_periph_clk();
	case MXC_AHB_CLK:
		return get_ahb_clk();
	case MXC_IPG_CLK:
		return get_ipg_clk();
	case MXC_IPG_PERCLK:
	case MXC_I2C_CLK:
		return get_ipg_per_clk();
	case MXC_UART_CLK:
		return get_uart_clk();
	case MXC_CSPI_CLK:
		return get_cspi_clk();
	case MXC_AXI_CLK:
		return get_axi_clk();
	case MXC_EMI_SLOW_CLK:
		return get_emi_slow_clk();
	case MXC_DDR_CLK:
		return get_mmdc_ch0_clk();
	case MXC_ESDHC_CLK:
		return get_usdhc_clk(0);
	case MXC_ESDHC2_CLK:
		return get_usdhc_clk(1);
	case MXC_ESDHC3_CLK:
		return get_usdhc_clk(2);
	case MXC_ESDHC4_CLK:
		return get_usdhc_clk(3);
	case MXC_SATA_CLK:
		return get_ahb_clk();
	default:
		break;
	}

	return -1;
}

/*
 * Dump some core clockes.
 */
int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	u32 freq;
	freq = decode_pll(PLL_SYS, MXC_HCLK);
	printf("PLL_SYS    %8d MHz\n", freq / 1000000);
	freq = decode_pll(PLL_BUS, MXC_HCLK);
	printf("PLL_BUS    %8d MHz\n", freq / 1000000);
	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
	printf("PLL_OTG    %8d MHz\n", freq / 1000000);
	freq = decode_pll(PLL_ENET, MXC_HCLK);
	printf("PLL_NET    %8d MHz\n", freq / 1000000);

	printf("\n");
	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
	printf("UART       %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
#ifdef CONFIG_MXC_SPI
	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
#endif
	printf("AHB        %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
	printf("AXI        %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
	printf("USDHC1     %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
	printf("USDHC2     %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
	printf("USDHC3     %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
	printf("USDHC4     %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
	printf("EMI SLOW   %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);

	return 0;
}

void enable_ipu_clock(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	int reg;
	reg = readl(&mxc_ccm->CCGR3);
	reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
	writel(reg, &mxc_ccm->CCGR3);
}
/***************************************************/

U_BOOT_CMD(
	clocks,	CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
	"display clocks",
	""
);
Commit	Line	Data
23608e23 JL	1	/*
	2	* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
23608e23 JL	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <asm/errno.h>
	10	#include <asm/arch/imx-regs.h>
6a376046	11	#include <asm/arch/crm_regs.h>
23608e23	12	#include <asm/arch/clock.h>
6a376046	13	#include <asm/arch/sys_proto.h>
23608e23 JL	14
	15	enum pll_clocks {
	16	PLL_SYS, /* System PLL */
	17	PLL_BUS, /* System Bus PLL*/
	18	PLL_USBOTG, /* OTG USB PLL */
	19	PLL_ENET, /* ENET PLL */
	20	};
	21
6a376046	22	struct mxc_ccm_reg imx_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
23608e23	23
112fd2ec BT	24	#ifdef CONFIG_MXC_OCOTP
	25	void enable_ocotp_clk(unsigned char enable)
	26	{
	27	u32 reg;
	28
	29	reg = __raw_readl(&imx_ccm->CCGR2);
	30	if (enable)
	31	reg \|= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
	32	else
	33	reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
	34	__raw_writel(reg, &imx_ccm->CCGR2);
	35	}
	36	#endif
	37
3f467529 WG	38	void enable_usboh3_clk(unsigned char enable)
	39	{
	40	u32 reg;
	41
	42	reg = __raw_readl(&imx_ccm->CCGR6);
	43	if (enable)
0bb7e316	44	reg \|= MXC_CCM_CCGR6_USBOH3_MASK;
3f467529	45	else
0bb7e316	46	reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
3f467529 WG	47	__raw_writel(reg, &imx_ccm->CCGR6);
	48
	49	}
	50
fac96408	51	#ifdef CONFIG_SYS_I2C_MXC
cc54a0f7 TK	52	/* i2c_num can be from 0 - 2 */
	53	int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
	54	{
	55	u32 reg;
	56	u32 mask;
	57
	58	if (i2c_num > 2)
	59	return -EINVAL;
0bb7e316 EN	60
	61	mask = MXC_CCM_CCGR_CG_MASK
	62	<< (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
cc54a0f7 TK	63	reg = __raw_readl(&imx_ccm->CCGR2);
	64	if (enable)
	65	reg \|= mask;
	66	else
	67	reg &= ~mask;
	68	__raw_writel(reg, &imx_ccm->CCGR2);
	69	return 0;
	70	}
	71	#endif
	72
23608e23 JL	73	static u32 decode_pll(enum pll_clocks pll, u32 infreq)
	74	{
	75	u32 div;
	76
	77	switch (pll) {
	78	case PLL_SYS:
	79	div = __raw_readl(&imx_ccm->analog_pll_sys);
	80	div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
	81
	82	return infreq * (div >> 1);
	83	case PLL_BUS:
	84	div = __raw_readl(&imx_ccm->analog_pll_528);
	85	div &= BM_ANADIG_PLL_528_DIV_SELECT;
	86
	87	return infreq * (20 + (div << 1));
	88	case PLL_USBOTG:
	89	div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
	90	div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
	91
	92	return infreq * (20 + (div << 1));
	93	case PLL_ENET:
	94	div = __raw_readl(&imx_ccm->analog_pll_enet);
	95	div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
	96
	97	return (div == 3 ? 125000000 : 25000000 * (div << 1));
	98	default:
	99	return 0;
	100	}
	101	/* NOTREACHED */
	102	}
	103
	104	static u32 get_mcu_main_clk(void)
	105	{
	106	u32 reg, freq;
	107
	108	reg = __raw_readl(&imx_ccm->cacrr);
	109	reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
	110	reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
833b6435	111	freq = decode_pll(PLL_SYS, MXC_HCLK);
23608e23 JL	112
	113	return freq / (reg + 1);
	114	}
	115
6a376046	116	u32 get_periph_clk(void)
23608e23 JL	117	{
	118	u32 reg, freq = 0;
	119
	120	reg = __raw_readl(&imx_ccm->cbcdr);
	121	if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
	122	reg = __raw_readl(&imx_ccm->cbcmr);
	123	reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
	124	reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
	125
	126	switch (reg) {
	127	case 0:
833b6435	128	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23 JL	129	break;
	130	case 1:
	131	case 2:
833b6435	132	freq = MXC_HCLK;
23608e23 JL	133	break;
	134	default:
	135	break;
	136	}
	137	} else {
	138	reg = __raw_readl(&imx_ccm->cbcmr);
	139	reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
	140	reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
	141
	142	switch (reg) {
	143	case 0:
833b6435	144	freq = decode_pll(PLL_BUS, MXC_HCLK);
23608e23 JL	145	break;
	146	case 1:
	147	freq = PLL2_PFD2_FREQ;
	148	break;
	149	case 2:
	150	freq = PLL2_PFD0_FREQ;
	151	break;
	152	case 3:
	153	freq = PLL2_PFD2_DIV_FREQ;
	154	break;
	155	default:
	156	break;
	157	}
	158	}
	159
	160	return freq;
	161	}
	162
23608e23 JL	163	static u32 get_ipg_clk(void)
	164	{
	165	u32 reg, ipg_podf;
	166
	167	reg = __raw_readl(&imx_ccm->cbcdr);
	168	reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
	169	ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
	170
	171	return get_ahb_clk() / (ipg_podf + 1);
	172	}
	173
	174	static u32 get_ipg_per_clk(void)
	175	{
	176	u32 reg, perclk_podf;
	177
	178	reg = __raw_readl(&imx_ccm->cscmr1);
	179	perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
	180
	181	return get_ipg_clk() / (perclk_podf + 1);
	182	}
	183
	184	static u32 get_uart_clk(void)
	185	{
	186	u32 reg, uart_podf;
25b4aa14	187	u32 freq = PLL3_80M;
23608e23	188	reg = __raw_readl(&imx_ccm->cscdr1);
25b4aa14 FE	189	#ifdef CONFIG_MX6SL
	190	if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
	191	freq = MXC_HCLK;
	192	#endif
23608e23 JL	193	reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
	194	uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
	195
25b4aa14	196	return freq / (uart_podf + 1);
23608e23 JL	197	}
	198
	199	static u32 get_cspi_clk(void)
	200	{
	201	u32 reg, cspi_podf;
	202
	203	reg = __raw_readl(&imx_ccm->cscdr2);
	204	reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
	205	cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
	206
	207	return PLL3_60M / (cspi_podf + 1);
	208	}
	209
	210	static u32 get_axi_clk(void)
	211	{
	212	u32 root_freq, axi_podf;
	213	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	214
	215	axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
	216	axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
	217
	218	if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
	219	if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
	220	root_freq = PLL2_PFD2_FREQ;
	221	else
	222	root_freq = PLL3_PFD1_FREQ;
	223	} else
	224	root_freq = get_periph_clk();
	225
	226	return root_freq / (axi_podf + 1);
	227	}
	228
	229	static u32 get_emi_slow_clk(void)
	230	{
d55e0dab	231	u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
23608e23 JL	232
	233	cscmr1 = __raw_readl(&imx_ccm->cscmr1);
	234	emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
	235	emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
d55e0dab AG	236	emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
d55e0dab AG	237	emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
23608e23 JL	238
	239	switch (emi_clk_sel) {
	240	case 0:
	241	root_freq = get_axi_clk();
	242	break;
	243	case 1:
833b6435	244	root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23 JL	245	break;
	246	case 2:
	247	root_freq = PLL2_PFD2_FREQ;
	248	break;
	249	case 3:
	250	root_freq = PLL2_PFD0_FREQ;
	251	break;
	252	}
	253
d55e0dab	254	return root_freq / (emi_slow_podf + 1);
23608e23 JL	255	}
23608e23 JL	256
25b4aa14 FE	257	#ifdef CONFIG_MX6SL
	258	static u32 get_mmdc_ch0_clk(void)
	259	{
	260	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
	261	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	262	u32 freq, podf;
	263
	264	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
	265	>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
	266
	267	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
	268	MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
	269	case 0:
	270	freq = decode_pll(PLL_BUS, MXC_HCLK);
	271	break;
	272	case 1:
	273	freq = PLL2_PFD2_FREQ;
	274	break;
	275	case 2:
	276	freq = PLL2_PFD0_FREQ;
	277	break;
	278	case 3:
	279	freq = PLL2_PFD2_DIV_FREQ;
	280	}
	281
	282	return freq / (podf + 1);
	283
	284	}
31f07964 FE	285
	286	int enable_fec_anatop_clock(void)
	287	{
	288	u32 reg = 0;
	289	s32 timeout = 100000;
	290
	291	struct anatop_regs __iomem *anatop =
	292	(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
	293
	294	reg = readl(&anatop->pll_enet);
	295	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) \|\|
	296	(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
	297	reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
	298	writel(reg, &anatop->pll_enet);
	299	while (timeout--) {
	300	if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
	301	break;
	302	}
	303	if (timeout < 0)
	304	return -ETIMEDOUT;
	305	}
	306
	307	/* Enable FEC clock */
	308	reg \|= BM_ANADIG_PLL_ENET_ENABLE;
	309	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
	310	writel(reg, &anatop->pll_enet);
	311
	312	return 0;
	313	}
	314
25b4aa14	315	#else
23608e23 JL	316	static u32 get_mmdc_ch0_clk(void)
	317	{
	318	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
	319	u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
	320	MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
	321
	322	return get_periph_clk() / (mmdc_ch0_podf + 1);
	323	}
25b4aa14	324	#endif
23608e23 JL	325
	326	static u32 get_usdhc_clk(u32 port)
	327	{
	328	u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
	329	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
	330	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
	331
	332	switch (port) {
	333	case 0:
	334	usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
	335	MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
	336	clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
	337
	338	break;
	339	case 1:
	340	usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
	341	MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
	342	clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
	343
	344	break;
	345	case 2:
	346	usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
	347	MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
	348	clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
	349
	350	break;
	351	case 3:
	352	usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
	353	MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
	354	clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
	355
	356	break;
	357	default:
	358	break;
	359	}
	360
	361	if (clk_sel)
	362	root_freq = PLL2_PFD0_FREQ;
	363	else
	364	root_freq = PLL2_PFD2_FREQ;
	365
	366	return root_freq / (usdhc_podf + 1);
	367	}
	368
	369	u32 imx_get_uartclk(void)
	370	{
	371	return get_uart_clk();
	372	}
	373
ff167df5 JL	374	u32 imx_get_fecclk(void)
ff167df5 JL	375	{
833b6435	376	return decode_pll(PLL_ENET, MXC_HCLK);
ff167df5 JL	377	}
ff167df5 JL	378
64e7cdb5 EN	379	int enable_sata_clock(void)
	380	{
	381	u32 reg = 0;
	382	s32 timeout = 100000;
	383	struct mxc_ccm_reg *const imx_ccm
	384	= (struct mxc_ccm_reg *) CCM_BASE_ADDR;
	385
	386	/* Enable sata clock */
	387	reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
0bb7e316	388	reg \|= MXC_CCM_CCGR5_SATA_MASK;
64e7cdb5 EN	389	writel(reg, &imx_ccm->CCGR5);
	390
	391	/* Enable PLLs */
	392	reg = readl(&imx_ccm->analog_pll_enet);
	393	reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
	394	writel(reg, &imx_ccm->analog_pll_enet);
	395	reg \|= BM_ANADIG_PLL_SYS_ENABLE;
	396	while (timeout--) {
	397	if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
	398	break;
	399	}
	400	if (timeout <= 0)
	401	return -EIO;
	402	reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
	403	writel(reg, &imx_ccm->analog_pll_enet);
	404	reg \|= BM_ANADIG_PLL_ENET_ENABLE_SATA;
	405	writel(reg, &imx_ccm->analog_pll_enet);
	406
	407	return 0 ;
	408	}
	409
23608e23 JL	410	unsigned int mxc_get_clock(enum mxc_clock clk)
	411	{
	412	switch (clk) {
	413	case MXC_ARM_CLK:
	414	return get_mcu_main_clk();
	415	case MXC_PER_CLK:
	416	return get_periph_clk();
	417	case MXC_AHB_CLK:
	418	return get_ahb_clk();
	419	case MXC_IPG_CLK:
	420	return get_ipg_clk();
	421	case MXC_IPG_PERCLK:
e7bed5c2	422	case MXC_I2C_CLK:
23608e23 JL	423	return get_ipg_per_clk();
	424	case MXC_UART_CLK:
	425	return get_uart_clk();
	426	case MXC_CSPI_CLK:
	427	return get_cspi_clk();
	428	case MXC_AXI_CLK:
	429	return get_axi_clk();
	430	case MXC_EMI_SLOW_CLK:
	431	return get_emi_slow_clk();
	432	case MXC_DDR_CLK:
	433	return get_mmdc_ch0_clk();
	434	case MXC_ESDHC_CLK:
	435	return get_usdhc_clk(0);
	436	case MXC_ESDHC2_CLK:
	437	return get_usdhc_clk(1);
	438	case MXC_ESDHC3_CLK:
	439	return get_usdhc_clk(2);
	440	case MXC_ESDHC4_CLK:
	441	return get_usdhc_clk(3);
	442	case MXC_SATA_CLK:
	443	return get_ahb_clk();
	444	default:
	445	break;
	446	}
	447
	448	return -1;
	449	}
	450
	451	/*
	452	* Dump some core clockes.
	453	*/
	454	int do_mx6_showclocks(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	455	{
	456	u32 freq;
833b6435	457	freq = decode_pll(PLL_SYS, MXC_HCLK);
23608e23	458	printf("PLL_SYS %8d MHz\n", freq / 1000000);
833b6435	459	freq = decode_pll(PLL_BUS, MXC_HCLK);
23608e23	460	printf("PLL_BUS %8d MHz\n", freq / 1000000);
833b6435	461	freq = decode_pll(PLL_USBOTG, MXC_HCLK);
23608e23	462	printf("PLL_OTG %8d MHz\n", freq / 1000000);
833b6435	463	freq = decode_pll(PLL_ENET, MXC_HCLK);
23608e23 JL	464	printf("PLL_NET %8d MHz\n", freq / 1000000);
	465
	466	printf("\n");
	467	printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
	468	printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
cc446726	469	#ifdef CONFIG_MXC_SPI
23608e23	470	printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
cc446726	471	#endif
23608e23 JL	472	printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
	473	printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
	474	printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
	475	printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
	476	printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
	477	printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
	478	printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
	479	printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
	480	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
	481
	482	return 0;
	483	}
	484
5ea7f0e3 PKS	485	void enable_ipu_clock(void)
	486	{
	487	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	488	int reg;
	489	reg = readl(&mxc_ccm->CCGR3);
a0a0dacf	490	reg \|= MXC_CCM_CCGR3_IPU1_IPU_MASK;
5ea7f0e3 PKS	491	writel(reg, &mxc_ccm->CCGR3);
5ea7f0e3 PKS	492	}
23608e23 JL	493	/***************************************************/
	494
	495	U_BOOT_CMD(
	496	clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
	497	"display clocks",
	498	""
	499	);