[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap3 / sys_info.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Manikandan Pillai <mani.pillai@ti.com>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <r-woodruff2@ti.com>
 *      Syed Mohammed Khasim <khasim@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/mem.h>	/* get mem tables */
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <linux/compiler.h>

extern omap3_sysinfo sysinfo;
static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;

#ifdef CONFIG_DISPLAY_CPUINFO
static char *rev_s[CPU_3XX_MAX_REV] = {
				"1.0",
				"2.0",
				"2.1",
				"3.0",
				"3.1",
				"UNKNOWN",
				"UNKNOWN",
				"3.1.2"};

/* this is the revision table for 37xx CPUs */
static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
				"1.0",
				"1.1",
				"1.2"};
#endif /* CONFIG_DISPLAY_CPUINFO */

/*****************************************************************
 * dieid_num_r(void) - read and set die ID
 *****************************************************************/
void dieid_num_r(void)
{
	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
	char *uid_s, die_id[34];
	u32 id[4];

	memset(die_id, 0, sizeof(die_id));

	uid_s = getenv("dieid#");

	if (uid_s == NULL) {
		id[3] = readl(&id_base->die_id_0);
		id[2] = readl(&id_base->die_id_1);
		id[1] = readl(&id_base->die_id_2);
		id[0] = readl(&id_base->die_id_3);
		sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
		setenv("dieid#", die_id);
		uid_s = die_id;
	}

	printf("Die ID #%s\n", uid_s);
}

/******************************************
 * get_cpu_type(void) - extract cpu info
 ******************************************/
u32 get_cpu_type(void)
{
	return readl(&ctrl_base->ctrl_omap_stat);
}

/******************************************
 * get_cpu_id(void) - extract cpu id
 * returns 0 for ES1.0, cpuid otherwise
 ******************************************/
u32 get_cpu_id(void)
{
	struct ctrl_id *id_base;
	u32 cpuid = 0;

	/*
	 * On ES1.0 the IDCODE register is not exposed on L4
	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
	 */
	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
	if ((cpuid & 0xf) == 0x0) {
		return 0;
	} else {
		/* Decode the IDs on > ES1.0 */
		id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;

		cpuid = readl(&id_base->idcode);
	}

	return cpuid;
}

/******************************************
 * get_cpu_family(void) - extract cpu info
 ******************************************/
u32 get_cpu_family(void)
{
	u16 hawkeye;
	u32 cpu_family;
	u32 cpuid = get_cpu_id();

	if (cpuid == 0)
		return CPU_OMAP34XX;

	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
	switch (hawkeye) {
	case HAWKEYE_OMAP34XX:
		cpu_family = CPU_OMAP34XX;
		break;
	case HAWKEYE_AM35XX:
		cpu_family = CPU_AM35XX;
		break;
	case HAWKEYE_OMAP36XX:
		cpu_family = CPU_OMAP36XX;
		break;
	default:
		cpu_family = CPU_OMAP34XX;
	}

	return cpu_family;
}

/******************************************
 * get_cpu_rev(void) - extract version info
 ******************************************/
u32 get_cpu_rev(void)
{
	u32 cpuid = get_cpu_id();

	if (cpuid == 0)
		return CPU_3XX_ES10;
	else
		return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
}

/*****************************************************************
 * get_sku_id(void) - read sku_id to get info on max clock rate
 *****************************************************************/
u32 get_sku_id(void)
{
	struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
	return readl(&id_base->sku_id) & SKUID_CLK_MASK;
}

/***************************************************************************
 *  get_gpmc0_base() - Return current address hardware will be
 *     fetching from. The below effectively gives what is correct, its a bit
 *   mis-leading compared to the TRM.  For the most general case the mask
 *   needs to be also taken into account this does work in practice.
 *   - for u-boot we currently map:
 *       -- 0 to nothing,
 *       -- 4 to flash
 *       -- 8 to enent
 *       -- c to wifi
 ****************************************************************************/
u32 get_gpmc0_base(void)
{
	u32 b;

	b = readl(&gpmc_cfg->cs[0].config7);
	b &= 0x1F;		/* keep base [5:0] */
	b = b << 24;		/* ret 0x0b000000 */
	return b;
}

/*******************************************************************
 * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
 *******************************************************************/
u32 get_gpmc0_width(void)
{
	return WIDTH_16BIT;
}

/*************************************************************************
 * get_board_rev() - setup to pass kernel board revision information
 * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
 *************************************************************************/
u32 __weak get_board_rev(void)
{
	return 0x20;
}

/********************************************************
 *  get_base(); get upper addr of current execution
 *******************************************************/
u32 get_base(void)
{
	u32 val;

	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
	val &= 0xF0000000;
	val >>= 28;
	return val;
}

/********************************************************
 *  is_running_in_flash() - tell if currently running in
 *  FLASH.
 *******************************************************/
u32 is_running_in_flash(void)
{
	if (get_base() < 4)
		return 1;	/* in FLASH */

	return 0;		/* running in SRAM or SDRAM */
}

/********************************************************
 *  is_running_in_sram() - tell if currently running in
 *  SRAM.
 *******************************************************/
u32 is_running_in_sram(void)
{
	if (get_base() == 4)
		return 1;	/* in SRAM */

	return 0;		/* running in FLASH or SDRAM */
}

/********************************************************
 *  is_running_in_sdram() - tell if currently running in
 *  SDRAM.
 *******************************************************/
u32 is_running_in_sdram(void)
{
	if (get_base() > 4)
		return 1;	/* in SDRAM */

	return 0;		/* running in SRAM or FLASH */
}

/***************************************************************
 *  get_boot_type() - Is this an XIP type device or a stream one
 *  bits 4-0 specify type. Bit 5 says mem/perif
 ***************************************************************/
u32 get_boot_type(void)
{
	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
}

/*************************************************************
 *  get_device_type(): tell if GP/HS/EMU/TST
 *************************************************************/
u32 get_device_type(void)
{
	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
}

#ifdef CONFIG_DISPLAY_CPUINFO
/**
 * Print CPU information
 */
int print_cpuinfo (void)
{
	char *cpu_family_s, *cpu_s, *sec_s, *max_clk;

	switch (get_cpu_family()) {
	case CPU_OMAP34XX:
		cpu_family_s = "OMAP";
		switch (get_cpu_type()) {
		case OMAP3503:
			cpu_s = "3503";
			break;
		case OMAP3515:
			cpu_s = "3515";
			break;
		case OMAP3525:
			cpu_s = "3525";
			break;
		case OMAP3530:
			cpu_s = "3530";
			break;
		default:
			cpu_s = "35XX";
			break;
		}
		if ((get_cpu_rev() >= CPU_3XX_ES31) &&
		    (get_sku_id() == SKUID_CLK_720MHZ))
			max_clk = "720 MHz";
		else
			max_clk = "600 MHz";

		break;
	case CPU_AM35XX:
		cpu_family_s = "AM";
		switch (get_cpu_type()) {
		case AM3505:
			cpu_s = "3505";
			break;
		case AM3517:
			cpu_s = "3517";
			break;
		default:
			cpu_s = "35XX";
			break;
		}
		max_clk = "600 Mhz";
		break;
	case CPU_OMAP36XX:
		cpu_family_s = "OMAP";
		switch (get_cpu_type()) {
		case OMAP3730:
			cpu_s = "3630/3730";
			break;
		default:
			cpu_s = "36XX/37XX";
			break;
		}
		max_clk = "1 Ghz";
		break;
	default:
		cpu_family_s = "OMAP";
		cpu_s = "35XX";
		max_clk = "600 Mhz";
	}

	switch (get_device_type()) {
	case TST_DEVICE:
		sec_s = "TST";
		break;
	case EMU_DEVICE:
		sec_s = "EMU";
		break;
	case HS_DEVICE:
		sec_s = "HS";
		break;
	case GP_DEVICE:
		sec_s = "GP";
		break;
	default:
		sec_s = "?";
	}

	if (CPU_OMAP36XX == get_cpu_family())
		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
			cpu_family_s, cpu_s, sec_s,
			rev_s_37xx[get_cpu_rev()], max_clk);
	else
		printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
			cpu_family_s, cpu_s, sec_s,
			rev_s[get_cpu_rev()], max_clk);

	return 0;
}
#endif	/* CONFIG_DISPLAY_CPUINFO */
Commit	Line	Data
91eee546 DB	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	*
	5	* Author :
	6	* Manikandan Pillai <mani.pillai@ti.com>
	7	*
	8	* Derived from Beagle Board and 3430 SDP code by
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	* Syed Mohammed Khasim <khasim@ti.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
91eee546 DB	13	*/
	14
	15	#include <common.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/mem.h> /* get mem tables */
	18	#include <asm/arch/sys_proto.h>
	19	#include <i2c.h>
715462dd	20	#include <linux/compiler.h>
91eee546 DB	21
91eee546 DB	22	extern omap3_sysinfo sysinfo;
97a099ea	23	static struct ctrl ctrl_base = (struct ctrl )OMAP34XX_CTRL_BASE;
80bb756d SP	24
80bb756d SP	25	#ifdef CONFIG_DISPLAY_CPUINFO
cba0b778 SP	26	static char *rev_s[CPU_3XX_MAX_REV] = {
	27	"1.0",
	28	"2.0",
	29	"2.1",
	30	"3.0",
b2b9169f SS	31	"3.1",
	32	"UNKNOWN",
	33	"UNKNOWN",
	34	"3.1.2"};
91eee546	35
32b58ce7 HG	36	/* this is the revision table for 37xx CPUs */
	37	static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
	38	"1.0",
	39	"1.1",
	40	"1.2"};
939e7222	41	#endif /* CONFIG_DISPLAY_CPUINFO */
32b58ce7	42
e6a6a704 DB	43	/*****************************************************************
	44	* dieid_num_r(void) - read and set die ID
	45	*****************************************************************/
	46	void dieid_num_r(void)
	47	{
97a099ea	48	struct ctrl_id id_base = (struct ctrl_id )OMAP34XX_ID_L4_IO_BASE;
e6a6a704 DB	49	char *uid_s, die_id[34];
	50	u32 id[4];
	51
	52	memset(die_id, 0, sizeof(die_id));
	53
	54	uid_s = getenv("dieid#");
	55
	56	if (uid_s == NULL) {
	57	id[3] = readl(&id_base->die_id_0);
	58	id[2] = readl(&id_base->die_id_1);
	59	id[1] = readl(&id_base->die_id_2);
	60	id[0] = readl(&id_base->die_id_3);
	61	sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
	62	setenv("dieid#", die_id);
	63	uid_s = die_id;
	64	}
	65
	66	printf("Die ID #%s\n", uid_s);
	67	}
	68
6530a8bf DB	69	/******************************************
	70	* get_cpu_type(void) - extract cpu info
	71	******************************************/
	72	u32 get_cpu_type(void)
	73	{
	74	return readl(&ctrl_base->ctrl_omap_stat);
	75	}
	76
91eee546	77	/******************************************
b2b9169f SS	78	* get_cpu_id(void) - extract cpu id
b2b9169f SS	79	* returns 0 for ES1.0, cpuid otherwise
91eee546	80	******************************************/
b2b9169f	81	u32 get_cpu_id(void)
91eee546	82	{
97a099ea	83	struct ctrl_id *id_base;
b2b9169f	84	u32 cpuid = 0;
91eee546 DB	85
	86	/*
	87	* On ES1.0 the IDCODE register is not exposed on L4
cba0b778	88	* so using CPU ID to differentiate between ES1.0 and > ES1.0.
91eee546 DB	89	*/
91eee546 DB	90	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
b2b9169f SS	91	if ((cpuid & 0xf) == 0x0) {
	92	return 0;
	93	} else {
cba0b778	94	/* Decode the IDs on > ES1.0 */
97a099ea	95	id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
91eee546	96
b2b9169f SS	97	cpuid = readl(&id_base->idcode);
b2b9169f SS	98	}
cba0b778	99
b2b9169f SS	100	return cpuid;
b2b9169f SS	101	}
cba0b778	102
b2b9169f SS	103	/******************************************
	104	* get_cpu_family(void) - extract cpu info
	105	******************************************/
	106	u32 get_cpu_family(void)
	107	{
	108	u16 hawkeye;
	109	u32 cpu_family;
	110	u32 cpuid = get_cpu_id();
	111
	112	if (cpuid == 0)
	113	return CPU_OMAP34XX;
	114
	115	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
	116	switch (hawkeye) {
	117	case HAWKEYE_OMAP34XX:
	118	cpu_family = CPU_OMAP34XX;
	119	break;
	120	case HAWKEYE_AM35XX:
	121	cpu_family = CPU_AM35XX;
	122	break;
	123	case HAWKEYE_OMAP36XX:
	124	cpu_family = CPU_OMAP36XX;
	125	break;
	126	default:
	127	cpu_family = CPU_OMAP34XX;
cba0b778	128	}
b2b9169f SS	129
	130	return cpu_family;
	131	}
	132
	133	/******************************************
	134	* get_cpu_rev(void) - extract version info
	135	******************************************/
	136	u32 get_cpu_rev(void)
	137	{
	138	u32 cpuid = get_cpu_id();
	139
	140	if (cpuid == 0)
	141	return CPU_3XX_ES10;
	142	else
	143	return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
	144	}
	145
	146	/*****************************************************************
	147	* get_sku_id(void) - read sku_id to get info on max clock rate
	148	*****************************************************************/
	149	u32 get_sku_id(void)
	150	{
	151	struct ctrl_id id_base = (struct ctrl_id )OMAP34XX_ID_L4_IO_BASE;
	152	return readl(&id_base->sku_id) & SKUID_CLK_MASK;
91eee546 DB	153	}
91eee546 DB	154
91eee546 DB	155	/***************************************************************************
	156	* get_gpmc0_base() - Return current address hardware will be
	157	* fetching from. The below effectively gives what is correct, its a bit
	158	* mis-leading compared to the TRM. For the most general case the mask
	159	* needs to be also taken into account this does work in practice.
	160	* - for u-boot we currently map:
	161	* -- 0 to nothing,
	162	* -- 4 to flash
	163	* -- 8 to enent
	164	* -- c to wifi
	165	****************************************************************************/
	166	u32 get_gpmc0_base(void)
	167	{
	168	u32 b;
	169
89411352	170	b = readl(&gpmc_cfg->cs[0].config7);
91eee546 DB	171	b &= 0x1F; /* keep base [5:0] */
	172	b = b << 24; /* ret 0x0b000000 */
	173	return b;
	174	}
	175
	176	/*******************************************************************
	177	* get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
	178	*******************************************************************/
	179	u32 get_gpmc0_width(void)
	180	{
	181	return WIDTH_16BIT;
	182	}
	183
	184	/*************************************************************************
	185	* get_board_rev() - setup to pass kernel board revision information
	186	* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
	187	*************************************************************************/
715462dd	188	u32 __weak get_board_rev(void)
91eee546 DB	189	{
	190	return 0x20;
	191	}
	192
91eee546 DB	193	/********************************************************
	194	* get_base(); get upper addr of current execution
	195	*******************************************************/
	196	u32 get_base(void)
	197	{
	198	u32 val;
	199
	200	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
	201	val &= 0xF0000000;
	202	val >>= 28;
	203	return val;
	204	}
	205
	206	/********************************************************
	207	* is_running_in_flash() - tell if currently running in
	208	* FLASH.
	209	*******************************************************/
	210	u32 is_running_in_flash(void)
	211	{
	212	if (get_base() < 4)
	213	return 1; /* in FLASH */
	214
	215	return 0; /* running in SRAM or SDRAM */
	216	}
	217
	218	/********************************************************
	219	* is_running_in_sram() - tell if currently running in
	220	* SRAM.
	221	*******************************************************/
	222	u32 is_running_in_sram(void)
	223	{
	224	if (get_base() == 4)
	225	return 1; /* in SRAM */
	226
	227	return 0; /* running in FLASH or SDRAM */
	228	}
	229
	230	/********************************************************
	231	* is_running_in_sdram() - tell if currently running in
	232	* SDRAM.
	233	*******************************************************/
	234	u32 is_running_in_sdram(void)
	235	{
	236	if (get_base() > 4)
	237	return 1; /* in SDRAM */
	238
	239	return 0; /* running in SRAM or FLASH */
	240	}
	241
	242	/***************************************************************
	243	* get_boot_type() - Is this an XIP type device or a stream one
	244	* bits 4-0 specify type. Bit 5 says mem/perif
	245	***************************************************************/
	246	u32 get_boot_type(void)
	247	{
	248	return (readl(&ctrl_base->status) & SYSBOOT_MASK);
	249	}
	250
	251	/*************************************************************
	252	* get_device_type(): tell if GP/HS/EMU/TST
	253	*************************************************************/
	254	u32 get_device_type(void)
	255	{
	256	return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
257	}
6a6b62e3 SP	258
	259	#ifdef CONFIG_DISPLAY_CPUINFO
	260	/**
	261	* Print CPU information
	262	*/
	263	int print_cpuinfo (void)
	264	{
b2b9169f SS	265	char cpu_family_s, cpu_s, sec_s, max_clk;
	266
	267	switch (get_cpu_family()) {
	268	case CPU_OMAP34XX:
	269	cpu_family_s = "OMAP";
	270	switch (get_cpu_type()) {
	271	case OMAP3503:
	272	cpu_s = "3503";
	273	break;
	274	case OMAP3515:
	275	cpu_s = "3515";
	276	break;
	277	case OMAP3525:
	278	cpu_s = "3525";
	279	break;
	280	case OMAP3530:
	281	cpu_s = "3530";
	282	break;
	283	default:
	284	cpu_s = "35XX";
	285	break;
	286	}
	287	if ((get_cpu_rev() >= CPU_3XX_ES31) &&
	288	(get_sku_id() == SKUID_CLK_720MHZ))
9d0fd10c	289	max_clk = "720 MHz";
b2b9169f	290	else
9d0fd10c	291	max_clk = "600 MHz";
6a6b62e3	292
6a6b62e3	293	break;
b2b9169f SS	294	case CPU_AM35XX:
	295	cpu_family_s = "AM";
	296	switch (get_cpu_type()) {
	297	case AM3505:
	298	cpu_s = "3505";
	299	break;
	300	case AM3517:
	301	cpu_s = "3517";
	302	break;
	303	default:
	304	cpu_s = "35XX";
	305	break;
	306	}
	307	max_clk = "600 Mhz";
6a6b62e3	308	break;
b2b9169f SS	309	case CPU_OMAP36XX:
	310	cpu_family_s = "OMAP";
	311	switch (get_cpu_type()) {
	312	case OMAP3730:
	313	cpu_s = "3630/3730";
	314	break;
	315	default:
	316	cpu_s = "36XX/37XX";
	317	break;
	318	}
	319	max_clk = "1 Ghz";
6a6b62e3 SP	320	break;
6a6b62e3 SP	321	default:
b2b9169f	322	cpu_family_s = "OMAP";
6a6b62e3	323	cpu_s = "35XX";
b2b9169f	324	max_clk = "600 Mhz";
6a6b62e3 SP	325	}
	326
	327	switch (get_device_type()) {
	328	case TST_DEVICE:
	329	sec_s = "TST";
	330	break;
	331	case EMU_DEVICE:
	332	sec_s = "EMU";
	333	break;
	334	case HS_DEVICE:
	335	sec_s = "HS";
	336	break;
	337	case GP_DEVICE:
	338	sec_s = "GP";
	339	break;
	340	default:
	341	sec_s = "?";
	342	}
	343
32b58ce7 HG	344	if (CPU_OMAP36XX == get_cpu_family())
	345	printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
	346	cpu_family_s, cpu_s, sec_s,
	347	rev_s_37xx[get_cpu_rev()], max_clk);
	348	else
	349	printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
b2b9169f SS	350	cpu_family_s, cpu_s, sec_s,
b2b9169f SS	351	rev_s[get_cpu_rev()], max_clk);
6a6b62e3 SP	352
	353	return 0;
	354	}
	355	#endif /* CONFIG_DISPLAY_CPUINFO */