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ARM: DRA7xx: clocks: Update PLL values
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / hw_data.c
CommitLineData
01b753ff
S		 1/*
2 *
3 * HW data initialization for OMAP5
4 *
5 * (C) Copyright 2013
6 * Texas Instruments, <www.ti.com>
7 *
8 * Sricharan R <r.sricharan@ti.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28#include <common.h>
63fc0c77 29#include <palmas.h>
01b753ff 30#include <asm/arch/omap.h>
ee9447bf 31#include <asm/arch/sys_proto.h>
01b753ff 32#include <asm/omap_common.h>
af1d002f 33#include <asm/arch/clock.h>
3fcdd4a5 34#include <asm/omap_gpio.h>
ee9447bf 35#include <asm/io.h>
ef1697e9 36#include <asm/emif.h>
01b753ff
S		 37
38struct prcm_regs const **prcm =
39 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
ee9447bf
S		 40struct dplls const **dplls_data =
41 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
3fcdd4a5
S		 42struct vcores_data const **omap_vcores =
43 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
c43c8339 44struct omap_sys_ctrl_regs const **ctrl =
f92f2277 45 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
ee9447bf 46
47abc3df 47/* OPP HIGH FREQUENCY for ES2.0 */
ee9447bf 48static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
47abc3df
S		 49 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
50 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
51 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
52 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
53 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
54 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
55 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 56};
57
47abc3df 58/* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
ee9447bf 59static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
47abc3df
S		 60 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
61 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
62 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
63 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
64 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
65 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
66 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 67};
68
47abc3df 69/* OPP NOM FREQUENCY for ES1.0 */
ee9447bf 70static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
47abc3df
S		 71 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
72 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
73 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
74 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
75 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
76 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
77 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 78};
79
47abc3df 80/* OPP LOW FREQUENCY for ES1.0 */
ee9447bf 81static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
47abc3df
S		 82 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
83 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
84 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
85 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
86 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
87 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
88 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 89};
90
47abc3df
S		 91/* OPP LOW FREQUENCY for ES2.0 */
92static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
93 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
94 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
95 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
96 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
97 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
98 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
99 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 100};
101
ea8eff1f 102static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
97405d84
LV		 103 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
104 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
105 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
106 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
107 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
ea8eff1f 108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
97405d84 109 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
ea8eff1f
LV		 110};
111
ee9447bf
S		 112static const struct dpll_params
113 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
47abc3df
S		 114 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
116 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
117 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
118 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
119 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
120 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
121};
122
123static const struct dpll_params
124 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
125 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
127 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
128 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
129 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
130 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
131 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
ee9447bf
S		 132};
133
ea8eff1f 134static const struct dpll_params
97405d84
LV		 135 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
136 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
137 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
138 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
139 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
140 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
ea8eff1f 141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
97405d84 142 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
ea8eff1f
LV		 143};
144
ee9447bf
S		 145static const struct dpll_params
146 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
47abc3df
S		 147 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
148 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
149 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
150 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
151 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
152 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
153 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
154};
155
156static const struct dpll_params
157 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
158 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
159 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
160 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
161 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
162 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
163 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
164 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
ee9447bf
S		 165};
166
167static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
47abc3df
S		 168 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
169 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
170 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
171 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
172 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
174 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
175};
176
177static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
178 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
179 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
180 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
181 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
182 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
183 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
184 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 185};
186
ea8eff1f 187static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
97405d84
LV		 188 {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
189 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
190 {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
191 {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
192 {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
ea8eff1f 193 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
97405d84 194 {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
ea8eff1f
LV		 195};
196
ee9447bf 197static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
47abc3df
S		 198 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
200 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
201 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
202 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
203 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
204 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 205};
206
97405d84
LV		 207static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
208 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
209 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
210 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
211 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
212 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
214 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
215};
216
ee9447bf
S		 217/* ABE M & N values with sys_clk as source */
218static const struct dpll_params
219 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
47abc3df
S		 220 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
221 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
222 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
223 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
224 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
225 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
226 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
ee9447bf
S		 227};
228
229/* ABE M & N values with 32K clock as source */
230static const struct dpll_params abe_dpll_params_32k_196608khz = {
47abc3df 231 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
ee9447bf
S		 232};
233
97405d84
LV		 234/* ABE M & N values with sysclk2(22.5792 MHz) as input */
235static const struct dpll_params
236 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
237 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
238 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
239 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
240 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
241 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
242 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
243 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
244};
245
ee9447bf 246static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
47abc3df 247 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
97405d84 248 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
47abc3df
S		 249 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
250 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
251 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
252 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
ea8eff1f 253 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
ea8eff1f
LV		 254};
255
97405d84
LV		 256static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
257 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
258 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
259 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
260 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
261 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
ea8eff1f 262 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
97405d84 263 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
ee9447bf
S		 264};
265
266struct dplls omap5_dplls_es1 = {
267 .mpu = mpu_dpll_params_800mhz,
268 .core = core_dpll_params_2128mhz_ddr532,
269 .per = per_dpll_params_768mhz,
270 .iva = iva_dpll_params_2330mhz,
271#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
272 .abe = abe_dpll_params_sysclk_196608khz,
273#else
274 .abe = &abe_dpll_params_32k_196608khz,
275#endif
ea8eff1f
LV		 276 .usb = usb_dpll_params_1920mhz,
277 .ddr = NULL
ee9447bf
S		 278};
279
47abc3df
S		 280struct dplls omap5_dplls_es2 = {
281 .mpu = mpu_dpll_params_1100mhz,
282 .core = core_dpll_params_2128mhz_ddr532_es2,
283 .per = per_dpll_params_768mhz_es2,
284 .iva = iva_dpll_params_2330mhz,
285#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
286 .abe = abe_dpll_params_sysclk_196608khz,
287#else
288 .abe = &abe_dpll_params_32k_196608khz,
289#endif
ea8eff1f
LV		 290 .usb = usb_dpll_params_1920mhz,
291 .ddr = NULL
292};
293
294struct dplls dra7xx_dplls = {
295 .mpu = mpu_dpll_params_1ghz,
97405d84 296 .core = core_dpll_params_2128mhz_dra7xx,
ea8eff1f 297 .per = per_dpll_params_768mhz_dra7xx,
97405d84
LV		 298 .abe = abe_dpll_params_sysclk2_361267khz,
299 .iva = iva_dpll_params_2330mhz_dra7xx,
ea8eff1f 300 .usb = usb_dpll_params_1920mhz,
97405d84 301 .ddr = ddr_dpll_params_2128mhz,
47abc3df
S		 302};
303
3fcdd4a5
S		 304struct pmic_data palmas = {
305 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
306 .step = 10000, /* 10 mV represented in uV */
307 /*
308 * Offset codes 1-6 all give the base voltage in Palmas
309 * Offset code 0 switches OFF the SMPS
310 */
311 .start_code = 6,
4ca94d81
LV		 312 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
313 .pmic_bus_init = sri2c_init,
314 .pmic_write = omap_vc_bypass_send_value,
3fcdd4a5
S		 315};
316
63fc0c77
LV		 317struct pmic_data tps659038 = {
318 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
319 .step = 10000, /* 10 mV represented in uV */
320 /*
321 * Offset codes 1-6 all give the base voltage in Palmas
322 * Offset code 0 switches OFF the SMPS
323 */
324 .start_code = 6,
325 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
326 .pmic_bus_init = gpi2c_init,
327 .pmic_write = palmas_i2c_write_u8,
328};
329
3fcdd4a5
S		 330struct vcores_data omap5430_volts = {
331 .mpu.value = VDD_MPU,
332 .mpu.addr = SMPS_REG_ADDR_12_MPU,
333 .mpu.pmic = &palmas,
334
335 .core.value = VDD_CORE,
336 .core.addr = SMPS_REG_ADDR_8_CORE,
337 .core.pmic = &palmas,
338
339 .mm.value = VDD_MM,
340 .mm.addr = SMPS_REG_ADDR_45_IVA,
341 .mm.pmic = &palmas,
342};
343
47abc3df
S		 344struct vcores_data omap5430_volts_es2 = {
345 .mpu.value = VDD_MPU_ES2,
3fcdd4a5
S		 346 .mpu.addr = SMPS_REG_ADDR_12_MPU,
347 .mpu.pmic = &palmas,
348
47abc3df 349 .core.value = VDD_CORE_ES2,
3fcdd4a5
S		 350 .core.addr = SMPS_REG_ADDR_8_CORE,
351 .core.pmic = &palmas,
352
47abc3df 353 .mm.value = VDD_MM_ES2,
3fcdd4a5
S		 354 .mm.addr = SMPS_REG_ADDR_45_IVA,
355 .mm.pmic = &palmas,
356};
357
63fc0c77
LV		 358struct vcores_data dra752_volts = {
359 .mpu.value = VDD_MPU_DRA752,
18c9d55a
NM		 360 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
361 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
63fc0c77
LV		 362 .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
363 .mpu.pmic = &tps659038,
364
365 .eve.value = VDD_EVE_DRA752,
18c9d55a
NM		 366 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
367 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
63fc0c77
LV		 368 .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
369 .eve.pmic = &tps659038,
370
371 .gpu.value = VDD_GPU_DRA752,
18c9d55a
NM		 372 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
373 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
63fc0c77
LV		 374 .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
375 .gpu.pmic = &tps659038,
376
377 .core.value = VDD_CORE_DRA752,
18c9d55a
NM		 378 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
379 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
63fc0c77
LV		 380 .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
381 .core.pmic = &tps659038,
382
383 .iva.value = VDD_IVA_DRA752,
18c9d55a
NM		 384 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
385 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
63fc0c77
LV		 386 .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
387 .iva.pmic = &tps659038,
388};
389
ee9447bf
S		 390/*
391 * Enable essential clock domains, modules and
392 * do some additional special settings needed
393 */
394void enable_basic_clocks(void)
395{
396 u32 const clk_domains_essential[] = {
397 (*prcm)->cm_l4per_clkstctrl,
398 (*prcm)->cm_l3init_clkstctrl,
399 (*prcm)->cm_memif_clkstctrl,
400 (*prcm)->cm_l4cfg_clkstctrl,
401 0
402 };
403
404 u32 const clk_modules_hw_auto_essential[] = {
d4e4129c 405 (*prcm)->cm_l3_gpmc_clkctrl,
ee9447bf
S		 406 (*prcm)->cm_memif_emif_1_clkctrl,
407 (*prcm)->cm_memif_emif_2_clkctrl,
408 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
409 (*prcm)->cm_wkup_gpio1_clkctrl,
410 (*prcm)->cm_l4per_gpio2_clkctrl,
411 (*prcm)->cm_l4per_gpio3_clkctrl,
412 (*prcm)->cm_l4per_gpio4_clkctrl,
413 (*prcm)->cm_l4per_gpio5_clkctrl,
414 (*prcm)->cm_l4per_gpio6_clkctrl,
415 0
416 };
417
418 u32 const clk_modules_explicit_en_essential[] = {
419 (*prcm)->cm_wkup_gptimer1_clkctrl,
420 (*prcm)->cm_l3init_hsmmc1_clkctrl,
421 (*prcm)->cm_l3init_hsmmc2_clkctrl,
422 (*prcm)->cm_l4per_gptimer2_clkctrl,
423 (*prcm)->cm_wkup_wdtimer2_clkctrl,
424 (*prcm)->cm_l4per_uart3_clkctrl,
425 (*prcm)->cm_l4per_i2c1_clkctrl,
426 0
427 };
428
429 /* Enable optional additional functional clock for GPIO4 */
430 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
431 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
432
433 /* Enable 96 MHz clock for MMC1 & MMC2 */
434 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
435 HSMMC_CLKCTRL_CLKSEL_MASK);
436 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
437 HSMMC_CLKCTRL_CLKSEL_MASK);
438
439 /* Set the correct clock dividers for mmc */
440 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
441 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
442 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
443 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
444
445 /* Select 32KHz clock as the source of GPTIMER1 */
446 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
447 GPTIMER1_CLKCTRL_CLKSEL_MASK);
448
449 do_enable_clocks(clk_domains_essential,
450 clk_modules_hw_auto_essential,
451 clk_modules_explicit_en_essential,
452 1);
453
ee9447bf
S		 454 /* Enable SCRM OPT clocks for PER and CORE dpll */
455 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
456 OPTFCLKEN_SCRM_PER_MASK);
457 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
458 OPTFCLKEN_SCRM_CORE_MASK);
459}
460
461void enable_basic_uboot_clocks(void)
462{
463 u32 const clk_domains_essential[] = {
464 0
465 };
466
467 u32 const clk_modules_hw_auto_essential[] = {
2bcc785a 468 (*prcm)->cm_l3init_hsusbtll_clkctrl,
ee9447bf
S		 469 0
470 };
471
472 u32 const clk_modules_explicit_en_essential[] = {
473 (*prcm)->cm_l4per_mcspi1_clkctrl,
474 (*prcm)->cm_l4per_i2c2_clkctrl,
475 (*prcm)->cm_l4per_i2c3_clkctrl,
476 (*prcm)->cm_l4per_i2c4_clkctrl,
3935277d 477 (*prcm)->cm_l4per_i2c5_clkctrl,
ee9447bf
S		 478 (*prcm)->cm_l3init_hsusbhost_clkctrl,
479 (*prcm)->cm_l3init_fsusb_clkctrl,
480 0
481 };
482
483 do_enable_clocks(clk_domains_essential,
484 clk_modules_hw_auto_essential,
485 clk_modules_explicit_en_essential,
486 1);
487}
488
489/*
490 * Enable non-essential clock domains, modules and
491 * do some additional special settings needed
492 */
493void enable_non_essential_clocks(void)
494{
495 u32 const clk_domains_non_essential[] = {
496 (*prcm)->cm_mpu_m3_clkstctrl,
497 (*prcm)->cm_ivahd_clkstctrl,
498 (*prcm)->cm_dsp_clkstctrl,
499 (*prcm)->cm_dss_clkstctrl,
500 (*prcm)->cm_sgx_clkstctrl,
501 (*prcm)->cm1_abe_clkstctrl,
502 (*prcm)->cm_c2c_clkstctrl,
503 (*prcm)->cm_cam_clkstctrl,
504 (*prcm)->cm_dss_clkstctrl,
505 (*prcm)->cm_sdma_clkstctrl,
506 0
507 };
508
509 u32 const clk_modules_hw_auto_non_essential[] = {
510 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
511 (*prcm)->cm_ivahd_ivahd_clkctrl,
512 (*prcm)->cm_ivahd_sl2_clkctrl,
513 (*prcm)->cm_dsp_dsp_clkctrl,
514 (*prcm)->cm_l3instr_l3_3_clkctrl,
515 (*prcm)->cm_l3instr_l3_instr_clkctrl,
516 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
517 (*prcm)->cm_l3init_hsi_clkctrl,
518 (*prcm)->cm_l4per_hdq1w_clkctrl,
519 0
520 };
521
522 u32 const clk_modules_explicit_en_non_essential[] = {
523 (*prcm)->cm1_abe_aess_clkctrl,
524 (*prcm)->cm1_abe_pdm_clkctrl,
525 (*prcm)->cm1_abe_dmic_clkctrl,
526 (*prcm)->cm1_abe_mcasp_clkctrl,
527 (*prcm)->cm1_abe_mcbsp1_clkctrl,
528 (*prcm)->cm1_abe_mcbsp2_clkctrl,
529 (*prcm)->cm1_abe_mcbsp3_clkctrl,
530 (*prcm)->cm1_abe_slimbus_clkctrl,
531 (*prcm)->cm1_abe_timer5_clkctrl,
532 (*prcm)->cm1_abe_timer6_clkctrl,
533 (*prcm)->cm1_abe_timer7_clkctrl,
534 (*prcm)->cm1_abe_timer8_clkctrl,
535 (*prcm)->cm1_abe_wdt3_clkctrl,
536 (*prcm)->cm_l4per_gptimer9_clkctrl,
537 (*prcm)->cm_l4per_gptimer10_clkctrl,
538 (*prcm)->cm_l4per_gptimer11_clkctrl,
539 (*prcm)->cm_l4per_gptimer3_clkctrl,
540 (*prcm)->cm_l4per_gptimer4_clkctrl,
541 (*prcm)->cm_l4per_mcspi2_clkctrl,
542 (*prcm)->cm_l4per_mcspi3_clkctrl,
543 (*prcm)->cm_l4per_mcspi4_clkctrl,
544 (*prcm)->cm_l4per_mmcsd3_clkctrl,
545 (*prcm)->cm_l4per_mmcsd4_clkctrl,
546 (*prcm)->cm_l4per_mmcsd5_clkctrl,
547 (*prcm)->cm_l4per_uart1_clkctrl,
548 (*prcm)->cm_l4per_uart2_clkctrl,
549 (*prcm)->cm_l4per_uart4_clkctrl,
550 (*prcm)->cm_wkup_keyboard_clkctrl,
551 (*prcm)->cm_wkup_wdtimer2_clkctrl,
552 (*prcm)->cm_cam_iss_clkctrl,
553 (*prcm)->cm_cam_fdif_clkctrl,
554 (*prcm)->cm_dss_dss_clkctrl,
555 (*prcm)->cm_sgx_sgx_clkctrl,
556 0
557 };
558
559 /* Enable optional functional clock for ISS */
560 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
561
562 /* Enable all optional functional clocks of DSS */
563 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
564
565 do_enable_clocks(clk_domains_non_essential,
566 clk_modules_hw_auto_non_essential,
567 clk_modules_explicit_en_non_essential,
568 0);
569
570 /* Put camera module in no sleep mode */
571 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
572 MODULE_CLKCTRL_MODULEMODE_MASK,
573 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
574 MODULE_CLKCTRL_MODULEMODE_SHIFT);
575}
01b753ff 576
ef1697e9
LV		 577const struct ctrl_ioregs ioregs_omap5430 = {
578 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
579 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
580 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
581 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
582 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
583};
584
585const struct ctrl_ioregs ioregs_omap5432_es1 = {
586 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
587 .ctrl_lpddr2ch = 0x0,
588 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
589 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
590 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
591 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
592 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
593};
594
9100edec
LV		 595const struct ctrl_ioregs ioregs_omap5432_es2 = {
596 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
597 .ctrl_lpddr2ch = 0x0,
598 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
599 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
600 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
601 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
602 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
603};
604
01b753ff
S		 605void hw_data_init(void)
606{
ee9447bf
S		 607 u32 omap_rev = omap_revision();
608
609 switch (omap_rev) {
610
611 case OMAP5430_ES1_0:
ee9447bf
S		 612 case OMAP5432_ES1_0:
613 *prcm = &omap5_es1_prcm;
614 *dplls_data = &omap5_dplls_es1;
47abc3df 615 *omap_vcores = &omap5430_volts;
8b12f177 616 *ctrl = &omap5_ctrl;
ee9447bf
S		 617 break;
618
afc2f9dc
S		 619 case OMAP5430_ES2_0:
620 case OMAP5432_ES2_0:
621 *prcm = &omap5_es2_prcm;
47abc3df
S		 622 *dplls_data = &omap5_dplls_es2;
623 *omap_vcores = &omap5430_volts_es2;
8b12f177 624 *ctrl = &omap5_ctrl;
afc2f9dc
S		 625 break;
626
d4e4129c
LV		 627 case DRA752_ES1_0:
628 *prcm = &dra7xx_prcm;
ea8eff1f 629 *dplls_data = &dra7xx_dplls;
63fc0c77 630 *omap_vcores = &dra752_volts;
8b12f177 631 *ctrl = &dra7xx_ctrl;
d4e4129c
LV		 632 break;
633
ee9447bf
S		 634 default:
635 printf("\n INVALID OMAP REVISION ");
636 }
01b753ff 637}
ef1697e9
LV		 638
639void get_ioregs(const struct ctrl_ioregs **regs)
640{
641 u32 omap_rev = omap_revision();
642
643 switch (omap_rev) {
644 case OMAP5430_ES1_0:
9100edec 645 case OMAP5430_ES2_0:
ef1697e9
LV		 646 *regs = &ioregs_omap5430;
647 break;
648 case OMAP5432_ES1_0:
649 *regs = &ioregs_omap5432_es1;
650 break;
9100edec 651 case OMAP5432_ES2_0:
7831419d 652 case DRA752_ES1_0:
9100edec
LV		 653 *regs = &ioregs_omap5432_es2;
654 break;
ef1697e9
LV		 655
656 default:
657 printf("\n INVALID OMAP REVISION ");
658 }
659}
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