[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / sdram.c

/*
 * Timing and Organization details of the ddr device parts used in OMAP5
 * EVM
 *
 * (C) Copyright 2010
 * Texas Instruments, <www.ti.com>
 *
 * Aneesh V <aneesh@ti.com>
 * Sricharan R <r.sricharan@ti.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/emif.h>
#include <asm/arch/sys_proto.h>

/*
 * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
 * EVM. Since the parts used and geometry are identical for
 * evm for a given OMAP5 revision, this information is kept
 * here instead of being in board directory. However the key functions
 * exported are weakly linked so that they can be over-ridden in the board
 * directory if there is a OMAP5 board in the future that uses a different
 * memory device or geometry.
 *
 * For any new board with different memory devices over-ride one or more
 * of the following functions as per the CONFIG flags you intend to enable:
 * - emif_get_reg_dump()
 * - emif_get_dmm_regs()
 * - emif_get_device_details()
 * - emif_get_device_timings()
 */

#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
const struct emif_regs emif_regs_532_mhz_2cs = {
	.sdram_config_init		= 0x80800EBA,
	.sdram_config			= 0x808022BA,
	.ref_ctrl			= 0x0000081A,
	.sdram_tim1			= 0x772F6873,
	.sdram_tim2			= 0x304a129a,
	.sdram_tim3			= 0x02f7e45f,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x000b3215,
	.temp_alert_config		= 0x08000a05,
	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
};

const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
	.sdram_config_init		= 0x80800EBA,
	.sdram_config			= 0x808022BA,
	.ref_ctrl			= 0x0000081A,
	.sdram_tim1			= 0x772F6873,
	.sdram_tim2			= 0x304a129a,
	.sdram_tim3			= 0x02f7e45f,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x100b3215,
	.temp_alert_config		= 0x08000a05,
	.emif_ddr_phy_ctlr_1_init	= 0x0E30400d,
	.emif_ddr_phy_ctlr_1		= 0x0E30400d,
	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
	.emif_ddr_ext_phy_ctrl_2	= 0x28C518A3,
	.emif_ddr_ext_phy_ctrl_3	= 0x518A3146,
	.emif_ddr_ext_phy_ctrl_4	= 0x0014628C,
	.emif_ddr_ext_phy_ctrl_5	= 0xC330CC33,
};

const struct emif_regs emif_regs_266_mhz_2cs = {
	.sdram_config_init		= 0x80800EBA,
	.sdram_config			= 0x808022BA,
	.ref_ctrl			= 0x0000040D,
	.sdram_tim1			= 0x2A86B419,
	.sdram_tim2			= 0x1025094A,
	.sdram_tim3			= 0x026BA22F,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x000b3215,
	.temp_alert_config		= 0x08000a05,
	.emif_ddr_phy_ctlr_1_init	= 0x0E28420d,
	.emif_ddr_phy_ctlr_1		= 0x0E28420d,
	.emif_ddr_ext_phy_ctrl_1	= 0x04020080,
	.emif_ddr_ext_phy_ctrl_2	= 0x0A414829,
	.emif_ddr_ext_phy_ctrl_3	= 0x14829052,
	.emif_ddr_ext_phy_ctrl_4	= 0x000520A4,
	.emif_ddr_ext_phy_ctrl_5	= 0x04010040
};

const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
	.sdram_config_init		= 0x61851B32,
	.sdram_config			= 0x61851B32,
	.sdram_config2			= 0x0,
	.ref_ctrl			= 0x00001035,
	.sdram_tim1			= 0xCCCF36B3,
	.sdram_tim2			= 0x308F7FDA,
	.sdram_tim3			= 0x027F88A8,
	.read_idle_ctrl			= 0x00050000,
	.zq_config			= 0x0007190B,
	.temp_alert_config		= 0x00000000,
	.emif_ddr_phy_ctlr_1_init	= 0x0020420A,
	.emif_ddr_phy_ctlr_1		= 0x0024420A,
	.emif_ddr_ext_phy_ctrl_1	= 0x04040100,
	.emif_ddr_ext_phy_ctrl_2	= 0x00000000,
	.emif_ddr_ext_phy_ctrl_3	= 0x00000000,
	.emif_ddr_ext_phy_ctrl_4	= 0x00000000,
	.emif_ddr_ext_phy_ctrl_5	= 0x04010040,
	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
	.emif_rd_wr_lvl_ctl		= 0x00000000,
	.emif_rd_wr_exec_thresh		= 0x00000305
};

const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
	.sdram_config_init              = 0x61851B32,
	.sdram_config                   = 0x61851B32,
	.sdram_config2			= 0x0,
	.ref_ctrl                       = 0x00001035,
	.sdram_tim1                     = 0xCCCF36B3,
	.sdram_tim2                     = 0x308F7FDA,
	.sdram_tim3                     = 0x027F88A8,
	.read_idle_ctrl                 = 0x00050000,
	.zq_config                      = 0x1007190B,
	.temp_alert_config              = 0x00000000,
	.emif_ddr_phy_ctlr_1_init       = 0x0030400A,
	.emif_ddr_phy_ctlr_1            = 0x0034400A,
	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
	.emif_ddr_ext_phy_ctrl_2        = 0x00000000,
	.emif_ddr_ext_phy_ctrl_3        = 0x00000000,
	.emif_ddr_ext_phy_ctrl_4        = 0x00000000,
	.emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
	.emif_rd_wr_lvl_ctl             = 0x00000000,
	.emif_rd_wr_exec_thresh         = 0x40000305
};

const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
	.sdram_config_init              = 0x61851ab2,
	.sdram_config                   = 0x61851ab2,
	.sdram_config2			= 0x08000000,
	.ref_ctrl                       = 0x00001035,
	.sdram_tim1                     = 0xCCCF36B3,
	.sdram_tim2                     = 0x308F7FDA,
	.sdram_tim3                     = 0x027F88A8,
	.read_idle_ctrl                 = 0x00050001,
	.zq_config                      = 0x0007190B,
	.temp_alert_config              = 0x00000000,
	.emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
	.emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
	.emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
	.emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
	.emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
	.emif_rd_wr_lvl_ctl             = 0x00000000,
	.emif_rd_wr_exec_thresh         = 0x00000305
};

const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
	.sdram_config_init              = 0x61851B32,
	.sdram_config                   = 0x61851B32,
	.sdram_config2			= 0x08000000,
	.ref_ctrl                       = 0x00001035,
	.sdram_tim1                     = 0xCCCF36B3,
	.sdram_tim2                     = 0x308F7FDA,
	.sdram_tim3                     = 0x027F88A8,
	.read_idle_ctrl                 = 0x00050001,
	.zq_config                      = 0x0007190B,
	.temp_alert_config              = 0x00000000,
	.emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
	.emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
	.emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
	.emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
	.emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
	.emif_rd_wr_lvl_ctl             = 0x00000000,
	.emif_rd_wr_exec_thresh         = 0x00000305
};

const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
	.dmm_lisa_map_0 = 0x0,
	.dmm_lisa_map_1 = 0x0,
	.dmm_lisa_map_2 = 0x80740300,
	.dmm_lisa_map_3 = 0xFF020100,
	.is_ma_present	= 0x1
};

/*
 * DRA752 EVM board has 1.5 GB of memory
 * EMIF1 --> 2Gb * 2 =  512MB
 * EMIF2 --> 2Gb * 4 =  1GB
 * so mapping 1GB interleaved and 512MB non-interleaved
 */
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
	.dmm_lisa_map_0 = 0x0,
	.dmm_lisa_map_1 = 0x80640300,
	.dmm_lisa_map_2 = 0xC0500220,
	.dmm_lisa_map_3 = 0xFF020100,
	.is_ma_present	= 0x1
};

/*
 * DRA752 EVM EMIF1 ONLY CONFIGURATION
 */
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
	.dmm_lisa_map_0 = 0x0,
	.dmm_lisa_map_1 = 0x0,
	.dmm_lisa_map_2 = 0x80500100,
	.dmm_lisa_map_3 = 0xFF020100,
	.is_ma_present	= 0x1
};

/*
 * DRA752 EVM EMIF2 ONLY CONFIGURATION
 */
const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
	.dmm_lisa_map_0 = 0x0,
	.dmm_lisa_map_1 = 0x0,
	.dmm_lisa_map_2 = 0x80600200,
	.dmm_lisa_map_3 = 0xFF020100,
	.is_ma_present	= 0x1
};

/*
 * DRA722 EVM EMIF1 CONFIGURATION
 */
const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
	.dmm_lisa_map_0 = 0x0,
	.dmm_lisa_map_1 = 0x0,
	.dmm_lisa_map_2 = 0x80600100,
	.dmm_lisa_map_3 = 0xFF020100,
	.is_ma_present	= 0x1
};

static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
{
	switch (omap_revision()) {
	case OMAP5430_ES1_0:
		*regs = &emif_regs_532_mhz_2cs;
		break;
	case OMAP5432_ES1_0:
		*regs = &emif_regs_ddr3_532_mhz_1cs;
		break;
	case OMAP5430_ES2_0:
		*regs = &emif_regs_532_mhz_2cs_es2;
		break;
	case OMAP5432_ES2_0:
		*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
		break;
	case DRA752_ES1_0:
	case DRA752_ES1_1:
		switch (emif_nr) {
		case 1:
			*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
			break;
		case 2:
			*regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
			break;
		}
		break;
	case DRA722_ES1_0:
	default:
		*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
	}
}

void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
	__attribute__((weak, alias("emif_get_reg_dump_sdp")));

static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
						**dmm_lisa_regs)
{
	switch (omap_revision()) {
	case OMAP5430_ES1_0:
	case OMAP5430_ES2_0:
	case OMAP5432_ES1_0:
	case OMAP5432_ES2_0:
		*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
		break;
	case DRA752_ES1_0:
	case DRA752_ES1_1:
		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
		break;
	case DRA722_ES1_0:
	default:
		*dmm_lisa_regs = &lisa_map_2G_x_2;
	}

}

void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
#else

static const struct lpddr2_device_details dev_4G_S4_details = {
	.type		= LPDDR2_TYPE_S4,
	.density	= LPDDR2_DENSITY_4Gb,
	.io_width	= LPDDR2_IO_WIDTH_32,
	.manufacturer	= LPDDR2_MANUFACTURER_SAMSUNG
};

static void emif_get_device_details_sdp(u32 emif_nr,
		struct lpddr2_device_details *cs0_device_details,
		struct lpddr2_device_details *cs1_device_details)
{
	/* EMIF1 & EMIF2 have identical configuration */
	*cs0_device_details = dev_4G_S4_details;
	*cs1_device_details = dev_4G_S4_details;
}

void emif_get_device_details(u32 emif_nr,
		struct lpddr2_device_details *cs0_device_details,
		struct lpddr2_device_details *cs1_device_details)
	__attribute__((weak, alias("emif_get_device_details_sdp")));

#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */

const u32 ext_phy_ctrl_const_base[] = {
	0x01004010,
	0x00001004,
	0x04010040,
	0x01004010,
	0x00001004,
	0x00000000,
	0x00000000,
	0x00000000,
	0x80080080,
	0x00800800,
	0x08102040,
	0x00000001,
	0x540A8150,
	0xA81502a0,
	0x002A0540,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000077,
	0x0
};

const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
	0x01004010,
	0x00001004,
	0x04010040,
	0x01004010,
	0x00001004,
	0x00000000,
	0x00000000,
	0x00000000,
	0x80080080,
	0x00800800,
	0x08102040,
	0x00000002,
	0x0,
	0x0,
	0x0,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000057,
	0x0
};

const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
	0x50D4350D,
	0x00000D43,
	0x04010040,
	0x01004010,
	0x00001004,
	0x00000000,
	0x00000000,
	0x00000000,
	0x80080080,
	0x00800800,
	0x08102040,
	0x00000002,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000000,
	0x00000057,
	0x0
};

const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
	0x00BB00BB,
	0x00440044,
	0x00440044,
	0x00440044,
	0x00440044,
	0x00440044,
	0x007F007F,
	0x007F007F,
	0x007F007F,
	0x007F007F,
	0x007F007F,
	0x00600060,
	0x00600060,
	0x00600060,
	0x00600060,
	0x00600060,
	0x00000000,
	0x00600020,
	0x40010080,
	0x08102040,
	0x0,
	0x0,
	0x0,
	0x0,
	0x0
};

const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
	0x00BB00BB,
	0x00440044,
	0x00440044,
	0x00440044,
	0x00440044,
	0x00440044,
	0x007F007F,
	0x007F007F,
	0x007F007F,
	0x007F007F,
	0x007F007F,
	0x00600060,
	0x00600060,
	0x00600060,
	0x00600060,
	0x00600060,
	0x00000000,
	0x00600020,
	0x40010080,
	0x08102040,
	0x0,
	0x0,
	0x0,
	0x0,
	0x0
};

const struct lpddr2_mr_regs mr_regs = {
	.mr1	= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
	.mr2	= 0x6,
	.mr3	= 0x1,
	.mr10	= MR10_ZQ_ZQINIT,
	.mr16	= MR16_REF_FULL_ARRAY
};

static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
					     const u32 **regs,
					     u32 *size)
{
	switch (omap_revision()) {
	case OMAP5430_ES1_0:
	case OMAP5430_ES2_0:
		*regs = ext_phy_ctrl_const_base;
		*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
		break;
	case OMAP5432_ES1_0:
		*regs = ddr3_ext_phy_ctrl_const_base_es1;
		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
		break;
	case OMAP5432_ES2_0:
		*regs = ddr3_ext_phy_ctrl_const_base_es2;
		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
		break;
	case DRA752_ES1_0:
	case DRA752_ES1_1:
	case DRA722_ES1_0:
		if (emif_nr == 1) {
			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
			*size =
			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
		} else {
			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
			*size =
			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
		}
		break;
	default:
		*regs = ddr3_ext_phy_ctrl_const_base_es2;
		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);

	}
}

void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
	*regs = &mr_regs;
}

void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
{
	u32 *ext_phy_ctrl_base = 0;
	u32 *emif_ext_phy_ctrl_base = 0;
	u32 emif_nr;
	const u32 *ext_phy_ctrl_const_regs;
	u32 i = 0;
	u32 size;

	emif_nr = (base == EMIF1_BASE) ? 1 : 2;

	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;

	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);

	/* Configure external phy control timing registers */
	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
		writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
		/* Update shadow registers */
		writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
	}

	/*
	 * external phy 6-24 registers do not change with
	 * ddr frequency
	 */
	emif_get_ext_phy_ctrl_const_regs(emif_nr,
					 &ext_phy_ctrl_const_regs, &size);

	for (i = 0; i < size; i++) {
		writel(ext_phy_ctrl_const_regs[i],
		       emif_ext_phy_ctrl_base++);
		/* Update shadow registers */
		writel(ext_phy_ctrl_const_regs[i],
		       emif_ext_phy_ctrl_base++);
	}
}

#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
	.max_freq	= 532000000,
	.RL		= 8,
	.tRPab		= 21,
	.tRCD		= 18,
	.tWR		= 15,
	.tRASmin	= 42,
	.tRRD		= 10,
	.tWTRx2		= 15,
	.tXSR		= 140,
	.tXPx2		= 15,
	.tRFCab		= 130,
	.tRTPx2		= 15,
	.tCKE		= 3,
	.tCKESR		= 15,
	.tZQCS		= 90,
	.tZQCL		= 360,
	.tZQINIT	= 1000,
	.tDQSCKMAXx2	= 11,
	.tRASmax	= 70,
	.tFAW		= 50
};

static const struct lpddr2_min_tck min_tck = {
	.tRL		= 3,
	.tRP_AB		= 3,
	.tRCD		= 3,
	.tWR		= 3,
	.tRAS_MIN	= 3,
	.tRRD		= 2,
	.tWTR		= 2,
	.tXP		= 2,
	.tRTP		= 2,
	.tCKE		= 3,
	.tCKESR		= 3,
	.tFAW		= 8
};

static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
	&timings_jedec_532_mhz
};

static const struct lpddr2_device_timings dev_4G_S4_timings = {
	.ac_timings	= ac_timings,
	.min_tck	= &min_tck,
};

/*
 * List of status registers to be controlled back to control registers
 * after initial leveling
 * readreg, writereg
 */
const struct read_write_regs omap5_bug_00339_regs[] = {
	{ 8,  5 },
	{ 9,  6 },
	{ 10, 7 },
	{ 14, 8 },
	{ 15, 9 },
	{ 16, 10 },
	{ 11, 2 },
	{ 12, 3 },
	{ 13, 4 },
	{ 17, 11 },
	{ 18, 12 },
	{ 19, 13 },
};

const struct read_write_regs dra_bug_00339_regs[] = {
	{ 7,  7 },
	{ 8,  8 },
	{ 9,  9 },
	{ 10, 10 },
	{ 11, 11 },
	{ 12, 2 },
	{ 13, 3 },
	{ 14, 4 },
	{ 15, 5 },
	{ 16, 6 },
	{ 17, 12 },
	{ 18, 13 },
	{ 19, 14 },
	{ 20, 15 },
	{ 21, 16 },
	{ 22, 17 },
	{ 23, 18 },
	{ 24, 19 },
	{ 25, 20 },
	{ 26, 21}
};

const struct read_write_regs *get_bug_regs(u32 *iterations)
{
	const struct read_write_regs *bug_00339_regs_ptr = NULL;

	switch (omap_revision()) {
	case OMAP5430_ES1_0:
	case OMAP5430_ES2_0:
	case OMAP5432_ES1_0:
	case OMAP5432_ES2_0:
		bug_00339_regs_ptr = omap5_bug_00339_regs;
		*iterations = sizeof(omap5_bug_00339_regs)/
			     sizeof(omap5_bug_00339_regs[0]);
		break;
	case DRA752_ES1_0:
	case DRA752_ES1_1:
	case DRA722_ES1_0:
		bug_00339_regs_ptr = dra_bug_00339_regs;
		*iterations = sizeof(dra_bug_00339_regs)/
			     sizeof(dra_bug_00339_regs[0]);
		break;
	default:
		printf("\n Error: UnKnown SOC");
	}

	return bug_00339_regs_ptr;
}

void emif_get_device_timings_sdp(u32 emif_nr,
		const struct lpddr2_device_timings **cs0_device_timings,
		const struct lpddr2_device_timings **cs1_device_timings)
{
	/* Identical devices on EMIF1 & EMIF2 */
	*cs0_device_timings = &dev_4G_S4_timings;
	*cs1_device_timings = &dev_4G_S4_timings;
}

void emif_get_device_timings(u32 emif_nr,
		const struct lpddr2_device_timings **cs0_device_timings,
		const struct lpddr2_device_timings **cs1_device_timings)
	__attribute__((weak, alias("emif_get_device_timings_sdp")));

#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
Commit	Line	Data
bb772a59	1	/*
971f2ba2	2	* Timing and Organization details of the ddr device parts used in OMAP5
bb772a59 S	3	* EVM
	4	*
	5	* (C) Copyright 2010
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Aneesh V <aneesh@ti.com>
	9	* Sricharan R <r.sricharan@ti.com>
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
bb772a59 S	12	*/
	13
	14	#include <asm/emif.h>
	15	#include <asm/arch/sys_proto.h>
	16
	17	/*
	18	* This file provides details of the LPDDR2 SDRAM parts used on OMAP5
	19	* EVM. Since the parts used and geometry are identical for
	20	* evm for a given OMAP5 revision, this information is kept
	21	* here instead of being in board directory. However the key functions
	22	* exported are weakly linked so that they can be over-ridden in the board
	23	* directory if there is a OMAP5 board in the future that uses a different
	24	* memory device or geometry.
	25	*
	26	* For any new board with different memory devices over-ride one or more
	27	* of the following functions as per the CONFIG flags you intend to enable:
	28	* - emif_get_reg_dump()
	29	* - emif_get_dmm_regs()
	30	* - emif_get_device_details()
	31	* - emif_get_device_timings()
	32	*/
	33
	34	#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
971f2ba2	35	const struct emif_regs emif_regs_532_mhz_2cs = {
f4010734 S	36	.sdram_config_init = 0x80800EBA,
f4010734 S	37	.sdram_config = 0x808022BA,
bb772a59 S	38	.ref_ctrl = 0x0000081A,
bb772a59 S	39	.sdram_tim1 = 0x772F6873,
f4010734 S	40	.sdram_tim2 = 0x304a129a,
	41	.sdram_tim3 = 0x02f7e45f,
	42	.read_idle_ctrl = 0x00050000,
	43	.zq_config = 0x000b3215,
	44	.temp_alert_config = 0x08000a05,
	45	.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
	46	.emif_ddr_phy_ctlr_1 = 0x0E28420d,
	47	.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
	48	.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
	49	.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
	50	.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
	51	.emif_ddr_ext_phy_ctrl_5 = 0x04010040
	52	};
	53
9100edec LV	54	const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
	55	.sdram_config_init = 0x80800EBA,
	56	.sdram_config = 0x808022BA,
	57	.ref_ctrl = 0x0000081A,
	58	.sdram_tim1 = 0x772F6873,
	59	.sdram_tim2 = 0x304a129a,
	60	.sdram_tim3 = 0x02f7e45f,
	61	.read_idle_ctrl = 0x00050000,
	62	.zq_config = 0x100b3215,
	63	.temp_alert_config = 0x08000a05,
	64	.emif_ddr_phy_ctlr_1_init = 0x0E30400d,
	65	.emif_ddr_phy_ctlr_1 = 0x0E30400d,
	66	.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
	67	.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
	68	.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
	69	.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
	70	.emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
	71	};
	72
971f2ba2	73	const struct emif_regs emif_regs_266_mhz_2cs = {
f4010734 S	74	.sdram_config_init = 0x80800EBA,
	75	.sdram_config = 0x808022BA,
	76	.ref_ctrl = 0x0000040D,
	77	.sdram_tim1 = 0x2A86B419,
	78	.sdram_tim2 = 0x1025094A,
	79	.sdram_tim3 = 0x026BA22F,
bb772a59	80	.read_idle_ctrl = 0x00050000,
f4010734 S	81	.zq_config = 0x000b3215,
	82	.temp_alert_config = 0x08000a05,
	83	.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
	84	.emif_ddr_phy_ctlr_1 = 0x0E28420d,
	85	.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
	86	.emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
	87	.emif_ddr_ext_phy_ctrl_3 = 0x14829052,
	88	.emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
	89	.emif_ddr_ext_phy_ctrl_5 = 0x04010040
bb772a59 S	90	};
bb772a59 S	91
43037d76 LV	92	const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
	93	.sdram_config_init = 0x61851B32,
	94	.sdram_config = 0x61851B32,
92b0482c	95	.sdram_config2 = 0x0,
43037d76 LV	96	.ref_ctrl = 0x00001035,
	97	.sdram_tim1 = 0xCCCF36B3,
	98	.sdram_tim2 = 0x308F7FDA,
	99	.sdram_tim3 = 0x027F88A8,
	100	.read_idle_ctrl = 0x00050000,
	101	.zq_config = 0x0007190B,
	102	.temp_alert_config = 0x00000000,
	103	.emif_ddr_phy_ctlr_1_init = 0x0020420A,
	104	.emif_ddr_phy_ctlr_1 = 0x0024420A,
	105	.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
	106	.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
	107	.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
	108	.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
	109	.emif_ddr_ext_phy_ctrl_5 = 0x04010040,
	110	.emif_rd_wr_lvl_rmp_win = 0x00000000,
	111	.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
	112	.emif_rd_wr_lvl_ctl = 0x00000000,
	113	.emif_rd_wr_exec_thresh = 0x00000305
	114	};
	115
9100edec LV	116	const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
	117	.sdram_config_init = 0x61851B32,
	118	.sdram_config = 0x61851B32,
92b0482c	119	.sdram_config2 = 0x0,
9100edec LV	120	.ref_ctrl = 0x00001035,
	121	.sdram_tim1 = 0xCCCF36B3,
	122	.sdram_tim2 = 0x308F7FDA,
	123	.sdram_tim3 = 0x027F88A8,
	124	.read_idle_ctrl = 0x00050000,
	125	.zq_config = 0x1007190B,
	126	.temp_alert_config = 0x00000000,
	127	.emif_ddr_phy_ctlr_1_init = 0x0030400A,
	128	.emif_ddr_phy_ctlr_1 = 0x0034400A,
	129	.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
	130	.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
	131	.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
	132	.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
	133	.emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
	134	.emif_rd_wr_lvl_rmp_win = 0x00000000,
	135	.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
	136	.emif_rd_wr_lvl_ctl = 0x00000000,
	137	.emif_rd_wr_exec_thresh = 0x40000305
	138	};
	139
92b0482c S	140	const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
	141	.sdram_config_init = 0x61851ab2,
	142	.sdram_config = 0x61851ab2,
	143	.sdram_config2 = 0x08000000,
	144	.ref_ctrl = 0x00001035,
	145	.sdram_tim1 = 0xCCCF36B3,
	146	.sdram_tim2 = 0x308F7FDA,
	147	.sdram_tim3 = 0x027F88A8,
f2a1b93b	148	.read_idle_ctrl = 0x00050001,
92b0482c S	149	.zq_config = 0x0007190B,
92b0482c S	150	.temp_alert_config = 0x00000000,
f2a1b93b S	151	.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
f2a1b93b S	152	.emif_ddr_phy_ctlr_1 = 0x0E24400A,
6c70935d	153	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
f2a1b93b S	154	.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
	155	.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
	156	.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
	157	.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
92b0482c	158	.emif_rd_wr_lvl_rmp_win = 0x00000000,
f2a1b93b	159	.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
92b0482c S	160	.emif_rd_wr_lvl_ctl = 0x00000000,
	161	.emif_rd_wr_exec_thresh = 0x00000305
	162	};
	163
	164	const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
	165	.sdram_config_init = 0x61851B32,
	166	.sdram_config = 0x61851B32,
	167	.sdram_config2 = 0x08000000,
	168	.ref_ctrl = 0x00001035,
	169	.sdram_tim1 = 0xCCCF36B3,
	170	.sdram_tim2 = 0x308F7FDA,
	171	.sdram_tim3 = 0x027F88A8,
f2a1b93b	172	.read_idle_ctrl = 0x00050001,
92b0482c S	173	.zq_config = 0x0007190B,
92b0482c S	174	.temp_alert_config = 0x00000000,
f2a1b93b S	175	.emif_ddr_phy_ctlr_1_init = 0x0E24400A,
f2a1b93b S	176	.emif_ddr_phy_ctlr_1 = 0x0E24400A,
6c70935d	177	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
f2a1b93b S	178	.emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
	179	.emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
	180	.emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
	181	.emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
92b0482c	182	.emif_rd_wr_lvl_rmp_win = 0x00000000,
f2a1b93b	183	.emif_rd_wr_lvl_rmp_ctl = 0x00000000,
92b0482c S	184	.emif_rd_wr_lvl_ctl = 0x00000000,
	185	.emif_rd_wr_exec_thresh = 0x00000305
	186	};
	187
f4010734 S	188	const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
f4010734 S	189	.dmm_lisa_map_0 = 0x0,
77efdeb7 S	190	.dmm_lisa_map_1 = 0x0,
77efdeb7 S	191	.dmm_lisa_map_2 = 0x80740300,
7831419d LV	192	.dmm_lisa_map_3 = 0xFF020100,
	193	.is_ma_present = 0x1
	194	};
	195
92b0482c S	196	/*
	197	* DRA752 EVM board has 1.5 GB of memory
	198	* EMIF1 --> 2Gb * 2 = 512MB
	199	* EMIF2 --> 2Gb * 4 = 1GB
	200	* so mapping 1GB interleaved and 512MB non-interleaved
	201	*/
	202	const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
	203	.dmm_lisa_map_0 = 0x0,
	204	.dmm_lisa_map_1 = 0x80640300,
	205	.dmm_lisa_map_2 = 0xC0500220,
	206	.dmm_lisa_map_3 = 0xFF020100,
	207	.is_ma_present = 0x1
	208	};
	209
	210	/*
	211	* DRA752 EVM EMIF1 ONLY CONFIGURATION
	212	*/
	213	const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
7831419d LV	214	.dmm_lisa_map_0 = 0x0,
7831419d LV	215	.dmm_lisa_map_1 = 0x0,
92b0482c S	216	.dmm_lisa_map_2 = 0x80500100,
	217	.dmm_lisa_map_3 = 0xFF020100,
	218	.is_ma_present = 0x1
	219	};
	220
	221	/*
	222	* DRA752 EVM EMIF2 ONLY CONFIGURATION
	223	*/
	224	const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
	225	.dmm_lisa_map_0 = 0x0,
	226	.dmm_lisa_map_1 = 0x0,
	227	.dmm_lisa_map_2 = 0x80600200,
	228	.dmm_lisa_map_3 = 0xFF020100,
7831419d	229	.is_ma_present = 0x1
f4010734 S	230	};
f4010734 S	231
9fcf3d3a LV	232	/*
	233	* DRA722 EVM EMIF1 CONFIGURATION
	234	*/
	235	const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
	236	.dmm_lisa_map_0 = 0x0,
	237	.dmm_lisa_map_1 = 0x0,
	238	.dmm_lisa_map_2 = 0x80600100,
	239	.dmm_lisa_map_3 = 0xFF020100,
	240	.is_ma_present = 0x1
	241	};
	242
e05a4f1f LV	243	static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
	244	{
	245	switch (omap_revision()) {
	246	case OMAP5430_ES1_0:
	247	*regs = &emif_regs_532_mhz_2cs;
	248	break;
	249	case OMAP5432_ES1_0:
	250	*regs = &emif_regs_ddr3_532_mhz_1cs;
	251	break;
9100edec LV	252	case OMAP5430_ES2_0:
	253	*regs = &emif_regs_532_mhz_2cs_es2;
	254	break;
	255	case OMAP5432_ES2_0:
92b0482c S	256	*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
92b0482c S	257	break;
7831419d	258	case DRA752_ES1_0:
3ac8c0bf	259	case DRA752_ES1_1:
92b0482c S	260	switch (emif_nr) {
	261	case 1:
	262	*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
	263	break;
	264	case 2:
	265	*regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
	266	break;
	267	}
	268	break;
9fcf3d3a	269	case DRA722_ES1_0:
e05a4f1f	270	default:
92b0482c	271	*regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
e05a4f1f LV	272	}
	273	}
	274
	275	void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
	276	__attribute__((weak, alias("emif_get_reg_dump_sdp")));
	277
	278	static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
	279	**dmm_lisa_regs)
	280	{
7831419d LV	281	switch (omap_revision()) {
	282	case OMAP5430_ES1_0:
	283	case OMAP5430_ES2_0:
	284	case OMAP5432_ES1_0:
	285	case OMAP5432_ES2_0:
	286	*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
	287	break;
	288	case DRA752_ES1_0:
3ac8c0bf	289	case DRA752_ES1_1:
92b0482c	290	*dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
9fcf3d3a LV	291	break;
	292	case DRA722_ES1_0:
	293	default:
	294	*dmm_lisa_regs = &lisa_map_2G_x_2;
7831419d LV	295	}
7831419d LV	296
e05a4f1f LV	297	}
	298
	299	void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
	300	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
	301	#else
	302
	303	static const struct lpddr2_device_details dev_4G_S4_details = {
	304	.type = LPDDR2_TYPE_S4,
	305	.density = LPDDR2_DENSITY_4Gb,
	306	.io_width = LPDDR2_IO_WIDTH_32,
	307	.manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
	308	};
	309
	310	static void emif_get_device_details_sdp(u32 emif_nr,
	311	struct lpddr2_device_details *cs0_device_details,
	312	struct lpddr2_device_details *cs1_device_details)
	313	{
	314	/* EMIF1 & EMIF2 have identical configuration */
	315	*cs0_device_details = dev_4G_S4_details;
	316	*cs1_device_details = dev_4G_S4_details;
	317	}
	318
	319	void emif_get_device_details(u32 emif_nr,
	320	struct lpddr2_device_details *cs0_device_details,
	321	struct lpddr2_device_details *cs1_device_details)
	322	__attribute__((weak, alias("emif_get_device_details_sdp")));
	323
	324	#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
	325
6c70935d	326	const u32 ext_phy_ctrl_const_base[] = {
f4010734 S	327	0x01004010,
	328	0x00001004,
	329	0x04010040,
	330	0x01004010,
	331	0x00001004,
	332	0x00000000,
	333	0x00000000,
	334	0x00000000,
	335	0x80080080,
	336	0x00800800,
	337	0x08102040,
	338	0x00000001,
	339	0x540A8150,
	340	0xA81502a0,
	341	0x002A0540,
	342	0x00000000,
	343	0x00000000,
	344	0x00000000,
92b0482c S	345	0x00000077,
92b0482c S	346	0x0
bb772a59 S	347	};
bb772a59 S	348
6c70935d	349	const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
43037d76 LV	350	0x01004010,
	351	0x00001004,
	352	0x04010040,
	353	0x01004010,
	354	0x00001004,
	355	0x00000000,
	356	0x00000000,
	357	0x00000000,
	358	0x80080080,
	359	0x00800800,
	360	0x08102040,
	361	0x00000002,
	362	0x0,
	363	0x0,
	364	0x0,
	365	0x00000000,
	366	0x00000000,
	367	0x00000000,
92b0482c S	368	0x00000057,
92b0482c S	369	0x0
43037d76 LV	370	};
43037d76 LV	371
6c70935d	372	const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
9100edec LV	373	0x50D4350D,
	374	0x00000D43,
	375	0x04010040,
	376	0x01004010,
	377	0x00001004,
	378	0x00000000,
	379	0x00000000,
	380	0x00000000,
	381	0x80080080,
	382	0x00800800,
	383	0x08102040,
	384	0x00000002,
	385	0x00000000,
	386	0x00000000,
	387	0x00000000,
	388	0x00000000,
	389	0x00000000,
	390	0x00000000,
92b0482c S	391	0x00000057,
	392	0x0
	393	};
	394
	395	const u32
6c70935d	396	dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
f2a1b93b S	397	0x00BB00BB,
	398	0x00440044,
	399	0x00440044,
	400	0x00440044,
	401	0x00440044,
	402	0x00440044,
	403	0x007F007F,
	404	0x007F007F,
	405	0x007F007F,
	406	0x007F007F,
	407	0x007F007F,
6c70935d S	408	0x00600060,
	409	0x00600060,
	410	0x00600060,
	411	0x00600060,
	412	0x00600060,
f2a1b93b S	413	0x00000000,
f2a1b93b S	414	0x00600020,
92b0482c	415	0x40010080,
6c70935d S	416	0x08102040,
	417	0x0,
	418	0x0,
	419	0x0,
	420	0x0,
	421	0x0
92b0482c S	422	};
	423
	424	const u32
6c70935d S	425	dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
	426	0x00BB00BB,
	427	0x00440044,
	428	0x00440044,
	429	0x00440044,
	430	0x00440044,
	431	0x00440044,
	432	0x007F007F,
	433	0x007F007F,
	434	0x007F007F,
	435	0x007F007F,
	436	0x007F007F,
	437	0x00600060,
	438	0x00600060,
	439	0x00600060,
	440	0x00600060,
	441	0x00600060,
f2a1b93b	442	0x00000000,
6c70935d	443	0x00600020,
92b0482c	444	0x40010080,
6c70935d S	445	0x08102040,
	446	0x0,
	447	0x0,
	448	0x0,
	449	0x0,
	450	0x0
9100edec LV	451	};
9100edec LV	452
e05a4f1f LV	453	const struct lpddr2_mr_regs mr_regs = {
	454	.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
	455	.mr2 = 0x6,
	456	.mr3 = 0x1,
	457	.mr10 = MR10_ZQ_ZQINIT,
	458	.mr16 = MR16_REF_FULL_ARRAY
	459	};
bb772a59	460
6c70935d S	461	static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
	462	const u32 **regs,
	463	u32 *size)
bb772a59	464	{
e05a4f1f LV	465	switch (omap_revision()) {
e05a4f1f LV	466	case OMAP5430_ES1_0:
9100edec	467	case OMAP5430_ES2_0:
e05a4f1f	468	*regs = ext_phy_ctrl_const_base;
6c70935d	469	*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
e05a4f1f LV	470	break;
	471	case OMAP5432_ES1_0:
	472	*regs = ddr3_ext_phy_ctrl_const_base_es1;
6c70935d	473	*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
e05a4f1f	474	break;
9100edec	475	case OMAP5432_ES2_0:
92b0482c	476	*regs = ddr3_ext_phy_ctrl_const_base_es2;
6c70935d	477	*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
92b0482c	478	break;
7831419d	479	case DRA752_ES1_0:
3ac8c0bf	480	case DRA752_ES1_1:
9fcf3d3a	481	case DRA722_ES1_0:
6c70935d	482	if (emif_nr == 1) {
92b0482c	483	*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
6c70935d S	484	*size =
	485	ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
	486	} else {
92b0482c	487	*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
6c70935d S	488	*size =
	489	ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
	490	}
92b0482c	491	break;
e05a4f1f	492	default:
9100edec	493	*regs = ddr3_ext_phy_ctrl_const_base_es2;
6c70935d	494	*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
9100edec	495
e05a4f1f	496	}
bb772a59 S	497	}
bb772a59 S	498
e05a4f1f	499	void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
bb772a59	500	{
e05a4f1f	501	*regs = &mr_regs;
bb772a59 S	502	}
bb772a59 S	503
25476382 S	504	void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
	505	{
	506	u32 *ext_phy_ctrl_base = 0;
	507	u32 *emif_ext_phy_ctrl_base = 0;
92b0482c	508	u32 emif_nr;
e05a4f1f	509	const u32 *ext_phy_ctrl_const_regs;
25476382	510	u32 i = 0;
6c70935d	511	u32 size;
25476382	512
92b0482c S	513	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
92b0482c S	514
25476382 S	515	struct emif_reg_struct emif = (struct emif_reg_struct )base;
	516
	517	ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
	518	emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
	519
	520	/* Configure external phy control timing registers */
	521	for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
	522	writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
	523	/* Update shadow registers */
	524	writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
	525	}
	526
	527	/*
	528	* external phy 6-24 registers do not change with
	529	* ddr frequency
	530	*/
6c70935d S	531	emif_get_ext_phy_ctrl_const_regs(emif_nr,
	532	&ext_phy_ctrl_const_regs, &size);
	533
	534	for (i = 0; i < size; i++) {
e05a4f1f LV	535	writel(ext_phy_ctrl_const_regs[i],
e05a4f1f LV	536	emif_ext_phy_ctrl_base++);
25476382	537	/* Update shadow registers */
e05a4f1f LV	538	writel(ext_phy_ctrl_const_regs[i],
e05a4f1f LV	539	emif_ext_phy_ctrl_base++);
25476382 S	540	}
	541	}
	542
bb772a59 S	543	#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
	544	static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
	545	.max_freq = 532000000,
	546	.RL = 8,
	547	.tRPab = 21,
	548	.tRCD = 18,
	549	.tWR = 15,
	550	.tRASmin = 42,
	551	.tRRD = 10,
	552	.tWTRx2 = 15,
	553	.tXSR = 140,
	554	.tXPx2 = 15,
	555	.tRFCab = 130,
	556	.tRTPx2 = 15,
	557	.tCKE = 3,
	558	.tCKESR = 15,
	559	.tZQCS = 90,
	560	.tZQCL = 360,
	561	.tZQINIT = 1000,
	562	.tDQSCKMAXx2 = 11,
	563	.tRASmax = 70,
	564	.tFAW = 50
	565	};
	566
971f2ba2	567	static const struct lpddr2_min_tck min_tck = {
bb772a59 S	568	.tRL = 3,
	569	.tRP_AB = 3,
	570	.tRCD = 3,
	571	.tWR = 3,
	572	.tRAS_MIN = 3,
	573	.tRRD = 2,
	574	.tWTR = 2,
	575	.tXP = 2,
	576	.tRTP = 2,
	577	.tCKE = 3,
	578	.tCKESR = 3,
	579	.tFAW = 8
	580	};
	581
971f2ba2	582	static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
bb772a59 S	583	&timings_jedec_532_mhz
	584	};
	585
971f2ba2 S	586	static const struct lpddr2_device_timings dev_4G_S4_timings = {
	587	.ac_timings = ac_timings,
	588	.min_tck = &min_tck,
bb772a59 S	589	};
bb772a59 S	590
54d022e7 S	591	/*
	592	* List of status registers to be controlled back to control registers
	593	* after initial leveling
	594	* readreg, writereg
	595	*/
	596	const struct read_write_regs omap5_bug_00339_regs[] = {
	597	{ 8, 5 },
	598	{ 9, 6 },
	599	{ 10, 7 },
	600	{ 14, 8 },
	601	{ 15, 9 },
	602	{ 16, 10 },
	603	{ 11, 2 },
	604	{ 12, 3 },
	605	{ 13, 4 },
	606	{ 17, 11 },
	607	{ 18, 12 },
	608	{ 19, 13 },
	609	};
	610
	611	const struct read_write_regs dra_bug_00339_regs[] = {
	612	{ 7, 7 },
	613	{ 8, 8 },
	614	{ 9, 9 },
	615	{ 10, 10 },
	616	{ 11, 11 },
	617	{ 12, 2 },
	618	{ 13, 3 },
	619	{ 14, 4 },
	620	{ 15, 5 },
	621	{ 16, 6 },
	622	{ 17, 12 },
	623	{ 18, 13 },
	624	{ 19, 14 },
	625	{ 20, 15 },
	626	{ 21, 16 },
	627	{ 22, 17 },
	628	{ 23, 18 },
	629	{ 24, 19 },
	630	{ 25, 20 },
	631	{ 26, 21}
	632	};
	633
	634	const struct read_write_regs get_bug_regs(u32 iterations)
	635	{
	636	const struct read_write_regs *bug_00339_regs_ptr = NULL;
	637
	638	switch (omap_revision()) {
	639	case OMAP5430_ES1_0:
	640	case OMAP5430_ES2_0:
	641	case OMAP5432_ES1_0:
	642	case OMAP5432_ES2_0:
	643	bug_00339_regs_ptr = omap5_bug_00339_regs;
	644	*iterations = sizeof(omap5_bug_00339_regs)/
	645	sizeof(omap5_bug_00339_regs[0]);
	646	break;
	647	case DRA752_ES1_0:
3ac8c0bf	648	case DRA752_ES1_1:
9fcf3d3a	649	case DRA722_ES1_0:
54d022e7 S	650	bug_00339_regs_ptr = dra_bug_00339_regs;
	651	*iterations = sizeof(dra_bug_00339_regs)/
	652	sizeof(dra_bug_00339_regs[0]);
	653	break;
	654	default:
	655	printf("\n Error: UnKnown SOC");
	656	}
	657
	658	return bug_00339_regs_ptr;
	659	}
	660
bb772a59 S	661	void emif_get_device_timings_sdp(u32 emif_nr,
	662	const struct lpddr2_device_timings **cs0_device_timings,
	663	const struct lpddr2_device_timings **cs1_device_timings)
	664	{
	665	/* Identical devices on EMIF1 & EMIF2 */
971f2ba2 S	666	*cs0_device_timings = &dev_4G_S4_timings;
971f2ba2 S	667	*cs1_device_timings = &dev_4G_S4_timings;
bb772a59 S	668	}
	669
	670	void emif_get_device_timings(u32 emif_nr,
	671	const struct lpddr2_device_timings **cs0_device_timings,
	672	const struct lpddr2_device_timings **cs1_device_timings)
	673	__attribute__((weak, alias("emif_get_device_timings_sdp")));
	674
	675	#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */