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cba69eee IC |
1 | /* |
2 | * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net> | |
3 | * | |
4 | * (C) Copyright 2007-2011 | |
5 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
6 | * Tom Cubie <tangliang@allwinnertech.com> | |
7 | * | |
8 | * Some init for sunxi platform. | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #include <common.h> | |
6620377e | 14 | #include <i2c.h> |
5835823d IC |
15 | #include <netdev.h> |
16 | #include <miiphy.h> | |
cba69eee IC |
17 | #include <serial.h> |
18 | #ifdef CONFIG_SPL_BUILD | |
19 | #include <spl.h> | |
20 | #endif | |
21 | #include <asm/gpio.h> | |
22 | #include <asm/io.h> | |
23 | #include <asm/arch/clock.h> | |
24 | #include <asm/arch/gpio.h> | |
25 | #include <asm/arch/sys_proto.h> | |
26 | #include <asm/arch/timer.h> | |
27 | ||
799aff38 IC |
28 | #include <linux/compiler.h> |
29 | ||
942cb0b6 SG |
30 | struct fel_stash { |
31 | uint32_t sp; | |
32 | uint32_t lr; | |
33 | }; | |
34 | ||
35 | struct fel_stash fel_stash __attribute__((section(".data"))); | |
36 | ||
f630974c | 37 | static int gpio_init(void) |
cba69eee | 38 | { |
ff2b47f6 | 39 | #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) |
ed41e62f | 40 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) |
ff2b47f6 CYT |
41 | /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ |
42 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); | |
43 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); | |
44 | #endif | |
45 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX); | |
46 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX); | |
47 | sunxi_gpio_set_pull(SUNXI_GPF(4), 1); | |
ed41e62f | 48 | #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) |
cba69eee IC |
49 | sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); |
50 | sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); | |
ea520947 | 51 | sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); |
ed41e62f | 52 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I) |
f84269c5 HG |
53 | sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); |
54 | sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); | |
ea520947 | 55 | sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); |
ed41e62f | 56 | #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I) |
77115397 MR |
57 | sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX); |
58 | sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX); | |
59 | sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); | |
ed41e62f | 60 | #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) |
f84269c5 HG |
61 | sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); |
62 | sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); | |
ea520947 | 63 | sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); |
ed41e62f | 64 | #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) |
c757a50b CYT |
65 | sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX); |
66 | sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX); | |
67 | sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); | |
f84269c5 HG |
68 | #else |
69 | #error Unsupported console port number. Please fix pin mux settings in board.c | |
70 | #endif | |
cba69eee IC |
71 | |
72 | return 0; | |
73 | } | |
74 | ||
942cb0b6 SG |
75 | void spl_board_load_image(void) |
76 | { | |
77 | debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); | |
78 | return_to_fel(fel_stash.sp, fel_stash.lr); | |
79 | } | |
80 | ||
b56f6e2b | 81 | void s_init(void) |
f630974c SG |
82 | { |
83 | #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I | |
84 | /* Magic (undocmented) value taken from boot0, without this DRAM | |
85 | * access gets messed up (seems cache related) */ | |
86 | setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); | |
87 | #endif | |
88 | #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \ | |
89 | defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I) | |
90 | /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ | |
91 | asm volatile( | |
92 | "mrc p15, 0, r0, c1, c0, 1\n" | |
93 | "orr r0, r0, #1 << 6\n" | |
94 | "mcr p15, 0, r0, c1, c0, 1\n"); | |
95 | #endif | |
96 | ||
97 | clock_init(); | |
98 | timer_init(); | |
99 | gpio_init(); | |
100 | i2c_init_board(); | |
b56f6e2b | 101 | } |
f630974c | 102 | |
b56f6e2b HG |
103 | #ifdef CONFIG_SPL_BUILD |
104 | /* The sunxi internal brom will try to loader external bootloader | |
105 | * from mmc0, nand flash, mmc2. | |
106 | * Unfortunately we can't check how SPL was loaded so assume | |
107 | * it's always the first SD/MMC controller | |
108 | */ | |
109 | u32 spl_boot_device(void) | |
110 | { | |
942cb0b6 SG |
111 | /* |
112 | * Have we been asked to return to the FEL portion of the boot ROM? | |
113 | * TODO: We need a more robust test here, or bracket this with | |
114 | * #ifdef CONFIG_SPL_FEL. | |
115 | */ | |
116 | if (fel_stash.lr >= 0xffff0000 && fel_stash.lr < 0xffff4000) | |
117 | return BOOT_DEVICE_BOARD; | |
118 | ||
b56f6e2b HG |
119 | return BOOT_DEVICE_MMC1; |
120 | } | |
121 | ||
122 | /* No confirmation data available in SPL yet. Hardcode bootmode */ | |
123 | u32 spl_boot_mode(void) | |
124 | { | |
125 | return MMCSD_MODE_RAW; | |
126 | } | |
127 | ||
128 | void board_init_f(ulong dummy) | |
129 | { | |
f630974c SG |
130 | preloader_console_init(); |
131 | ||
132 | #ifdef CONFIG_SPL_I2C_SUPPORT | |
133 | /* Needed early by sunxi_board_init if PMU is enabled */ | |
134 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
135 | #endif | |
136 | sunxi_board_init(); | |
137 | ||
138 | /* Clear the BSS. */ | |
139 | memset(__bss_start, 0, __bss_end - __bss_start); | |
140 | ||
141 | board_init_r(NULL, 0); | |
142 | } | |
143 | #endif | |
144 | ||
cba69eee IC |
145 | void reset_cpu(ulong addr) |
146 | { | |
ed41e62f | 147 | #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) |
c7e79dec HG |
148 | static const struct sunxi_wdog *wdog = |
149 | &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; | |
150 | ||
151 | /* Set the watchdog for its shortest interval (.5s) and wait */ | |
152 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); | |
153 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); | |
ae5de5a1 HG |
154 | |
155 | while (1) { | |
156 | /* sun5i sometimes gets stuck without this */ | |
157 | writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); | |
158 | } | |
ed41e62f | 159 | #else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */ |
78c396a1 CYT |
160 | static const struct sunxi_wdog *wdog = |
161 | ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; | |
162 | ||
163 | /* Set the watchdog for its shortest interval (.5s) and wait */ | |
164 | writel(WDT_CFG_RESET, &wdog->cfg); | |
165 | writel(WDT_MODE_EN, &wdog->mode); | |
166 | writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl); | |
167 | #endif | |
cba69eee IC |
168 | } |
169 | ||
cba69eee IC |
170 | #ifndef CONFIG_SYS_DCACHE_OFF |
171 | void enable_caches(void) | |
172 | { | |
173 | /* Enable D-cache. I-cache is already enabled in start.S */ | |
174 | dcache_enable(); | |
175 | } | |
176 | #endif | |
5835823d IC |
177 | |
178 | #ifdef CONFIG_CMD_NET | |
179 | /* | |
180 | * Initializes on-chip ethernet controllers. | |
181 | * to override, implement board_eth_init() | |
182 | */ | |
183 | int cpu_eth_init(bd_t *bis) | |
184 | { | |
799aff38 | 185 | __maybe_unused int rc; |
5835823d | 186 | |
fc703001 HG |
187 | #ifdef CONFIG_MACPWR |
188 | gpio_direction_output(CONFIG_MACPWR, 1); | |
189 | mdelay(200); | |
190 | #endif | |
191 | ||
c26fb9db HG |
192 | #ifdef CONFIG_SUNXI_EMAC |
193 | rc = sunxi_emac_initialize(bis); | |
194 | if (rc < 0) { | |
195 | printf("sunxi: failed to initialize emac\n"); | |
196 | return rc; | |
197 | } | |
198 | #endif | |
199 | ||
5835823d IC |
200 | #ifdef CONFIG_SUNXI_GMAC |
201 | rc = sunxi_gmac_initialize(bis); | |
202 | if (rc < 0) { | |
203 | printf("sunxi: failed to initialize gmac\n"); | |
204 | return rc; | |
205 | } | |
206 | #endif | |
207 | ||
208 | return 0; | |
209 | } | |
210 | #endif |