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44303dfa MS |
1 | /* |
2 | * dts file for Xilinx ZynqMP | |
3 | * | |
4 | * (C) Copyright 2014 - 2015, Xilinx, Inc. | |
5 | * | |
6 | * Michal Simek <michal.simek@xilinx.com> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
91d11536 | 10 | |
44303dfa MS |
11 | / { |
12 | compatible = "xlnx,zynqmp"; | |
13 | #address-cells = <2>; | |
85d1142e | 14 | #size-cells = <2>; |
44303dfa MS |
15 | |
16 | cpus { | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
585ca873 | 20 | cpu0: cpu@0 { |
44303dfa MS |
21 | compatible = "arm,cortex-a53", "arm,armv8"; |
22 | device_type = "cpu"; | |
23 | enable-method = "psci"; | |
941f61fe | 24 | operating-points-v2 = <&cpu_opp_table>; |
44303dfa | 25 | reg = <0x0>; |
2e15b071 | 26 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
27 | }; |
28 | ||
585ca873 | 29 | cpu1: cpu@1 { |
44303dfa MS |
30 | compatible = "arm,cortex-a53", "arm,armv8"; |
31 | device_type = "cpu"; | |
32 | enable-method = "psci"; | |
33 | reg = <0x1>; | |
941f61fe | 34 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 | 35 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
36 | }; |
37 | ||
585ca873 | 38 | cpu2: cpu@2 { |
44303dfa MS |
39 | compatible = "arm,cortex-a53", "arm,armv8"; |
40 | device_type = "cpu"; | |
41 | enable-method = "psci"; | |
42 | reg = <0x2>; | |
941f61fe | 43 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 | 44 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
45 | }; |
46 | ||
585ca873 | 47 | cpu3: cpu@3 { |
44303dfa MS |
48 | compatible = "arm,cortex-a53", "arm,armv8"; |
49 | device_type = "cpu"; | |
50 | enable-method = "psci"; | |
51 | reg = <0x3>; | |
941f61fe | 52 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 SK |
53 | cpu-idle-states = <&CPU_SLEEP_0>; |
54 | }; | |
55 | ||
56 | idle-states { | |
fec54739 | 57 | entry-method = "arm,psci"; |
2e15b071 SK |
58 | |
59 | CPU_SLEEP_0: cpu-sleep-0 { | |
60 | compatible = "arm,idle-state"; | |
61 | arm,psci-suspend-param = <0x40000000>; | |
62 | local-timer-stop; | |
63 | entry-latency-us = <300>; | |
64 | exit-latency-us = <600>; | |
6a097b0d | 65 | min-residency-us = <10000>; |
2e15b071 | 66 | }; |
44303dfa MS |
67 | }; |
68 | }; | |
69 | ||
941f61fe SD |
70 | cpu_opp_table: cpu_opp_table { |
71 | compatible = "operating-points-v2"; | |
72 | opp-shared; | |
73 | opp00 { | |
74 | opp-hz = /bits/ 64 <1199999988>; | |
75 | opp-microvolt = <1000000>; | |
76 | clock-latency-ns = <500000>; | |
77 | }; | |
78 | opp01 { | |
79 | opp-hz = /bits/ 64 <599999994>; | |
80 | opp-microvolt = <1000000>; | |
81 | clock-latency-ns = <500000>; | |
82 | }; | |
83 | opp02 { | |
84 | opp-hz = /bits/ 64 <399999996>; | |
85 | opp-microvolt = <1000000>; | |
86 | clock-latency-ns = <500000>; | |
87 | }; | |
88 | opp03 { | |
89 | opp-hz = /bits/ 64 <299999997>; | |
90 | opp-microvolt = <1000000>; | |
91 | clock-latency-ns = <500000>; | |
92 | }; | |
93 | }; | |
94 | ||
69d09dd7 MS |
95 | dcc: dcc { |
96 | compatible = "arm,dcc"; | |
97 | status = "disabled"; | |
98 | u-boot,dm-pre-reloc; | |
99 | }; | |
100 | ||
8f4e3972 SB |
101 | power-domains { |
102 | compatible = "xlnx,zynqmp-genpd"; | |
103 | ||
104 | pd_usb0: pd-usb0 { | |
105 | #power-domain-cells = <0x0>; | |
106 | pd-id = <0x16>; | |
107 | }; | |
108 | ||
109 | pd_usb1: pd-usb1 { | |
110 | #power-domain-cells = <0x0>; | |
111 | pd-id = <0x17>; | |
112 | }; | |
113 | ||
114 | pd_sata: pd-sata { | |
115 | #power-domain-cells = <0x0>; | |
116 | pd-id = <0x1c>; | |
117 | }; | |
118 | ||
119 | pd_spi0: pd-spi0 { | |
120 | #power-domain-cells = <0x0>; | |
121 | pd-id = <0x23>; | |
122 | }; | |
123 | ||
124 | pd_spi1: pd-spi1 { | |
125 | #power-domain-cells = <0x0>; | |
126 | pd-id = <0x24>; | |
127 | }; | |
128 | ||
129 | pd_uart0: pd-uart0 { | |
130 | #power-domain-cells = <0x0>; | |
131 | pd-id = <0x21>; | |
132 | }; | |
133 | ||
134 | pd_uart1: pd-uart1 { | |
135 | #power-domain-cells = <0x0>; | |
136 | pd-id = <0x22>; | |
137 | }; | |
138 | ||
139 | pd_eth0: pd-eth0 { | |
140 | #power-domain-cells = <0x0>; | |
141 | pd-id = <0x1d>; | |
142 | }; | |
143 | ||
144 | pd_eth1: pd-eth1 { | |
145 | #power-domain-cells = <0x0>; | |
146 | pd-id = <0x1e>; | |
147 | }; | |
148 | ||
149 | pd_eth2: pd-eth2 { | |
150 | #power-domain-cells = <0x0>; | |
151 | pd-id = <0x1f>; | |
152 | }; | |
153 | ||
154 | pd_eth3: pd-eth3 { | |
155 | #power-domain-cells = <0x0>; | |
156 | pd-id = <0x20>; | |
157 | }; | |
158 | ||
159 | pd_i2c0: pd-i2c0 { | |
160 | #power-domain-cells = <0x0>; | |
161 | pd-id = <0x25>; | |
162 | }; | |
163 | ||
164 | pd_i2c1: pd-i2c1 { | |
165 | #power-domain-cells = <0x0>; | |
166 | pd-id = <0x26>; | |
167 | }; | |
168 | ||
169 | pd_dp: pd-dp { | |
170 | /* fixme: what to attach to */ | |
171 | #power-domain-cells = <0x0>; | |
172 | pd-id = <0x29>; | |
173 | }; | |
174 | ||
175 | pd_gdma: pd-gdma { | |
176 | #power-domain-cells = <0x0>; | |
177 | pd-id = <0x2a>; | |
178 | }; | |
179 | ||
180 | pd_adma: pd-adma { | |
181 | #power-domain-cells = <0x0>; | |
182 | pd-id = <0x2b>; | |
183 | }; | |
184 | ||
185 | pd_ttc0: pd-ttc0 { | |
186 | #power-domain-cells = <0x0>; | |
187 | pd-id = <0x18>; | |
188 | }; | |
189 | ||
190 | pd_ttc1: pd-ttc1 { | |
191 | #power-domain-cells = <0x0>; | |
192 | pd-id = <0x19>; | |
193 | }; | |
194 | ||
195 | pd_ttc2: pd-ttc2 { | |
196 | #power-domain-cells = <0x0>; | |
197 | pd-id = <0x1a>; | |
198 | }; | |
199 | ||
200 | pd_ttc3: pd-ttc3 { | |
201 | #power-domain-cells = <0x0>; | |
202 | pd-id = <0x1b>; | |
203 | }; | |
204 | ||
205 | pd_sd0: pd-sd0 { | |
206 | #power-domain-cells = <0x0>; | |
207 | pd-id = <0x27>; | |
208 | }; | |
209 | ||
210 | pd_sd1: pd-sd1 { | |
211 | #power-domain-cells = <0x0>; | |
212 | pd-id = <0x28>; | |
213 | }; | |
214 | ||
215 | pd_nand: pd-nand { | |
216 | #power-domain-cells = <0x0>; | |
217 | pd-id = <0x2c>; | |
218 | }; | |
219 | ||
220 | pd_qspi: pd-qspi { | |
221 | #power-domain-cells = <0x0>; | |
222 | pd-id = <0x2d>; | |
223 | }; | |
224 | ||
225 | pd_gpio: pd-gpio { | |
226 | #power-domain-cells = <0x0>; | |
227 | pd-id = <0x2e>; | |
228 | }; | |
229 | ||
230 | pd_can0: pd-can0 { | |
231 | #power-domain-cells = <0x0>; | |
232 | pd-id = <0x2f>; | |
233 | }; | |
234 | ||
235 | pd_can1: pd-can1 { | |
236 | #power-domain-cells = <0x0>; | |
237 | pd-id = <0x30>; | |
238 | }; | |
2af3932f FD |
239 | |
240 | pd_pcie: pd-pcie { | |
241 | #power-domain-cells = <0x0>; | |
242 | pd-id = <0x3b>; | |
243 | }; | |
244 | ||
245 | pd_gpu: pd-gpu { | |
246 | #power-domain-cells = <0x0>; | |
a4d7d560 | 247 | pd-id = <0x3a 0x14 0x15>; |
2af3932f | 248 | }; |
8f4e3972 SB |
249 | }; |
250 | ||
44303dfa MS |
251 | pmu { |
252 | compatible = "arm,armv8-pmuv3"; | |
14cd9eab | 253 | interrupt-parent = <&gic>; |
44303dfa MS |
254 | interrupts = <0 143 4>, |
255 | <0 144 4>, | |
256 | <0 145 4>, | |
257 | <0 146 4>; | |
258 | }; | |
259 | ||
260 | psci { | |
261 | compatible = "arm,psci-0.2"; | |
262 | method = "smc"; | |
263 | }; | |
264 | ||
265 | firmware { | |
266 | compatible = "xlnx,zynqmp-pm"; | |
267 | method = "smc"; | |
19ee402d SB |
268 | interrupt-parent = <&gic>; |
269 | interrupts = <0 35 4>; | |
44303dfa MS |
270 | }; |
271 | ||
272 | timer { | |
273 | compatible = "arm,armv8-timer"; | |
274 | interrupt-parent = <&gic>; | |
6db82e09 MS |
275 | interrupts = <1 13 0xf08>, |
276 | <1 14 0xf08>, | |
277 | <1 11 0xf08>, | |
278 | <1 10 0xf08>; | |
44303dfa MS |
279 | }; |
280 | ||
aaf232f3 NSR |
281 | edac { |
282 | compatible = "arm,cortex-a53-edac"; | |
283 | }; | |
284 | ||
7689dce7 NM |
285 | fpga_full: fpga-full { |
286 | compatible = "fpga-region"; | |
287 | fpga-mgr = <&pcap>; | |
288 | #address-cells = <2>; | |
289 | #size-cells = <2>; | |
290 | }; | |
291 | ||
292 | pcap: pcap { | |
d64e43f1 NM |
293 | compatible = "xlnx,zynqmp-pcap-fpga"; |
294 | }; | |
295 | ||
c926e6fb | 296 | amba_apu: amba_apu@0 { |
44303dfa MS |
297 | compatible = "simple-bus"; |
298 | #address-cells = <2>; | |
299 | #size-cells = <1>; | |
85d1142e | 300 | ranges = <0 0 0 0 0xffffffff>; |
44303dfa MS |
301 | |
302 | gic: interrupt-controller@f9010000 { | |
303 | compatible = "arm,gic-400", "arm,cortex-a15-gic"; | |
304 | #interrupt-cells = <3>; | |
305 | reg = <0x0 0xf9010000 0x10000>, | |
0a8c4f67 | 306 | <0x0 0xf9020000 0x20000>, |
44303dfa | 307 | <0x0 0xf9040000 0x20000>, |
0a8c4f67 | 308 | <0x0 0xf9060000 0x20000>; |
44303dfa MS |
309 | interrupt-controller; |
310 | interrupt-parent = <&gic>; | |
311 | interrupts = <1 9 0xf04>; | |
312 | }; | |
313 | }; | |
314 | ||
b976fd63 | 315 | amba: amba { |
44303dfa | 316 | compatible = "simple-bus"; |
c9811e14 | 317 | u-boot,dm-pre-reloc; |
44303dfa | 318 | #address-cells = <2>; |
b976fd63 MS |
319 | #size-cells = <2>; |
320 | ranges; | |
44303dfa MS |
321 | |
322 | can0: can@ff060000 { | |
323 | compatible = "xlnx,zynq-can-1.0"; | |
324 | status = "disabled"; | |
325 | clock-names = "can_clk", "pclk"; | |
b976fd63 | 326 | reg = <0x0 0xff060000 0x0 0x1000>; |
44303dfa MS |
327 | interrupts = <0 23 4>; |
328 | interrupt-parent = <&gic>; | |
329 | tx-fifo-depth = <0x40>; | |
330 | rx-fifo-depth = <0x40>; | |
8f4e3972 | 331 | power-domains = <&pd_can0>; |
44303dfa MS |
332 | }; |
333 | ||
334 | can1: can@ff070000 { | |
335 | compatible = "xlnx,zynq-can-1.0"; | |
336 | status = "disabled"; | |
337 | clock-names = "can_clk", "pclk"; | |
b976fd63 | 338 | reg = <0x0 0xff070000 0x0 0x1000>; |
44303dfa MS |
339 | interrupts = <0 24 4>; |
340 | interrupt-parent = <&gic>; | |
341 | tx-fifo-depth = <0x40>; | |
342 | rx-fifo-depth = <0x40>; | |
8f4e3972 | 343 | power-domains = <&pd_can1>; |
44303dfa MS |
344 | }; |
345 | ||
ff50d21b MS |
346 | cci: cci@fd6e0000 { |
347 | compatible = "arm,cci-400"; | |
b976fd63 | 348 | reg = <0x0 0xfd6e0000 0x0 0x9000>; |
ff50d21b MS |
349 | ranges = <0x0 0x0 0xfd6e0000 0x10000>; |
350 | #address-cells = <1>; | |
351 | #size-cells = <1>; | |
352 | ||
353 | pmu@9000 { | |
354 | compatible = "arm,cci-400-pmu,r1"; | |
355 | reg = <0x9000 0x5000>; | |
356 | interrupt-parent = <&gic>; | |
357 | interrupts = <0 123 4>, | |
358 | <0 123 4>, | |
359 | <0 123 4>, | |
360 | <0 123 4>, | |
361 | <0 123 4>; | |
362 | }; | |
363 | }; | |
364 | ||
44303dfa MS |
365 | /* GDMA */ |
366 | fpd_dma_chan1: dma@fd500000 { | |
367 | status = "disabled"; | |
368 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 369 | reg = <0x0 0xfd500000 0x0 0x1000>; |
44303dfa MS |
370 | interrupt-parent = <&gic>; |
371 | interrupts = <0 124 4>; | |
b34d11de | 372 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 373 | xlnx,bus-width = <128>; |
ba6ad317 MS |
374 | #stream-id-cells = <1>; |
375 | iommus = <&smmu 0x14e8>; | |
8f4e3972 | 376 | power-domains = <&pd_gdma>; |
44303dfa MS |
377 | }; |
378 | ||
379 | fpd_dma_chan2: dma@fd510000 { | |
380 | status = "disabled"; | |
381 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 382 | reg = <0x0 0xfd510000 0x0 0x1000>; |
44303dfa MS |
383 | interrupt-parent = <&gic>; |
384 | interrupts = <0 125 4>; | |
b34d11de | 385 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 386 | xlnx,bus-width = <128>; |
ba6ad317 MS |
387 | #stream-id-cells = <1>; |
388 | iommus = <&smmu 0x14e9>; | |
8f4e3972 | 389 | power-domains = <&pd_gdma>; |
44303dfa MS |
390 | }; |
391 | ||
392 | fpd_dma_chan3: dma@fd520000 { | |
393 | status = "disabled"; | |
394 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 395 | reg = <0x0 0xfd520000 0x0 0x1000>; |
44303dfa MS |
396 | interrupt-parent = <&gic>; |
397 | interrupts = <0 126 4>; | |
b34d11de | 398 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 399 | xlnx,bus-width = <128>; |
ba6ad317 MS |
400 | #stream-id-cells = <1>; |
401 | iommus = <&smmu 0x14ea>; | |
8f4e3972 | 402 | power-domains = <&pd_gdma>; |
44303dfa MS |
403 | }; |
404 | ||
405 | fpd_dma_chan4: dma@fd530000 { | |
406 | status = "disabled"; | |
407 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 408 | reg = <0x0 0xfd530000 0x0 0x1000>; |
44303dfa MS |
409 | interrupt-parent = <&gic>; |
410 | interrupts = <0 127 4>; | |
b34d11de | 411 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 412 | xlnx,bus-width = <128>; |
ba6ad317 MS |
413 | #stream-id-cells = <1>; |
414 | iommus = <&smmu 0x14eb>; | |
8f4e3972 | 415 | power-domains = <&pd_gdma>; |
44303dfa MS |
416 | }; |
417 | ||
418 | fpd_dma_chan5: dma@fd540000 { | |
419 | status = "disabled"; | |
420 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 421 | reg = <0x0 0xfd540000 0x0 0x1000>; |
44303dfa MS |
422 | interrupt-parent = <&gic>; |
423 | interrupts = <0 128 4>; | |
b34d11de | 424 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 425 | xlnx,bus-width = <128>; |
ba6ad317 MS |
426 | #stream-id-cells = <1>; |
427 | iommus = <&smmu 0x14ec>; | |
8f4e3972 | 428 | power-domains = <&pd_gdma>; |
44303dfa MS |
429 | }; |
430 | ||
431 | fpd_dma_chan6: dma@fd550000 { | |
432 | status = "disabled"; | |
433 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 434 | reg = <0x0 0xfd550000 0x0 0x1000>; |
44303dfa MS |
435 | interrupt-parent = <&gic>; |
436 | interrupts = <0 129 4>; | |
b34d11de | 437 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 438 | xlnx,bus-width = <128>; |
ba6ad317 MS |
439 | #stream-id-cells = <1>; |
440 | iommus = <&smmu 0x14ed>; | |
8f4e3972 | 441 | power-domains = <&pd_gdma>; |
44303dfa MS |
442 | }; |
443 | ||
444 | fpd_dma_chan7: dma@fd560000 { | |
445 | status = "disabled"; | |
446 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 447 | reg = <0x0 0xfd560000 0x0 0x1000>; |
44303dfa MS |
448 | interrupt-parent = <&gic>; |
449 | interrupts = <0 130 4>; | |
b34d11de | 450 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 451 | xlnx,bus-width = <128>; |
ba6ad317 MS |
452 | #stream-id-cells = <1>; |
453 | iommus = <&smmu 0x14ee>; | |
8f4e3972 | 454 | power-domains = <&pd_gdma>; |
44303dfa MS |
455 | }; |
456 | ||
457 | fpd_dma_chan8: dma@fd570000 { | |
458 | status = "disabled"; | |
459 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 460 | reg = <0x0 0xfd570000 0x0 0x1000>; |
44303dfa MS |
461 | interrupt-parent = <&gic>; |
462 | interrupts = <0 131 4>; | |
b34d11de | 463 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 464 | xlnx,bus-width = <128>; |
ba6ad317 MS |
465 | #stream-id-cells = <1>; |
466 | iommus = <&smmu 0x14ef>; | |
8f4e3972 | 467 | power-domains = <&pd_gdma>; |
44303dfa MS |
468 | }; |
469 | ||
470 | gpu: gpu@fd4b0000 { | |
471 | status = "disabled"; | |
472 | compatible = "arm,mali-400", "arm,mali-utgard"; | |
834ec8e9 | 473 | reg = <0x0 0xfd4b0000 0x0 0x10000>; |
44303dfa MS |
474 | interrupt-parent = <&gic>; |
475 | interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; | |
476 | interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; | |
59206dd1 | 477 | clock-names = "gpu", "gpu_pp0", "gpu_pp1"; |
2af3932f | 478 | power-domains = <&pd_gpu>; |
44303dfa MS |
479 | }; |
480 | ||
6af57737 KA |
481 | /* LPDDMA default allows only secured access. inorder to enable |
482 | * These dma channels, Users should ensure that these dma | |
483 | * Channels are allowed for non secure access. | |
484 | */ | |
44303dfa MS |
485 | lpd_dma_chan1: dma@ffa80000 { |
486 | status = "disabled"; | |
487 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 488 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 489 | reg = <0x0 0xffa80000 0x0 0x1000>; |
44303dfa MS |
490 | interrupt-parent = <&gic>; |
491 | interrupts = <0 77 4>; | |
44303dfa | 492 | xlnx,bus-width = <64>; |
ba6ad317 MS |
493 | #stream-id-cells = <1>; |
494 | iommus = <&smmu 0x868>; | |
8f4e3972 | 495 | power-domains = <&pd_adma>; |
44303dfa MS |
496 | }; |
497 | ||
498 | lpd_dma_chan2: dma@ffa90000 { | |
499 | status = "disabled"; | |
500 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 501 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 502 | reg = <0x0 0xffa90000 0x0 0x1000>; |
44303dfa MS |
503 | interrupt-parent = <&gic>; |
504 | interrupts = <0 78 4>; | |
44303dfa | 505 | xlnx,bus-width = <64>; |
ba6ad317 MS |
506 | #stream-id-cells = <1>; |
507 | iommus = <&smmu 0x869>; | |
8f4e3972 | 508 | power-domains = <&pd_adma>; |
44303dfa MS |
509 | }; |
510 | ||
511 | lpd_dma_chan3: dma@ffaa0000 { | |
512 | status = "disabled"; | |
513 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 514 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 515 | reg = <0x0 0xffaa0000 0x0 0x1000>; |
44303dfa MS |
516 | interrupt-parent = <&gic>; |
517 | interrupts = <0 79 4>; | |
44303dfa | 518 | xlnx,bus-width = <64>; |
ba6ad317 MS |
519 | #stream-id-cells = <1>; |
520 | iommus = <&smmu 0x86a>; | |
8f4e3972 | 521 | power-domains = <&pd_adma>; |
44303dfa MS |
522 | }; |
523 | ||
524 | lpd_dma_chan4: dma@ffab0000 { | |
525 | status = "disabled"; | |
526 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 527 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 528 | reg = <0x0 0xffab0000 0x0 0x1000>; |
44303dfa MS |
529 | interrupt-parent = <&gic>; |
530 | interrupts = <0 80 4>; | |
44303dfa | 531 | xlnx,bus-width = <64>; |
ba6ad317 MS |
532 | #stream-id-cells = <1>; |
533 | iommus = <&smmu 0x86b>; | |
8f4e3972 | 534 | power-domains = <&pd_adma>; |
44303dfa MS |
535 | }; |
536 | ||
537 | lpd_dma_chan5: dma@ffac0000 { | |
538 | status = "disabled"; | |
539 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 540 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 541 | reg = <0x0 0xffac0000 0x0 0x1000>; |
44303dfa MS |
542 | interrupt-parent = <&gic>; |
543 | interrupts = <0 81 4>; | |
44303dfa | 544 | xlnx,bus-width = <64>; |
ba6ad317 MS |
545 | #stream-id-cells = <1>; |
546 | iommus = <&smmu 0x86c>; | |
8f4e3972 | 547 | power-domains = <&pd_adma>; |
44303dfa MS |
548 | }; |
549 | ||
550 | lpd_dma_chan6: dma@ffad0000 { | |
551 | status = "disabled"; | |
552 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 553 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 554 | reg = <0x0 0xffad0000 0x0 0x1000>; |
44303dfa MS |
555 | interrupt-parent = <&gic>; |
556 | interrupts = <0 82 4>; | |
44303dfa | 557 | xlnx,bus-width = <64>; |
ba6ad317 MS |
558 | #stream-id-cells = <1>; |
559 | iommus = <&smmu 0x86d>; | |
8f4e3972 | 560 | power-domains = <&pd_adma>; |
44303dfa MS |
561 | }; |
562 | ||
563 | lpd_dma_chan7: dma@ffae0000 { | |
564 | status = "disabled"; | |
565 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 566 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 567 | reg = <0x0 0xffae0000 0x0 0x1000>; |
44303dfa MS |
568 | interrupt-parent = <&gic>; |
569 | interrupts = <0 83 4>; | |
44303dfa | 570 | xlnx,bus-width = <64>; |
ba6ad317 MS |
571 | #stream-id-cells = <1>; |
572 | iommus = <&smmu 0x86e>; | |
8f4e3972 | 573 | power-domains = <&pd_adma>; |
44303dfa MS |
574 | }; |
575 | ||
576 | lpd_dma_chan8: dma@ffaf0000 { | |
577 | status = "disabled"; | |
578 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 579 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 580 | reg = <0x0 0xffaf0000 0x0 0x1000>; |
44303dfa MS |
581 | interrupt-parent = <&gic>; |
582 | interrupts = <0 84 4>; | |
44303dfa | 583 | xlnx,bus-width = <64>; |
ba6ad317 MS |
584 | #stream-id-cells = <1>; |
585 | iommus = <&smmu 0x86f>; | |
8f4e3972 | 586 | power-domains = <&pd_adma>; |
44303dfa MS |
587 | }; |
588 | ||
90869009 NSR |
589 | mc: memory-controller@fd070000 { |
590 | compatible = "xlnx,zynqmp-ddrc-2.40a"; | |
b976fd63 | 591 | reg = <0x0 0xfd070000 0x0 0x30000>; |
90869009 NSR |
592 | interrupt-parent = <&gic>; |
593 | interrupts = <0 112 4>; | |
594 | }; | |
595 | ||
44303dfa MS |
596 | nand0: nand@ff100000 { |
597 | compatible = "arasan,nfc-v3p10"; | |
598 | status = "disabled"; | |
b976fd63 | 599 | reg = <0x0 0xff100000 0x0 0x1000>; |
44303dfa MS |
600 | clock-names = "clk_sys", "clk_flash"; |
601 | interrupt-parent = <&gic>; | |
602 | interrupts = <0 14 4>; | |
603 | #address-cells = <2>; | |
604 | #size-cells = <1>; | |
ba6ad317 MS |
605 | #stream-id-cells = <1>; |
606 | iommus = <&smmu 0x872>; | |
8f4e3972 | 607 | power-domains = <&pd_nand>; |
44303dfa MS |
608 | }; |
609 | ||
610 | gem0: ethernet@ff0b0000 { | |
da2ad784 | 611 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
612 | status = "disabled"; |
613 | interrupt-parent = <&gic>; | |
614 | interrupts = <0 57 4>, <0 57 4>; | |
b976fd63 | 615 | reg = <0x0 0xff0b0000 0x0 0x1000>; |
44303dfa MS |
616 | clock-names = "pclk", "hclk", "tx_clk"; |
617 | #address-cells = <1>; | |
618 | #size-cells = <0>; | |
7f1d7d97 | 619 | #stream-id-cells = <1>; |
ba6ad317 | 620 | iommus = <&smmu 0x874>; |
8f4e3972 | 621 | power-domains = <&pd_eth0>; |
44303dfa MS |
622 | }; |
623 | ||
624 | gem1: ethernet@ff0c0000 { | |
da2ad784 | 625 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
626 | status = "disabled"; |
627 | interrupt-parent = <&gic>; | |
628 | interrupts = <0 59 4>, <0 59 4>; | |
b976fd63 | 629 | reg = <0x0 0xff0c0000 0x0 0x1000>; |
44303dfa MS |
630 | clock-names = "pclk", "hclk", "tx_clk"; |
631 | #address-cells = <1>; | |
632 | #size-cells = <0>; | |
7f1d7d97 | 633 | #stream-id-cells = <1>; |
ba6ad317 | 634 | iommus = <&smmu 0x875>; |
8f4e3972 | 635 | power-domains = <&pd_eth1>; |
44303dfa MS |
636 | }; |
637 | ||
638 | gem2: ethernet@ff0d0000 { | |
da2ad784 | 639 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
640 | status = "disabled"; |
641 | interrupt-parent = <&gic>; | |
642 | interrupts = <0 61 4>, <0 61 4>; | |
b976fd63 | 643 | reg = <0x0 0xff0d0000 0x0 0x1000>; |
44303dfa MS |
644 | clock-names = "pclk", "hclk", "tx_clk"; |
645 | #address-cells = <1>; | |
646 | #size-cells = <0>; | |
7f1d7d97 | 647 | #stream-id-cells = <1>; |
ba6ad317 | 648 | iommus = <&smmu 0x876>; |
8f4e3972 | 649 | power-domains = <&pd_eth2>; |
44303dfa MS |
650 | }; |
651 | ||
652 | gem3: ethernet@ff0e0000 { | |
da2ad784 | 653 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
654 | status = "disabled"; |
655 | interrupt-parent = <&gic>; | |
656 | interrupts = <0 63 4>, <0 63 4>; | |
b976fd63 | 657 | reg = <0x0 0xff0e0000 0x0 0x1000>; |
44303dfa MS |
658 | clock-names = "pclk", "hclk", "tx_clk"; |
659 | #address-cells = <1>; | |
660 | #size-cells = <0>; | |
7f1d7d97 | 661 | #stream-id-cells = <1>; |
ba6ad317 | 662 | iommus = <&smmu 0x877>; |
8f4e3972 | 663 | power-domains = <&pd_eth3>; |
44303dfa MS |
664 | }; |
665 | ||
666 | gpio: gpio@ff0a0000 { | |
667 | compatible = "xlnx,zynqmp-gpio-1.0"; | |
668 | status = "disabled"; | |
669 | #gpio-cells = <0x2>; | |
670 | interrupt-parent = <&gic>; | |
671 | interrupts = <0 16 4>; | |
9e826b68 MS |
672 | interrupt-controller; |
673 | #interrupt-cells = <2>; | |
b976fd63 | 674 | reg = <0x0 0xff0a0000 0x0 0x1000>; |
0b33e0b1 | 675 | gpio-controller; |
8f4e3972 | 676 | power-domains = <&pd_gpio>; |
44303dfa MS |
677 | }; |
678 | ||
679 | i2c0: i2c@ff020000 { | |
de4914b4 | 680 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
44303dfa MS |
681 | status = "disabled"; |
682 | interrupt-parent = <&gic>; | |
683 | interrupts = <0 17 4>; | |
b976fd63 | 684 | reg = <0x0 0xff020000 0x0 0x1000>; |
44303dfa MS |
685 | #address-cells = <1>; |
686 | #size-cells = <0>; | |
8f4e3972 | 687 | power-domains = <&pd_i2c0>; |
44303dfa MS |
688 | }; |
689 | ||
690 | i2c1: i2c@ff030000 { | |
de4914b4 | 691 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
44303dfa MS |
692 | status = "disabled"; |
693 | interrupt-parent = <&gic>; | |
694 | interrupts = <0 18 4>; | |
b976fd63 | 695 | reg = <0x0 0xff030000 0x0 0x1000>; |
44303dfa MS |
696 | #address-cells = <1>; |
697 | #size-cells = <0>; | |
8f4e3972 | 698 | power-domains = <&pd_i2c1>; |
44303dfa MS |
699 | }; |
700 | ||
5534480a NSR |
701 | ocm: memory-controller@ff960000 { |
702 | compatible = "xlnx,zynqmp-ocmc-1.0"; | |
b976fd63 | 703 | reg = <0x0 0xff960000 0x0 0x1000>; |
5534480a NSR |
704 | interrupt-parent = <&gic>; |
705 | interrupts = <0 10 4>; | |
706 | }; | |
707 | ||
44303dfa MS |
708 | pcie: pcie@fd0e0000 { |
709 | compatible = "xlnx,nwl-pcie-2.11"; | |
710 | status = "disabled"; | |
711 | #address-cells = <3>; | |
712 | #size-cells = <2>; | |
713 | #interrupt-cells = <1>; | |
7d6ca73a | 714 | msi-controller; |
44303dfa MS |
715 | device_type = "pci"; |
716 | interrupt-parent = <&gic>; | |
91a8b0ee | 717 | interrupts = <0 118 4>, |
7d6ca73a | 718 | <0 117 4>, |
91a8b0ee MS |
719 | <0 116 4>, |
720 | <0 115 4>, /* MSI_1 [63...32] */ | |
721 | <0 114 4>; /* MSI_0 [31...0] */ | |
7d6ca73a BKG |
722 | interrupt-names = "misc","dummy","intx", "msi1", "msi0"; |
723 | msi-parent = <&pcie>; | |
b976fd63 MS |
724 | reg = <0x0 0xfd0e0000 0x0 0x1000>, |
725 | <0x0 0xfd480000 0x0 0x1000>, | |
688d1be5 | 726 | <0x80 0x00000000 0x0 0x1000000>; |
44303dfa | 727 | reg-names = "breg", "pcireg", "cfg"; |
688d1be5 BKG |
728 | ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ |
729 | 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ | |
33aec517 BKG |
730 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
731 | interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, | |
732 | <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, | |
733 | <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, | |
734 | <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; | |
2af3932f | 735 | power-domains = <&pd_pcie>; |
33aec517 BKG |
736 | pcie_intc: legacy-interrupt-controller { |
737 | interrupt-controller; | |
738 | #address-cells = <0>; | |
739 | #interrupt-cells = <1>; | |
740 | }; | |
44303dfa MS |
741 | }; |
742 | ||
743 | qspi: spi@ff0f0000 { | |
744 | compatible = "xlnx,zynqmp-qspi-1.0"; | |
745 | status = "disabled"; | |
746 | clock-names = "ref_clk", "pclk"; | |
747 | interrupts = <0 15 4>; | |
748 | interrupt-parent = <&gic>; | |
749 | num-cs = <1>; | |
b976fd63 MS |
750 | reg = <0x0 0xff0f0000 0x0 0x1000>, |
751 | <0x0 0xc0000000 0x0 0x8000000>; | |
44303dfa MS |
752 | #address-cells = <1>; |
753 | #size-cells = <0>; | |
ba6ad317 MS |
754 | #stream-id-cells = <1>; |
755 | iommus = <&smmu 0x873>; | |
8f4e3972 | 756 | power-domains = <&pd_qspi>; |
44303dfa MS |
757 | }; |
758 | ||
759 | rtc: rtc@ffa60000 { | |
760 | compatible = "xlnx,zynqmp-rtc"; | |
761 | status = "disabled"; | |
b976fd63 | 762 | reg = <0x0 0xffa60000 0x0 0x100>; |
44303dfa MS |
763 | interrupt-parent = <&gic>; |
764 | interrupts = <0 26 4>, <0 27 4>; | |
765 | interrupt-names = "alarm", "sec"; | |
766 | }; | |
767 | ||
db6c62e1 AKV |
768 | serdes: zynqmp_phy@fd400000 { |
769 | compatible = "xlnx,zynqmp-psgtr"; | |
770 | status = "disabled"; | |
b976fd63 MS |
771 | reg = <0x0 0xfd400000 0x0 0x40000>, |
772 | <0x0 0xfd3d0000 0x0 0x1000>, | |
773 | <0x0 0xfd1a0000 0x0 0x1000>, | |
774 | <0x0 0xff5e0000 0x0 0x1000>; | |
db6c62e1 AKV |
775 | reg-names = "serdes", "siou", "fpd", "lpd"; |
776 | xlnx,tx_termination_fix; | |
777 | lane0: lane0 { | |
778 | #phy-cells = <4>; | |
779 | }; | |
780 | lane1: lane1 { | |
781 | #phy-cells = <4>; | |
782 | }; | |
783 | lane2: lane2 { | |
784 | #phy-cells = <4>; | |
785 | }; | |
786 | lane3: lane3 { | |
787 | #phy-cells = <4>; | |
788 | }; | |
789 | }; | |
790 | ||
44303dfa MS |
791 | sata: ahci@fd0c0000 { |
792 | compatible = "ceva,ahci-1v84"; | |
793 | status = "disabled"; | |
b976fd63 | 794 | reg = <0x0 0xfd0c0000 0x0 0x2000>; |
44303dfa MS |
795 | interrupt-parent = <&gic>; |
796 | interrupts = <0 133 4>; | |
8f4e3972 | 797 | power-domains = <&pd_sata>; |
44303dfa MS |
798 | }; |
799 | ||
800 | sdhci0: sdhci@ff160000 { | |
c9811e14 | 801 | u-boot,dm-pre-reloc; |
0488a5e1 | 802 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
44303dfa MS |
803 | status = "disabled"; |
804 | interrupt-parent = <&gic>; | |
805 | interrupts = <0 48 4>; | |
b976fd63 | 806 | reg = <0x0 0xff160000 0x0 0x1000>; |
44303dfa | 807 | clock-names = "clk_xin", "clk_ahb"; |
0488a5e1 | 808 | xlnx,device_id = <0>; |
ba6ad317 MS |
809 | #stream-id-cells = <1>; |
810 | iommus = <&smmu 0x870>; | |
8f4e3972 | 811 | power-domains = <&pd_sd0>; |
44303dfa MS |
812 | }; |
813 | ||
814 | sdhci1: sdhci@ff170000 { | |
c9811e14 | 815 | u-boot,dm-pre-reloc; |
0488a5e1 | 816 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
44303dfa MS |
817 | status = "disabled"; |
818 | interrupt-parent = <&gic>; | |
819 | interrupts = <0 49 4>; | |
b976fd63 | 820 | reg = <0x0 0xff170000 0x0 0x1000>; |
44303dfa | 821 | clock-names = "clk_xin", "clk_ahb"; |
0488a5e1 | 822 | xlnx,device_id = <1>; |
ba6ad317 MS |
823 | #stream-id-cells = <1>; |
824 | iommus = <&smmu 0x871>; | |
8f4e3972 | 825 | power-domains = <&pd_sd1>; |
44303dfa MS |
826 | }; |
827 | ||
828 | smmu: smmu@fd800000 { | |
829 | compatible = "arm,mmu-500"; | |
b976fd63 | 830 | reg = <0x0 0xfd800000 0x0 0x20000>; |
ba6ad317 | 831 | #iommu-cells = <1>; |
44303dfa MS |
832 | #global-interrupts = <1>; |
833 | interrupt-parent = <&gic>; | |
88a85aac EI |
834 | interrupts = <0 155 4>, |
835 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
836 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
837 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
838 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; | |
7f1d7d97 EI |
839 | mmu-masters = < &gem0 0x874 |
840 | &gem1 0x875 | |
841 | &gem2 0x876 | |
ba6ad317 MS |
842 | &gem3 0x877 |
843 | &usb0 0x860 | |
844 | &usb1 0x861 | |
845 | &qspi 0x873 | |
846 | &lpd_dma_chan1 0x868 | |
847 | &lpd_dma_chan2 0x869 | |
848 | &lpd_dma_chan3 0x86a | |
849 | &lpd_dma_chan4 0x86b | |
850 | &lpd_dma_chan5 0x86c | |
851 | &lpd_dma_chan6 0x86d | |
852 | &lpd_dma_chan7 0x86e | |
853 | &lpd_dma_chan8 0x86f | |
854 | &fpd_dma_chan1 0x14e8 | |
855 | &fpd_dma_chan2 0x14e9 | |
856 | &fpd_dma_chan3 0x14ea | |
857 | &fpd_dma_chan4 0x14eb | |
858 | &fpd_dma_chan5 0x14ec | |
859 | &fpd_dma_chan6 0x14ed | |
860 | &fpd_dma_chan7 0x14ee | |
861 | &fpd_dma_chan8 0x14ef | |
862 | &sdhci0 0x870 | |
863 | &sdhci1 0x871 | |
864 | &nand0 0x872>; | |
44303dfa MS |
865 | }; |
866 | ||
867 | spi0: spi@ff040000 { | |
868 | compatible = "cdns,spi-r1p6"; | |
869 | status = "disabled"; | |
870 | interrupt-parent = <&gic>; | |
871 | interrupts = <0 19 4>; | |
b976fd63 | 872 | reg = <0x0 0xff040000 0x0 0x1000>; |
44303dfa MS |
873 | clock-names = "ref_clk", "pclk"; |
874 | #address-cells = <1>; | |
875 | #size-cells = <0>; | |
8f4e3972 | 876 | power-domains = <&pd_spi0>; |
44303dfa MS |
877 | }; |
878 | ||
879 | spi1: spi@ff050000 { | |
880 | compatible = "cdns,spi-r1p6"; | |
881 | status = "disabled"; | |
882 | interrupt-parent = <&gic>; | |
883 | interrupts = <0 20 4>; | |
b976fd63 | 884 | reg = <0x0 0xff050000 0x0 0x1000>; |
44303dfa MS |
885 | clock-names = "ref_clk", "pclk"; |
886 | #address-cells = <1>; | |
887 | #size-cells = <0>; | |
8f4e3972 | 888 | power-domains = <&pd_spi1>; |
44303dfa MS |
889 | }; |
890 | ||
891 | ttc0: timer@ff110000 { | |
892 | compatible = "cdns,ttc"; | |
893 | status = "disabled"; | |
894 | interrupt-parent = <&gic>; | |
895 | interrupts = <0 36 4>, <0 37 4>, <0 38 4>; | |
b976fd63 | 896 | reg = <0x0 0xff110000 0x0 0x1000>; |
44303dfa | 897 | timer-width = <32>; |
8f4e3972 | 898 | power-domains = <&pd_ttc0>; |
44303dfa MS |
899 | }; |
900 | ||
901 | ttc1: timer@ff120000 { | |
902 | compatible = "cdns,ttc"; | |
903 | status = "disabled"; | |
904 | interrupt-parent = <&gic>; | |
905 | interrupts = <0 39 4>, <0 40 4>, <0 41 4>; | |
b976fd63 | 906 | reg = <0x0 0xff120000 0x0 0x1000>; |
44303dfa | 907 | timer-width = <32>; |
8f4e3972 | 908 | power-domains = <&pd_ttc1>; |
44303dfa MS |
909 | }; |
910 | ||
911 | ttc2: timer@ff130000 { | |
912 | compatible = "cdns,ttc"; | |
913 | status = "disabled"; | |
914 | interrupt-parent = <&gic>; | |
915 | interrupts = <0 42 4>, <0 43 4>, <0 44 4>; | |
b976fd63 | 916 | reg = <0x0 0xff130000 0x0 0x1000>; |
44303dfa | 917 | timer-width = <32>; |
8f4e3972 | 918 | power-domains = <&pd_ttc2>; |
44303dfa MS |
919 | }; |
920 | ||
921 | ttc3: timer@ff140000 { | |
922 | compatible = "cdns,ttc"; | |
923 | status = "disabled"; | |
924 | interrupt-parent = <&gic>; | |
925 | interrupts = <0 45 4>, <0 46 4>, <0 47 4>; | |
b976fd63 | 926 | reg = <0x0 0xff140000 0x0 0x1000>; |
44303dfa | 927 | timer-width = <32>; |
8f4e3972 | 928 | power-domains = <&pd_ttc3>; |
44303dfa MS |
929 | }; |
930 | ||
931 | uart0: serial@ff000000 { | |
c9811e14 | 932 | u-boot,dm-pre-reloc; |
ca2f5878 | 933 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
44303dfa MS |
934 | status = "disabled"; |
935 | interrupt-parent = <&gic>; | |
936 | interrupts = <0 21 4>; | |
b976fd63 | 937 | reg = <0x0 0xff000000 0x0 0x1000>; |
44303dfa | 938 | clock-names = "uart_clk", "pclk"; |
8f4e3972 | 939 | power-domains = <&pd_uart0>; |
44303dfa MS |
940 | }; |
941 | ||
942 | uart1: serial@ff010000 { | |
c9811e14 | 943 | u-boot,dm-pre-reloc; |
ca2f5878 | 944 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
44303dfa MS |
945 | status = "disabled"; |
946 | interrupt-parent = <&gic>; | |
947 | interrupts = <0 22 4>; | |
b976fd63 | 948 | reg = <0x0 0xff010000 0x0 0x1000>; |
44303dfa | 949 | clock-names = "uart_clk", "pclk"; |
8f4e3972 | 950 | power-domains = <&pd_uart1>; |
44303dfa MS |
951 | }; |
952 | ||
c926e6fb | 953 | usb0: usb0 { |
a84de48e | 954 | #address-cells = <2>; |
b976fd63 | 955 | #size-cells = <2>; |
44303dfa | 956 | status = "disabled"; |
a84de48e MS |
957 | compatible = "xlnx,zynqmp-dwc3"; |
958 | clock-names = "bus_clk", "ref_clk"; | |
959 | clocks = <&clk125>, <&clk125>; | |
ba6ad317 MS |
960 | #stream-id-cells = <1>; |
961 | iommus = <&smmu 0x860>; | |
8f4e3972 | 962 | power-domains = <&pd_usb0>; |
a84de48e MS |
963 | ranges; |
964 | ||
965 | dwc3_0: dwc3@fe200000 { | |
966 | compatible = "snps,dwc3"; | |
967 | status = "disabled"; | |
b976fd63 | 968 | reg = <0x0 0xfe200000 0x0 0x40000>; |
a84de48e MS |
969 | interrupt-parent = <&gic>; |
970 | interrupts = <0 65 4>; | |
971 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
972 | snps,refclk_fladj; | |
973 | }; | |
44303dfa MS |
974 | }; |
975 | ||
c926e6fb | 976 | usb1: usb1 { |
a84de48e | 977 | #address-cells = <2>; |
b976fd63 | 978 | #size-cells = <2>; |
44303dfa | 979 | status = "disabled"; |
a84de48e MS |
980 | compatible = "xlnx,zynqmp-dwc3"; |
981 | clock-names = "bus_clk", "ref_clk"; | |
982 | clocks = <&clk125>, <&clk125>; | |
ba6ad317 MS |
983 | #stream-id-cells = <1>; |
984 | iommus = <&smmu 0x861>; | |
8f4e3972 | 985 | power-domains = <&pd_usb1>; |
a84de48e MS |
986 | ranges; |
987 | ||
988 | dwc3_1: dwc3@fe300000 { | |
989 | compatible = "snps,dwc3"; | |
990 | status = "disabled"; | |
b976fd63 | 991 | reg = <0x0 0xfe300000 0x0 0x40000>; |
a84de48e MS |
992 | interrupt-parent = <&gic>; |
993 | interrupts = <0 70 4>; | |
994 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
995 | snps,refclk_fladj; | |
996 | }; | |
44303dfa MS |
997 | }; |
998 | ||
999 | watchdog0: watchdog@fd4d0000 { | |
1000 | compatible = "cdns,wdt-r1p2"; | |
1001 | status = "disabled"; | |
1002 | interrupt-parent = <&gic>; | |
d3fd433f | 1003 | interrupts = <0 113 1>; |
b976fd63 | 1004 | reg = <0x0 0xfd4d0000 0x0 0x1000>; |
44303dfa MS |
1005 | timeout-sec = <10>; |
1006 | }; | |
1007 | ||
1008 | xilinx_drm: xilinx_drm { | |
1009 | compatible = "xlnx,drm"; | |
1010 | status = "disabled"; | |
1011 | xlnx,encoder-slave = <&xlnx_dp>; | |
1012 | xlnx,connector-type = "DisplayPort"; | |
1013 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
1014 | planes { | |
1015 | xlnx,pixel-format = "rgb565"; | |
1016 | plane0 { | |
1017 | dmas = <&xlnx_dpdma 3>; | |
bfe27980 | 1018 | dma-names = "dma0"; |
44303dfa MS |
1019 | }; |
1020 | plane1 { | |
bfe27980 HK |
1021 | dmas = <&xlnx_dpdma 0>, |
1022 | <&xlnx_dpdma 1>, | |
1023 | <&xlnx_dpdma 2>; | |
1024 | dma-names = "dma0", "dma1", "dma2"; | |
44303dfa MS |
1025 | }; |
1026 | }; | |
1027 | }; | |
1028 | ||
695d75a1 | 1029 | xlnx_dp: dp@fd4a0000 { |
44303dfa MS |
1030 | compatible = "xlnx,v-dp"; |
1031 | status = "disabled"; | |
b976fd63 | 1032 | reg = <0x0 0xfd4a0000 0x0 0x1000>; |
44303dfa MS |
1033 | interrupts = <0 119 4>; |
1034 | interrupt-parent = <&gic>; | |
1035 | clock-names = "aclk", "aud_clk"; | |
1036 | xlnx,dp-version = "v1.2"; | |
1037 | xlnx,max-lanes = <2>; | |
1038 | xlnx,max-link-rate = <540000>; | |
1039 | xlnx,max-bpc = <16>; | |
1040 | xlnx,enable-ycrcb; | |
1041 | xlnx,colormetry = "rgb"; | |
1042 | xlnx,bpc = <8>; | |
1043 | xlnx,audio-chan = <2>; | |
1044 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
939cfeaf | 1045 | xlnx,max-pclock-frequency = <300000>; |
44303dfa MS |
1046 | }; |
1047 | ||
1048 | xlnx_dp_snd_card: dp_snd_card { | |
1049 | compatible = "xlnx,dp-snd-card"; | |
1050 | status = "disabled"; | |
1051 | xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; | |
1052 | xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; | |
1053 | }; | |
1054 | ||
1055 | xlnx_dp_snd_codec0: dp_snd_codec0 { | |
1056 | compatible = "xlnx,dp-snd-codec"; | |
1057 | status = "disabled"; | |
1058 | clock-names = "aud_clk"; | |
1059 | }; | |
1060 | ||
1061 | xlnx_dp_snd_pcm0: dp_snd_pcm0 { | |
1062 | compatible = "xlnx,dp-snd-pcm"; | |
1063 | status = "disabled"; | |
1064 | dmas = <&xlnx_dpdma 4>; | |
1065 | dma-names = "tx"; | |
1066 | }; | |
1067 | ||
1068 | xlnx_dp_snd_pcm1: dp_snd_pcm1 { | |
1069 | compatible = "xlnx,dp-snd-pcm"; | |
1070 | status = "disabled"; | |
1071 | dmas = <&xlnx_dpdma 5>; | |
1072 | dma-names = "tx"; | |
1073 | }; | |
1074 | ||
695d75a1 | 1075 | xlnx_dp_sub: dp_sub@fd4aa000 { |
44303dfa MS |
1076 | compatible = "xlnx,dp-sub"; |
1077 | status = "disabled"; | |
b976fd63 MS |
1078 | reg = <0x0 0xfd4aa000 0x0 0x1000>, |
1079 | <0x0 0xfd4ab000 0x0 0x1000>, | |
1080 | <0x0 0xfd4ac000 0x0 0x1000>; | |
44303dfa MS |
1081 | reg-names = "blend", "av_buf", "aud"; |
1082 | xlnx,output-fmt = "rgb"; | |
939cfeaf HK |
1083 | xlnx,vid-fmt = "yuyv"; |
1084 | xlnx,gfx-fmt = "rgb565"; | |
44303dfa MS |
1085 | }; |
1086 | ||
1087 | xlnx_dpdma: dma@fd4c0000 { | |
1088 | compatible = "xlnx,dpdma"; | |
1089 | status = "disabled"; | |
b976fd63 | 1090 | reg = <0x0 0xfd4c0000 0x0 0x1000>; |
44303dfa MS |
1091 | interrupts = <0 122 4>; |
1092 | interrupt-parent = <&gic>; | |
1093 | clock-names = "axi_clk"; | |
1094 | dma-channels = <6>; | |
1095 | #dma-cells = <1>; | |
c926e6fb | 1096 | dma-video0channel { |
44303dfa MS |
1097 | compatible = "xlnx,video0"; |
1098 | }; | |
c926e6fb | 1099 | dma-video1channel { |
44303dfa MS |
1100 | compatible = "xlnx,video1"; |
1101 | }; | |
c926e6fb | 1102 | dma-video2channel { |
44303dfa MS |
1103 | compatible = "xlnx,video2"; |
1104 | }; | |
c926e6fb | 1105 | dma-graphicschannel { |
44303dfa MS |
1106 | compatible = "xlnx,graphics"; |
1107 | }; | |
c926e6fb | 1108 | dma-audio0channel { |
44303dfa MS |
1109 | compatible = "xlnx,audio0"; |
1110 | }; | |
c926e6fb | 1111 | dma-audio1channel { |
44303dfa MS |
1112 | compatible = "xlnx,audio1"; |
1113 | }; | |
1114 | }; | |
1115 | }; | |
1116 | }; |