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44303dfa MS |
1 | /* |
2 | * dts file for Xilinx ZynqMP | |
3 | * | |
4 | * (C) Copyright 2014 - 2015, Xilinx, Inc. | |
5 | * | |
6 | * Michal Simek <michal.simek@xilinx.com> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
91d11536 | 10 | |
44303dfa MS |
11 | / { |
12 | compatible = "xlnx,zynqmp"; | |
13 | #address-cells = <2>; | |
85d1142e | 14 | #size-cells = <2>; |
44303dfa MS |
15 | |
16 | cpus { | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
19 | ||
585ca873 | 20 | cpu0: cpu@0 { |
44303dfa MS |
21 | compatible = "arm,cortex-a53", "arm,armv8"; |
22 | device_type = "cpu"; | |
23 | enable-method = "psci"; | |
941f61fe | 24 | operating-points-v2 = <&cpu_opp_table>; |
44303dfa | 25 | reg = <0x0>; |
2e15b071 | 26 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
27 | }; |
28 | ||
585ca873 | 29 | cpu1: cpu@1 { |
44303dfa MS |
30 | compatible = "arm,cortex-a53", "arm,armv8"; |
31 | device_type = "cpu"; | |
32 | enable-method = "psci"; | |
33 | reg = <0x1>; | |
941f61fe | 34 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 | 35 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
36 | }; |
37 | ||
585ca873 | 38 | cpu2: cpu@2 { |
44303dfa MS |
39 | compatible = "arm,cortex-a53", "arm,armv8"; |
40 | device_type = "cpu"; | |
41 | enable-method = "psci"; | |
42 | reg = <0x2>; | |
941f61fe | 43 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 | 44 | cpu-idle-states = <&CPU_SLEEP_0>; |
44303dfa MS |
45 | }; |
46 | ||
585ca873 | 47 | cpu3: cpu@3 { |
44303dfa MS |
48 | compatible = "arm,cortex-a53", "arm,armv8"; |
49 | device_type = "cpu"; | |
50 | enable-method = "psci"; | |
51 | reg = <0x3>; | |
941f61fe | 52 | operating-points-v2 = <&cpu_opp_table>; |
2e15b071 SK |
53 | cpu-idle-states = <&CPU_SLEEP_0>; |
54 | }; | |
55 | ||
56 | idle-states { | |
fec54739 | 57 | entry-method = "arm,psci"; |
2e15b071 SK |
58 | |
59 | CPU_SLEEP_0: cpu-sleep-0 { | |
60 | compatible = "arm,idle-state"; | |
61 | arm,psci-suspend-param = <0x40000000>; | |
62 | local-timer-stop; | |
63 | entry-latency-us = <300>; | |
64 | exit-latency-us = <600>; | |
6a097b0d | 65 | min-residency-us = <10000>; |
2e15b071 | 66 | }; |
44303dfa MS |
67 | }; |
68 | }; | |
69 | ||
941f61fe SD |
70 | cpu_opp_table: cpu_opp_table { |
71 | compatible = "operating-points-v2"; | |
72 | opp-shared; | |
73 | opp00 { | |
74 | opp-hz = /bits/ 64 <1199999988>; | |
75 | opp-microvolt = <1000000>; | |
76 | clock-latency-ns = <500000>; | |
77 | }; | |
78 | opp01 { | |
79 | opp-hz = /bits/ 64 <599999994>; | |
80 | opp-microvolt = <1000000>; | |
81 | clock-latency-ns = <500000>; | |
82 | }; | |
83 | opp02 { | |
84 | opp-hz = /bits/ 64 <399999996>; | |
85 | opp-microvolt = <1000000>; | |
86 | clock-latency-ns = <500000>; | |
87 | }; | |
88 | opp03 { | |
89 | opp-hz = /bits/ 64 <299999997>; | |
90 | opp-microvolt = <1000000>; | |
91 | clock-latency-ns = <500000>; | |
92 | }; | |
93 | }; | |
94 | ||
69d09dd7 MS |
95 | dcc: dcc { |
96 | compatible = "arm,dcc"; | |
97 | status = "disabled"; | |
98 | u-boot,dm-pre-reloc; | |
99 | }; | |
100 | ||
8f4e3972 SB |
101 | power-domains { |
102 | compatible = "xlnx,zynqmp-genpd"; | |
103 | ||
104 | pd_usb0: pd-usb0 { | |
105 | #power-domain-cells = <0x0>; | |
106 | pd-id = <0x16>; | |
107 | }; | |
108 | ||
109 | pd_usb1: pd-usb1 { | |
110 | #power-domain-cells = <0x0>; | |
111 | pd-id = <0x17>; | |
112 | }; | |
113 | ||
114 | pd_sata: pd-sata { | |
115 | #power-domain-cells = <0x0>; | |
116 | pd-id = <0x1c>; | |
117 | }; | |
118 | ||
119 | pd_spi0: pd-spi0 { | |
120 | #power-domain-cells = <0x0>; | |
121 | pd-id = <0x23>; | |
122 | }; | |
123 | ||
124 | pd_spi1: pd-spi1 { | |
125 | #power-domain-cells = <0x0>; | |
126 | pd-id = <0x24>; | |
127 | }; | |
128 | ||
129 | pd_uart0: pd-uart0 { | |
130 | #power-domain-cells = <0x0>; | |
131 | pd-id = <0x21>; | |
132 | }; | |
133 | ||
134 | pd_uart1: pd-uart1 { | |
135 | #power-domain-cells = <0x0>; | |
136 | pd-id = <0x22>; | |
137 | }; | |
138 | ||
139 | pd_eth0: pd-eth0 { | |
140 | #power-domain-cells = <0x0>; | |
141 | pd-id = <0x1d>; | |
142 | }; | |
143 | ||
144 | pd_eth1: pd-eth1 { | |
145 | #power-domain-cells = <0x0>; | |
146 | pd-id = <0x1e>; | |
147 | }; | |
148 | ||
149 | pd_eth2: pd-eth2 { | |
150 | #power-domain-cells = <0x0>; | |
151 | pd-id = <0x1f>; | |
152 | }; | |
153 | ||
154 | pd_eth3: pd-eth3 { | |
155 | #power-domain-cells = <0x0>; | |
156 | pd-id = <0x20>; | |
157 | }; | |
158 | ||
159 | pd_i2c0: pd-i2c0 { | |
160 | #power-domain-cells = <0x0>; | |
161 | pd-id = <0x25>; | |
162 | }; | |
163 | ||
164 | pd_i2c1: pd-i2c1 { | |
165 | #power-domain-cells = <0x0>; | |
166 | pd-id = <0x26>; | |
167 | }; | |
168 | ||
169 | pd_dp: pd-dp { | |
170 | /* fixme: what to attach to */ | |
171 | #power-domain-cells = <0x0>; | |
172 | pd-id = <0x29>; | |
173 | }; | |
174 | ||
175 | pd_gdma: pd-gdma { | |
176 | #power-domain-cells = <0x0>; | |
177 | pd-id = <0x2a>; | |
178 | }; | |
179 | ||
180 | pd_adma: pd-adma { | |
181 | #power-domain-cells = <0x0>; | |
182 | pd-id = <0x2b>; | |
183 | }; | |
184 | ||
185 | pd_ttc0: pd-ttc0 { | |
186 | #power-domain-cells = <0x0>; | |
187 | pd-id = <0x18>; | |
188 | }; | |
189 | ||
190 | pd_ttc1: pd-ttc1 { | |
191 | #power-domain-cells = <0x0>; | |
192 | pd-id = <0x19>; | |
193 | }; | |
194 | ||
195 | pd_ttc2: pd-ttc2 { | |
196 | #power-domain-cells = <0x0>; | |
197 | pd-id = <0x1a>; | |
198 | }; | |
199 | ||
200 | pd_ttc3: pd-ttc3 { | |
201 | #power-domain-cells = <0x0>; | |
202 | pd-id = <0x1b>; | |
203 | }; | |
204 | ||
205 | pd_sd0: pd-sd0 { | |
206 | #power-domain-cells = <0x0>; | |
207 | pd-id = <0x27>; | |
208 | }; | |
209 | ||
210 | pd_sd1: pd-sd1 { | |
211 | #power-domain-cells = <0x0>; | |
212 | pd-id = <0x28>; | |
213 | }; | |
214 | ||
215 | pd_nand: pd-nand { | |
216 | #power-domain-cells = <0x0>; | |
217 | pd-id = <0x2c>; | |
218 | }; | |
219 | ||
220 | pd_qspi: pd-qspi { | |
221 | #power-domain-cells = <0x0>; | |
222 | pd-id = <0x2d>; | |
223 | }; | |
224 | ||
225 | pd_gpio: pd-gpio { | |
226 | #power-domain-cells = <0x0>; | |
227 | pd-id = <0x2e>; | |
228 | }; | |
229 | ||
230 | pd_can0: pd-can0 { | |
231 | #power-domain-cells = <0x0>; | |
232 | pd-id = <0x2f>; | |
233 | }; | |
234 | ||
235 | pd_can1: pd-can1 { | |
236 | #power-domain-cells = <0x0>; | |
237 | pd-id = <0x30>; | |
238 | }; | |
2af3932f FD |
239 | |
240 | pd_pcie: pd-pcie { | |
241 | #power-domain-cells = <0x0>; | |
242 | pd-id = <0x3b>; | |
243 | }; | |
244 | ||
245 | pd_gpu: pd-gpu { | |
246 | #power-domain-cells = <0x0>; | |
a4d7d560 | 247 | pd-id = <0x3a 0x14 0x15>; |
2af3932f | 248 | }; |
8f4e3972 SB |
249 | }; |
250 | ||
44303dfa MS |
251 | pmu { |
252 | compatible = "arm,armv8-pmuv3"; | |
14cd9eab | 253 | interrupt-parent = <&gic>; |
44303dfa MS |
254 | interrupts = <0 143 4>, |
255 | <0 144 4>, | |
256 | <0 145 4>, | |
257 | <0 146 4>; | |
258 | }; | |
259 | ||
260 | psci { | |
261 | compatible = "arm,psci-0.2"; | |
262 | method = "smc"; | |
263 | }; | |
264 | ||
265 | firmware { | |
266 | compatible = "xlnx,zynqmp-pm"; | |
267 | method = "smc"; | |
19ee402d SB |
268 | interrupt-parent = <&gic>; |
269 | interrupts = <0 35 4>; | |
44303dfa MS |
270 | }; |
271 | ||
272 | timer { | |
273 | compatible = "arm,armv8-timer"; | |
274 | interrupt-parent = <&gic>; | |
6db82e09 MS |
275 | interrupts = <1 13 0xf08>, |
276 | <1 14 0xf08>, | |
277 | <1 11 0xf08>, | |
278 | <1 10 0xf08>; | |
44303dfa MS |
279 | }; |
280 | ||
aaf232f3 NSR |
281 | edac { |
282 | compatible = "arm,cortex-a53-edac"; | |
283 | }; | |
284 | ||
d64e43f1 NM |
285 | pcap { |
286 | compatible = "xlnx,zynqmp-pcap-fpga"; | |
287 | }; | |
288 | ||
c926e6fb | 289 | amba_apu: amba_apu@0 { |
44303dfa MS |
290 | compatible = "simple-bus"; |
291 | #address-cells = <2>; | |
292 | #size-cells = <1>; | |
85d1142e | 293 | ranges = <0 0 0 0 0xffffffff>; |
44303dfa MS |
294 | |
295 | gic: interrupt-controller@f9010000 { | |
296 | compatible = "arm,gic-400", "arm,cortex-a15-gic"; | |
297 | #interrupt-cells = <3>; | |
298 | reg = <0x0 0xf9010000 0x10000>, | |
0a8c4f67 | 299 | <0x0 0xf9020000 0x20000>, |
44303dfa | 300 | <0x0 0xf9040000 0x20000>, |
0a8c4f67 | 301 | <0x0 0xf9060000 0x20000>; |
44303dfa MS |
302 | interrupt-controller; |
303 | interrupt-parent = <&gic>; | |
304 | interrupts = <1 9 0xf04>; | |
305 | }; | |
306 | }; | |
307 | ||
b976fd63 | 308 | amba: amba { |
44303dfa | 309 | compatible = "simple-bus"; |
c9811e14 | 310 | u-boot,dm-pre-reloc; |
44303dfa | 311 | #address-cells = <2>; |
b976fd63 MS |
312 | #size-cells = <2>; |
313 | ranges; | |
44303dfa MS |
314 | |
315 | can0: can@ff060000 { | |
316 | compatible = "xlnx,zynq-can-1.0"; | |
317 | status = "disabled"; | |
318 | clock-names = "can_clk", "pclk"; | |
b976fd63 | 319 | reg = <0x0 0xff060000 0x0 0x1000>; |
44303dfa MS |
320 | interrupts = <0 23 4>; |
321 | interrupt-parent = <&gic>; | |
322 | tx-fifo-depth = <0x40>; | |
323 | rx-fifo-depth = <0x40>; | |
8f4e3972 | 324 | power-domains = <&pd_can0>; |
44303dfa MS |
325 | }; |
326 | ||
327 | can1: can@ff070000 { | |
328 | compatible = "xlnx,zynq-can-1.0"; | |
329 | status = "disabled"; | |
330 | clock-names = "can_clk", "pclk"; | |
b976fd63 | 331 | reg = <0x0 0xff070000 0x0 0x1000>; |
44303dfa MS |
332 | interrupts = <0 24 4>; |
333 | interrupt-parent = <&gic>; | |
334 | tx-fifo-depth = <0x40>; | |
335 | rx-fifo-depth = <0x40>; | |
8f4e3972 | 336 | power-domains = <&pd_can1>; |
44303dfa MS |
337 | }; |
338 | ||
ff50d21b MS |
339 | cci: cci@fd6e0000 { |
340 | compatible = "arm,cci-400"; | |
b976fd63 | 341 | reg = <0x0 0xfd6e0000 0x0 0x9000>; |
ff50d21b MS |
342 | ranges = <0x0 0x0 0xfd6e0000 0x10000>; |
343 | #address-cells = <1>; | |
344 | #size-cells = <1>; | |
345 | ||
346 | pmu@9000 { | |
347 | compatible = "arm,cci-400-pmu,r1"; | |
348 | reg = <0x9000 0x5000>; | |
349 | interrupt-parent = <&gic>; | |
350 | interrupts = <0 123 4>, | |
351 | <0 123 4>, | |
352 | <0 123 4>, | |
353 | <0 123 4>, | |
354 | <0 123 4>; | |
355 | }; | |
356 | }; | |
357 | ||
44303dfa MS |
358 | /* GDMA */ |
359 | fpd_dma_chan1: dma@fd500000 { | |
360 | status = "disabled"; | |
361 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 362 | reg = <0x0 0xfd500000 0x0 0x1000>; |
44303dfa MS |
363 | interrupt-parent = <&gic>; |
364 | interrupts = <0 124 4>; | |
b34d11de | 365 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 366 | xlnx,bus-width = <128>; |
ba6ad317 MS |
367 | #stream-id-cells = <1>; |
368 | iommus = <&smmu 0x14e8>; | |
8f4e3972 | 369 | power-domains = <&pd_gdma>; |
44303dfa MS |
370 | }; |
371 | ||
372 | fpd_dma_chan2: dma@fd510000 { | |
373 | status = "disabled"; | |
374 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 375 | reg = <0x0 0xfd510000 0x0 0x1000>; |
44303dfa MS |
376 | interrupt-parent = <&gic>; |
377 | interrupts = <0 125 4>; | |
b34d11de | 378 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 379 | xlnx,bus-width = <128>; |
ba6ad317 MS |
380 | #stream-id-cells = <1>; |
381 | iommus = <&smmu 0x14e9>; | |
8f4e3972 | 382 | power-domains = <&pd_gdma>; |
44303dfa MS |
383 | }; |
384 | ||
385 | fpd_dma_chan3: dma@fd520000 { | |
386 | status = "disabled"; | |
387 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 388 | reg = <0x0 0xfd520000 0x0 0x1000>; |
44303dfa MS |
389 | interrupt-parent = <&gic>; |
390 | interrupts = <0 126 4>; | |
b34d11de | 391 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 392 | xlnx,bus-width = <128>; |
ba6ad317 MS |
393 | #stream-id-cells = <1>; |
394 | iommus = <&smmu 0x14ea>; | |
8f4e3972 | 395 | power-domains = <&pd_gdma>; |
44303dfa MS |
396 | }; |
397 | ||
398 | fpd_dma_chan4: dma@fd530000 { | |
399 | status = "disabled"; | |
400 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 401 | reg = <0x0 0xfd530000 0x0 0x1000>; |
44303dfa MS |
402 | interrupt-parent = <&gic>; |
403 | interrupts = <0 127 4>; | |
b34d11de | 404 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 405 | xlnx,bus-width = <128>; |
ba6ad317 MS |
406 | #stream-id-cells = <1>; |
407 | iommus = <&smmu 0x14eb>; | |
8f4e3972 | 408 | power-domains = <&pd_gdma>; |
44303dfa MS |
409 | }; |
410 | ||
411 | fpd_dma_chan5: dma@fd540000 { | |
412 | status = "disabled"; | |
413 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 414 | reg = <0x0 0xfd540000 0x0 0x1000>; |
44303dfa MS |
415 | interrupt-parent = <&gic>; |
416 | interrupts = <0 128 4>; | |
b34d11de | 417 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 418 | xlnx,bus-width = <128>; |
ba6ad317 MS |
419 | #stream-id-cells = <1>; |
420 | iommus = <&smmu 0x14ec>; | |
8f4e3972 | 421 | power-domains = <&pd_gdma>; |
44303dfa MS |
422 | }; |
423 | ||
424 | fpd_dma_chan6: dma@fd550000 { | |
425 | status = "disabled"; | |
426 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 427 | reg = <0x0 0xfd550000 0x0 0x1000>; |
44303dfa MS |
428 | interrupt-parent = <&gic>; |
429 | interrupts = <0 129 4>; | |
b34d11de | 430 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 431 | xlnx,bus-width = <128>; |
ba6ad317 MS |
432 | #stream-id-cells = <1>; |
433 | iommus = <&smmu 0x14ed>; | |
8f4e3972 | 434 | power-domains = <&pd_gdma>; |
44303dfa MS |
435 | }; |
436 | ||
437 | fpd_dma_chan7: dma@fd560000 { | |
438 | status = "disabled"; | |
439 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 440 | reg = <0x0 0xfd560000 0x0 0x1000>; |
44303dfa MS |
441 | interrupt-parent = <&gic>; |
442 | interrupts = <0 130 4>; | |
b34d11de | 443 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 444 | xlnx,bus-width = <128>; |
ba6ad317 MS |
445 | #stream-id-cells = <1>; |
446 | iommus = <&smmu 0x14ee>; | |
8f4e3972 | 447 | power-domains = <&pd_gdma>; |
44303dfa MS |
448 | }; |
449 | ||
450 | fpd_dma_chan8: dma@fd570000 { | |
451 | status = "disabled"; | |
452 | compatible = "xlnx,zynqmp-dma-1.0"; | |
b976fd63 | 453 | reg = <0x0 0xfd570000 0x0 0x1000>; |
44303dfa MS |
454 | interrupt-parent = <&gic>; |
455 | interrupts = <0 131 4>; | |
b34d11de | 456 | clock-names = "clk_main", "clk_apb"; |
44303dfa | 457 | xlnx,bus-width = <128>; |
ba6ad317 MS |
458 | #stream-id-cells = <1>; |
459 | iommus = <&smmu 0x14ef>; | |
8f4e3972 | 460 | power-domains = <&pd_gdma>; |
44303dfa MS |
461 | }; |
462 | ||
463 | gpu: gpu@fd4b0000 { | |
464 | status = "disabled"; | |
465 | compatible = "arm,mali-400", "arm,mali-utgard"; | |
b976fd63 | 466 | reg = <0x0 0xfd4b0000 0x0 0x30000>; |
44303dfa MS |
467 | interrupt-parent = <&gic>; |
468 | interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; | |
469 | interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; | |
2af3932f | 470 | power-domains = <&pd_gpu>; |
44303dfa MS |
471 | }; |
472 | ||
6af57737 KA |
473 | /* LPDDMA default allows only secured access. inorder to enable |
474 | * These dma channels, Users should ensure that these dma | |
475 | * Channels are allowed for non secure access. | |
476 | */ | |
44303dfa MS |
477 | lpd_dma_chan1: dma@ffa80000 { |
478 | status = "disabled"; | |
479 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 480 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 481 | reg = <0x0 0xffa80000 0x0 0x1000>; |
44303dfa MS |
482 | interrupt-parent = <&gic>; |
483 | interrupts = <0 77 4>; | |
44303dfa | 484 | xlnx,bus-width = <64>; |
ba6ad317 MS |
485 | #stream-id-cells = <1>; |
486 | iommus = <&smmu 0x868>; | |
8f4e3972 | 487 | power-domains = <&pd_adma>; |
44303dfa MS |
488 | }; |
489 | ||
490 | lpd_dma_chan2: dma@ffa90000 { | |
491 | status = "disabled"; | |
492 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 493 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 494 | reg = <0x0 0xffa90000 0x0 0x1000>; |
44303dfa MS |
495 | interrupt-parent = <&gic>; |
496 | interrupts = <0 78 4>; | |
44303dfa | 497 | xlnx,bus-width = <64>; |
ba6ad317 MS |
498 | #stream-id-cells = <1>; |
499 | iommus = <&smmu 0x869>; | |
8f4e3972 | 500 | power-domains = <&pd_adma>; |
44303dfa MS |
501 | }; |
502 | ||
503 | lpd_dma_chan3: dma@ffaa0000 { | |
504 | status = "disabled"; | |
505 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 506 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 507 | reg = <0x0 0xffaa0000 0x0 0x1000>; |
44303dfa MS |
508 | interrupt-parent = <&gic>; |
509 | interrupts = <0 79 4>; | |
44303dfa | 510 | xlnx,bus-width = <64>; |
ba6ad317 MS |
511 | #stream-id-cells = <1>; |
512 | iommus = <&smmu 0x86a>; | |
8f4e3972 | 513 | power-domains = <&pd_adma>; |
44303dfa MS |
514 | }; |
515 | ||
516 | lpd_dma_chan4: dma@ffab0000 { | |
517 | status = "disabled"; | |
518 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 519 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 520 | reg = <0x0 0xffab0000 0x0 0x1000>; |
44303dfa MS |
521 | interrupt-parent = <&gic>; |
522 | interrupts = <0 80 4>; | |
44303dfa | 523 | xlnx,bus-width = <64>; |
ba6ad317 MS |
524 | #stream-id-cells = <1>; |
525 | iommus = <&smmu 0x86b>; | |
8f4e3972 | 526 | power-domains = <&pd_adma>; |
44303dfa MS |
527 | }; |
528 | ||
529 | lpd_dma_chan5: dma@ffac0000 { | |
530 | status = "disabled"; | |
531 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 532 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 533 | reg = <0x0 0xffac0000 0x0 0x1000>; |
44303dfa MS |
534 | interrupt-parent = <&gic>; |
535 | interrupts = <0 81 4>; | |
44303dfa | 536 | xlnx,bus-width = <64>; |
ba6ad317 MS |
537 | #stream-id-cells = <1>; |
538 | iommus = <&smmu 0x86c>; | |
8f4e3972 | 539 | power-domains = <&pd_adma>; |
44303dfa MS |
540 | }; |
541 | ||
542 | lpd_dma_chan6: dma@ffad0000 { | |
543 | status = "disabled"; | |
544 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 545 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 546 | reg = <0x0 0xffad0000 0x0 0x1000>; |
44303dfa MS |
547 | interrupt-parent = <&gic>; |
548 | interrupts = <0 82 4>; | |
44303dfa | 549 | xlnx,bus-width = <64>; |
ba6ad317 MS |
550 | #stream-id-cells = <1>; |
551 | iommus = <&smmu 0x86d>; | |
8f4e3972 | 552 | power-domains = <&pd_adma>; |
44303dfa MS |
553 | }; |
554 | ||
555 | lpd_dma_chan7: dma@ffae0000 { | |
556 | status = "disabled"; | |
557 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 558 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 559 | reg = <0x0 0xffae0000 0x0 0x1000>; |
44303dfa MS |
560 | interrupt-parent = <&gic>; |
561 | interrupts = <0 83 4>; | |
44303dfa | 562 | xlnx,bus-width = <64>; |
ba6ad317 MS |
563 | #stream-id-cells = <1>; |
564 | iommus = <&smmu 0x86e>; | |
8f4e3972 | 565 | power-domains = <&pd_adma>; |
44303dfa MS |
566 | }; |
567 | ||
568 | lpd_dma_chan8: dma@ffaf0000 { | |
569 | status = "disabled"; | |
570 | compatible = "xlnx,zynqmp-dma-1.0"; | |
d33046aa | 571 | clock-names = "clk_main", "clk_apb"; |
b976fd63 | 572 | reg = <0x0 0xffaf0000 0x0 0x1000>; |
44303dfa MS |
573 | interrupt-parent = <&gic>; |
574 | interrupts = <0 84 4>; | |
44303dfa | 575 | xlnx,bus-width = <64>; |
ba6ad317 MS |
576 | #stream-id-cells = <1>; |
577 | iommus = <&smmu 0x86f>; | |
8f4e3972 | 578 | power-domains = <&pd_adma>; |
44303dfa MS |
579 | }; |
580 | ||
90869009 NSR |
581 | mc: memory-controller@fd070000 { |
582 | compatible = "xlnx,zynqmp-ddrc-2.40a"; | |
b976fd63 | 583 | reg = <0x0 0xfd070000 0x0 0x30000>; |
90869009 NSR |
584 | interrupt-parent = <&gic>; |
585 | interrupts = <0 112 4>; | |
586 | }; | |
587 | ||
44303dfa MS |
588 | nand0: nand@ff100000 { |
589 | compatible = "arasan,nfc-v3p10"; | |
590 | status = "disabled"; | |
b976fd63 | 591 | reg = <0x0 0xff100000 0x0 0x1000>; |
44303dfa MS |
592 | clock-names = "clk_sys", "clk_flash"; |
593 | interrupt-parent = <&gic>; | |
594 | interrupts = <0 14 4>; | |
595 | #address-cells = <2>; | |
596 | #size-cells = <1>; | |
ba6ad317 MS |
597 | #stream-id-cells = <1>; |
598 | iommus = <&smmu 0x872>; | |
8f4e3972 | 599 | power-domains = <&pd_nand>; |
44303dfa MS |
600 | }; |
601 | ||
602 | gem0: ethernet@ff0b0000 { | |
da2ad784 | 603 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
604 | status = "disabled"; |
605 | interrupt-parent = <&gic>; | |
606 | interrupts = <0 57 4>, <0 57 4>; | |
b976fd63 | 607 | reg = <0x0 0xff0b0000 0x0 0x1000>; |
44303dfa MS |
608 | clock-names = "pclk", "hclk", "tx_clk"; |
609 | #address-cells = <1>; | |
610 | #size-cells = <0>; | |
7f1d7d97 | 611 | #stream-id-cells = <1>; |
ba6ad317 | 612 | iommus = <&smmu 0x874>; |
8f4e3972 | 613 | power-domains = <&pd_eth0>; |
44303dfa MS |
614 | }; |
615 | ||
616 | gem1: ethernet@ff0c0000 { | |
da2ad784 | 617 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
618 | status = "disabled"; |
619 | interrupt-parent = <&gic>; | |
620 | interrupts = <0 59 4>, <0 59 4>; | |
b976fd63 | 621 | reg = <0x0 0xff0c0000 0x0 0x1000>; |
44303dfa MS |
622 | clock-names = "pclk", "hclk", "tx_clk"; |
623 | #address-cells = <1>; | |
624 | #size-cells = <0>; | |
7f1d7d97 | 625 | #stream-id-cells = <1>; |
ba6ad317 | 626 | iommus = <&smmu 0x875>; |
8f4e3972 | 627 | power-domains = <&pd_eth1>; |
44303dfa MS |
628 | }; |
629 | ||
630 | gem2: ethernet@ff0d0000 { | |
da2ad784 | 631 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
632 | status = "disabled"; |
633 | interrupt-parent = <&gic>; | |
634 | interrupts = <0 61 4>, <0 61 4>; | |
b976fd63 | 635 | reg = <0x0 0xff0d0000 0x0 0x1000>; |
44303dfa MS |
636 | clock-names = "pclk", "hclk", "tx_clk"; |
637 | #address-cells = <1>; | |
638 | #size-cells = <0>; | |
7f1d7d97 | 639 | #stream-id-cells = <1>; |
ba6ad317 | 640 | iommus = <&smmu 0x876>; |
8f4e3972 | 641 | power-domains = <&pd_eth2>; |
44303dfa MS |
642 | }; |
643 | ||
644 | gem3: ethernet@ff0e0000 { | |
da2ad784 | 645 | compatible = "cdns,zynqmp-gem"; |
44303dfa MS |
646 | status = "disabled"; |
647 | interrupt-parent = <&gic>; | |
648 | interrupts = <0 63 4>, <0 63 4>; | |
b976fd63 | 649 | reg = <0x0 0xff0e0000 0x0 0x1000>; |
44303dfa MS |
650 | clock-names = "pclk", "hclk", "tx_clk"; |
651 | #address-cells = <1>; | |
652 | #size-cells = <0>; | |
7f1d7d97 | 653 | #stream-id-cells = <1>; |
ba6ad317 | 654 | iommus = <&smmu 0x877>; |
8f4e3972 | 655 | power-domains = <&pd_eth3>; |
44303dfa MS |
656 | }; |
657 | ||
658 | gpio: gpio@ff0a0000 { | |
659 | compatible = "xlnx,zynqmp-gpio-1.0"; | |
660 | status = "disabled"; | |
661 | #gpio-cells = <0x2>; | |
662 | interrupt-parent = <&gic>; | |
663 | interrupts = <0 16 4>; | |
9e826b68 MS |
664 | interrupt-controller; |
665 | #interrupt-cells = <2>; | |
b976fd63 | 666 | reg = <0x0 0xff0a0000 0x0 0x1000>; |
8f4e3972 | 667 | power-domains = <&pd_gpio>; |
44303dfa MS |
668 | }; |
669 | ||
670 | i2c0: i2c@ff020000 { | |
de4914b4 | 671 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
44303dfa MS |
672 | status = "disabled"; |
673 | interrupt-parent = <&gic>; | |
674 | interrupts = <0 17 4>; | |
b976fd63 | 675 | reg = <0x0 0xff020000 0x0 0x1000>; |
44303dfa MS |
676 | #address-cells = <1>; |
677 | #size-cells = <0>; | |
8f4e3972 | 678 | power-domains = <&pd_i2c0>; |
44303dfa MS |
679 | }; |
680 | ||
681 | i2c1: i2c@ff030000 { | |
de4914b4 | 682 | compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; |
44303dfa MS |
683 | status = "disabled"; |
684 | interrupt-parent = <&gic>; | |
685 | interrupts = <0 18 4>; | |
b976fd63 | 686 | reg = <0x0 0xff030000 0x0 0x1000>; |
44303dfa MS |
687 | #address-cells = <1>; |
688 | #size-cells = <0>; | |
8f4e3972 | 689 | power-domains = <&pd_i2c1>; |
44303dfa MS |
690 | }; |
691 | ||
5534480a NSR |
692 | ocm: memory-controller@ff960000 { |
693 | compatible = "xlnx,zynqmp-ocmc-1.0"; | |
b976fd63 | 694 | reg = <0x0 0xff960000 0x0 0x1000>; |
5534480a NSR |
695 | interrupt-parent = <&gic>; |
696 | interrupts = <0 10 4>; | |
697 | }; | |
698 | ||
44303dfa MS |
699 | pcie: pcie@fd0e0000 { |
700 | compatible = "xlnx,nwl-pcie-2.11"; | |
701 | status = "disabled"; | |
702 | #address-cells = <3>; | |
703 | #size-cells = <2>; | |
704 | #interrupt-cells = <1>; | |
7d6ca73a | 705 | msi-controller; |
44303dfa MS |
706 | device_type = "pci"; |
707 | interrupt-parent = <&gic>; | |
91a8b0ee | 708 | interrupts = <0 118 4>, |
7d6ca73a | 709 | <0 117 4>, |
91a8b0ee MS |
710 | <0 116 4>, |
711 | <0 115 4>, /* MSI_1 [63...32] */ | |
712 | <0 114 4>; /* MSI_0 [31...0] */ | |
7d6ca73a BKG |
713 | interrupt-names = "misc","dummy","intx", "msi1", "msi0"; |
714 | msi-parent = <&pcie>; | |
b976fd63 MS |
715 | reg = <0x0 0xfd0e0000 0x0 0x1000>, |
716 | <0x0 0xfd480000 0x0 0x1000>, | |
688d1be5 | 717 | <0x80 0x00000000 0x0 0x1000000>; |
44303dfa | 718 | reg-names = "breg", "pcireg", "cfg"; |
688d1be5 BKG |
719 | ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ |
720 | 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ | |
33aec517 BKG |
721 | interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
722 | interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, | |
723 | <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, | |
724 | <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, | |
725 | <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; | |
2af3932f | 726 | power-domains = <&pd_pcie>; |
33aec517 BKG |
727 | pcie_intc: legacy-interrupt-controller { |
728 | interrupt-controller; | |
729 | #address-cells = <0>; | |
730 | #interrupt-cells = <1>; | |
731 | }; | |
44303dfa MS |
732 | }; |
733 | ||
734 | qspi: spi@ff0f0000 { | |
735 | compatible = "xlnx,zynqmp-qspi-1.0"; | |
736 | status = "disabled"; | |
737 | clock-names = "ref_clk", "pclk"; | |
738 | interrupts = <0 15 4>; | |
739 | interrupt-parent = <&gic>; | |
740 | num-cs = <1>; | |
b976fd63 MS |
741 | reg = <0x0 0xff0f0000 0x0 0x1000>, |
742 | <0x0 0xc0000000 0x0 0x8000000>; | |
44303dfa MS |
743 | #address-cells = <1>; |
744 | #size-cells = <0>; | |
ba6ad317 MS |
745 | #stream-id-cells = <1>; |
746 | iommus = <&smmu 0x873>; | |
8f4e3972 | 747 | power-domains = <&pd_qspi>; |
44303dfa MS |
748 | }; |
749 | ||
750 | rtc: rtc@ffa60000 { | |
751 | compatible = "xlnx,zynqmp-rtc"; | |
752 | status = "disabled"; | |
b976fd63 | 753 | reg = <0x0 0xffa60000 0x0 0x100>; |
44303dfa MS |
754 | interrupt-parent = <&gic>; |
755 | interrupts = <0 26 4>, <0 27 4>; | |
756 | interrupt-names = "alarm", "sec"; | |
757 | }; | |
758 | ||
db6c62e1 AKV |
759 | serdes: zynqmp_phy@fd400000 { |
760 | compatible = "xlnx,zynqmp-psgtr"; | |
761 | status = "disabled"; | |
b976fd63 MS |
762 | reg = <0x0 0xfd400000 0x0 0x40000>, |
763 | <0x0 0xfd3d0000 0x0 0x1000>, | |
764 | <0x0 0xfd1a0000 0x0 0x1000>, | |
765 | <0x0 0xff5e0000 0x0 0x1000>; | |
db6c62e1 AKV |
766 | reg-names = "serdes", "siou", "fpd", "lpd"; |
767 | xlnx,tx_termination_fix; | |
768 | lane0: lane0 { | |
769 | #phy-cells = <4>; | |
770 | }; | |
771 | lane1: lane1 { | |
772 | #phy-cells = <4>; | |
773 | }; | |
774 | lane2: lane2 { | |
775 | #phy-cells = <4>; | |
776 | }; | |
777 | lane3: lane3 { | |
778 | #phy-cells = <4>; | |
779 | }; | |
780 | }; | |
781 | ||
44303dfa MS |
782 | sata: ahci@fd0c0000 { |
783 | compatible = "ceva,ahci-1v84"; | |
784 | status = "disabled"; | |
b976fd63 | 785 | reg = <0x0 0xfd0c0000 0x0 0x2000>; |
44303dfa MS |
786 | interrupt-parent = <&gic>; |
787 | interrupts = <0 133 4>; | |
8f4e3972 | 788 | power-domains = <&pd_sata>; |
44303dfa MS |
789 | }; |
790 | ||
791 | sdhci0: sdhci@ff160000 { | |
c9811e14 | 792 | u-boot,dm-pre-reloc; |
0488a5e1 | 793 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
44303dfa MS |
794 | status = "disabled"; |
795 | interrupt-parent = <&gic>; | |
796 | interrupts = <0 48 4>; | |
b976fd63 | 797 | reg = <0x0 0xff160000 0x0 0x1000>; |
44303dfa | 798 | clock-names = "clk_xin", "clk_ahb"; |
0488a5e1 | 799 | xlnx,device_id = <0>; |
ba6ad317 MS |
800 | #stream-id-cells = <1>; |
801 | iommus = <&smmu 0x870>; | |
8f4e3972 | 802 | power-domains = <&pd_sd0>; |
44303dfa MS |
803 | }; |
804 | ||
805 | sdhci1: sdhci@ff170000 { | |
c9811e14 | 806 | u-boot,dm-pre-reloc; |
0488a5e1 | 807 | compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
44303dfa MS |
808 | status = "disabled"; |
809 | interrupt-parent = <&gic>; | |
810 | interrupts = <0 49 4>; | |
b976fd63 | 811 | reg = <0x0 0xff170000 0x0 0x1000>; |
44303dfa | 812 | clock-names = "clk_xin", "clk_ahb"; |
0488a5e1 | 813 | xlnx,device_id = <1>; |
ba6ad317 MS |
814 | #stream-id-cells = <1>; |
815 | iommus = <&smmu 0x871>; | |
8f4e3972 | 816 | power-domains = <&pd_sd1>; |
44303dfa MS |
817 | }; |
818 | ||
819 | smmu: smmu@fd800000 { | |
820 | compatible = "arm,mmu-500"; | |
b976fd63 | 821 | reg = <0x0 0xfd800000 0x0 0x20000>; |
ba6ad317 | 822 | #iommu-cells = <1>; |
44303dfa MS |
823 | #global-interrupts = <1>; |
824 | interrupt-parent = <&gic>; | |
88a85aac EI |
825 | interrupts = <0 155 4>, |
826 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
827 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
828 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, | |
829 | <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; | |
7f1d7d97 EI |
830 | mmu-masters = < &gem0 0x874 |
831 | &gem1 0x875 | |
832 | &gem2 0x876 | |
ba6ad317 MS |
833 | &gem3 0x877 |
834 | &usb0 0x860 | |
835 | &usb1 0x861 | |
836 | &qspi 0x873 | |
837 | &lpd_dma_chan1 0x868 | |
838 | &lpd_dma_chan2 0x869 | |
839 | &lpd_dma_chan3 0x86a | |
840 | &lpd_dma_chan4 0x86b | |
841 | &lpd_dma_chan5 0x86c | |
842 | &lpd_dma_chan6 0x86d | |
843 | &lpd_dma_chan7 0x86e | |
844 | &lpd_dma_chan8 0x86f | |
845 | &fpd_dma_chan1 0x14e8 | |
846 | &fpd_dma_chan2 0x14e9 | |
847 | &fpd_dma_chan3 0x14ea | |
848 | &fpd_dma_chan4 0x14eb | |
849 | &fpd_dma_chan5 0x14ec | |
850 | &fpd_dma_chan6 0x14ed | |
851 | &fpd_dma_chan7 0x14ee | |
852 | &fpd_dma_chan8 0x14ef | |
853 | &sdhci0 0x870 | |
854 | &sdhci1 0x871 | |
855 | &nand0 0x872>; | |
44303dfa MS |
856 | }; |
857 | ||
858 | spi0: spi@ff040000 { | |
859 | compatible = "cdns,spi-r1p6"; | |
860 | status = "disabled"; | |
861 | interrupt-parent = <&gic>; | |
862 | interrupts = <0 19 4>; | |
b976fd63 | 863 | reg = <0x0 0xff040000 0x0 0x1000>; |
44303dfa MS |
864 | clock-names = "ref_clk", "pclk"; |
865 | #address-cells = <1>; | |
866 | #size-cells = <0>; | |
8f4e3972 | 867 | power-domains = <&pd_spi0>; |
44303dfa MS |
868 | }; |
869 | ||
870 | spi1: spi@ff050000 { | |
871 | compatible = "cdns,spi-r1p6"; | |
872 | status = "disabled"; | |
873 | interrupt-parent = <&gic>; | |
874 | interrupts = <0 20 4>; | |
b976fd63 | 875 | reg = <0x0 0xff050000 0x0 0x1000>; |
44303dfa MS |
876 | clock-names = "ref_clk", "pclk"; |
877 | #address-cells = <1>; | |
878 | #size-cells = <0>; | |
8f4e3972 | 879 | power-domains = <&pd_spi1>; |
44303dfa MS |
880 | }; |
881 | ||
882 | ttc0: timer@ff110000 { | |
883 | compatible = "cdns,ttc"; | |
884 | status = "disabled"; | |
885 | interrupt-parent = <&gic>; | |
886 | interrupts = <0 36 4>, <0 37 4>, <0 38 4>; | |
b976fd63 | 887 | reg = <0x0 0xff110000 0x0 0x1000>; |
44303dfa | 888 | timer-width = <32>; |
8f4e3972 | 889 | power-domains = <&pd_ttc0>; |
44303dfa MS |
890 | }; |
891 | ||
892 | ttc1: timer@ff120000 { | |
893 | compatible = "cdns,ttc"; | |
894 | status = "disabled"; | |
895 | interrupt-parent = <&gic>; | |
896 | interrupts = <0 39 4>, <0 40 4>, <0 41 4>; | |
b976fd63 | 897 | reg = <0x0 0xff120000 0x0 0x1000>; |
44303dfa | 898 | timer-width = <32>; |
8f4e3972 | 899 | power-domains = <&pd_ttc1>; |
44303dfa MS |
900 | }; |
901 | ||
902 | ttc2: timer@ff130000 { | |
903 | compatible = "cdns,ttc"; | |
904 | status = "disabled"; | |
905 | interrupt-parent = <&gic>; | |
906 | interrupts = <0 42 4>, <0 43 4>, <0 44 4>; | |
b976fd63 | 907 | reg = <0x0 0xff130000 0x0 0x1000>; |
44303dfa | 908 | timer-width = <32>; |
8f4e3972 | 909 | power-domains = <&pd_ttc2>; |
44303dfa MS |
910 | }; |
911 | ||
912 | ttc3: timer@ff140000 { | |
913 | compatible = "cdns,ttc"; | |
914 | status = "disabled"; | |
915 | interrupt-parent = <&gic>; | |
916 | interrupts = <0 45 4>, <0 46 4>, <0 47 4>; | |
b976fd63 | 917 | reg = <0x0 0xff140000 0x0 0x1000>; |
44303dfa | 918 | timer-width = <32>; |
8f4e3972 | 919 | power-domains = <&pd_ttc3>; |
44303dfa MS |
920 | }; |
921 | ||
922 | uart0: serial@ff000000 { | |
c9811e14 | 923 | u-boot,dm-pre-reloc; |
ca2f5878 | 924 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
44303dfa MS |
925 | status = "disabled"; |
926 | interrupt-parent = <&gic>; | |
927 | interrupts = <0 21 4>; | |
b976fd63 | 928 | reg = <0x0 0xff000000 0x0 0x1000>; |
44303dfa | 929 | clock-names = "uart_clk", "pclk"; |
8f4e3972 | 930 | power-domains = <&pd_uart0>; |
44303dfa MS |
931 | }; |
932 | ||
933 | uart1: serial@ff010000 { | |
c9811e14 | 934 | u-boot,dm-pre-reloc; |
ca2f5878 | 935 | compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
44303dfa MS |
936 | status = "disabled"; |
937 | interrupt-parent = <&gic>; | |
938 | interrupts = <0 22 4>; | |
b976fd63 | 939 | reg = <0x0 0xff010000 0x0 0x1000>; |
44303dfa | 940 | clock-names = "uart_clk", "pclk"; |
8f4e3972 | 941 | power-domains = <&pd_uart1>; |
44303dfa MS |
942 | }; |
943 | ||
c926e6fb | 944 | usb0: usb0 { |
a84de48e | 945 | #address-cells = <2>; |
b976fd63 | 946 | #size-cells = <2>; |
44303dfa | 947 | status = "disabled"; |
a84de48e MS |
948 | compatible = "xlnx,zynqmp-dwc3"; |
949 | clock-names = "bus_clk", "ref_clk"; | |
950 | clocks = <&clk125>, <&clk125>; | |
ba6ad317 MS |
951 | #stream-id-cells = <1>; |
952 | iommus = <&smmu 0x860>; | |
8f4e3972 | 953 | power-domains = <&pd_usb0>; |
a84de48e MS |
954 | ranges; |
955 | ||
956 | dwc3_0: dwc3@fe200000 { | |
957 | compatible = "snps,dwc3"; | |
958 | status = "disabled"; | |
b976fd63 | 959 | reg = <0x0 0xfe200000 0x0 0x40000>; |
a84de48e MS |
960 | interrupt-parent = <&gic>; |
961 | interrupts = <0 65 4>; | |
962 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
963 | snps,refclk_fladj; | |
964 | }; | |
44303dfa MS |
965 | }; |
966 | ||
c926e6fb | 967 | usb1: usb1 { |
a84de48e | 968 | #address-cells = <2>; |
b976fd63 | 969 | #size-cells = <2>; |
44303dfa | 970 | status = "disabled"; |
a84de48e MS |
971 | compatible = "xlnx,zynqmp-dwc3"; |
972 | clock-names = "bus_clk", "ref_clk"; | |
973 | clocks = <&clk125>, <&clk125>; | |
ba6ad317 MS |
974 | #stream-id-cells = <1>; |
975 | iommus = <&smmu 0x861>; | |
8f4e3972 | 976 | power-domains = <&pd_usb1>; |
a84de48e MS |
977 | ranges; |
978 | ||
979 | dwc3_1: dwc3@fe300000 { | |
980 | compatible = "snps,dwc3"; | |
981 | status = "disabled"; | |
b976fd63 | 982 | reg = <0x0 0xfe300000 0x0 0x40000>; |
a84de48e MS |
983 | interrupt-parent = <&gic>; |
984 | interrupts = <0 70 4>; | |
985 | /* snps,quirk-frame-length-adjustment = <0x20>; */ | |
986 | snps,refclk_fladj; | |
987 | }; | |
44303dfa MS |
988 | }; |
989 | ||
990 | watchdog0: watchdog@fd4d0000 { | |
991 | compatible = "cdns,wdt-r1p2"; | |
992 | status = "disabled"; | |
993 | interrupt-parent = <&gic>; | |
d3fd433f | 994 | interrupts = <0 113 1>; |
b976fd63 | 995 | reg = <0x0 0xfd4d0000 0x0 0x1000>; |
44303dfa MS |
996 | timeout-sec = <10>; |
997 | }; | |
998 | ||
999 | xilinx_drm: xilinx_drm { | |
1000 | compatible = "xlnx,drm"; | |
1001 | status = "disabled"; | |
1002 | xlnx,encoder-slave = <&xlnx_dp>; | |
1003 | xlnx,connector-type = "DisplayPort"; | |
1004 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
1005 | planes { | |
1006 | xlnx,pixel-format = "rgb565"; | |
1007 | plane0 { | |
1008 | dmas = <&xlnx_dpdma 3>; | |
bfe27980 | 1009 | dma-names = "dma0"; |
44303dfa MS |
1010 | }; |
1011 | plane1 { | |
bfe27980 HK |
1012 | dmas = <&xlnx_dpdma 0>, |
1013 | <&xlnx_dpdma 1>, | |
1014 | <&xlnx_dpdma 2>; | |
1015 | dma-names = "dma0", "dma1", "dma2"; | |
44303dfa MS |
1016 | }; |
1017 | }; | |
1018 | }; | |
1019 | ||
695d75a1 | 1020 | xlnx_dp: dp@fd4a0000 { |
44303dfa MS |
1021 | compatible = "xlnx,v-dp"; |
1022 | status = "disabled"; | |
b976fd63 | 1023 | reg = <0x0 0xfd4a0000 0x0 0x1000>; |
44303dfa MS |
1024 | interrupts = <0 119 4>; |
1025 | interrupt-parent = <&gic>; | |
1026 | clock-names = "aclk", "aud_clk"; | |
1027 | xlnx,dp-version = "v1.2"; | |
1028 | xlnx,max-lanes = <2>; | |
1029 | xlnx,max-link-rate = <540000>; | |
1030 | xlnx,max-bpc = <16>; | |
1031 | xlnx,enable-ycrcb; | |
1032 | xlnx,colormetry = "rgb"; | |
1033 | xlnx,bpc = <8>; | |
1034 | xlnx,audio-chan = <2>; | |
1035 | xlnx,dp-sub = <&xlnx_dp_sub>; | |
939cfeaf | 1036 | xlnx,max-pclock-frequency = <300000>; |
44303dfa MS |
1037 | }; |
1038 | ||
1039 | xlnx_dp_snd_card: dp_snd_card { | |
1040 | compatible = "xlnx,dp-snd-card"; | |
1041 | status = "disabled"; | |
1042 | xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; | |
1043 | xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; | |
1044 | }; | |
1045 | ||
1046 | xlnx_dp_snd_codec0: dp_snd_codec0 { | |
1047 | compatible = "xlnx,dp-snd-codec"; | |
1048 | status = "disabled"; | |
1049 | clock-names = "aud_clk"; | |
1050 | }; | |
1051 | ||
1052 | xlnx_dp_snd_pcm0: dp_snd_pcm0 { | |
1053 | compatible = "xlnx,dp-snd-pcm"; | |
1054 | status = "disabled"; | |
1055 | dmas = <&xlnx_dpdma 4>; | |
1056 | dma-names = "tx"; | |
1057 | }; | |
1058 | ||
1059 | xlnx_dp_snd_pcm1: dp_snd_pcm1 { | |
1060 | compatible = "xlnx,dp-snd-pcm"; | |
1061 | status = "disabled"; | |
1062 | dmas = <&xlnx_dpdma 5>; | |
1063 | dma-names = "tx"; | |
1064 | }; | |
1065 | ||
695d75a1 | 1066 | xlnx_dp_sub: dp_sub@fd4aa000 { |
44303dfa MS |
1067 | compatible = "xlnx,dp-sub"; |
1068 | status = "disabled"; | |
b976fd63 MS |
1069 | reg = <0x0 0xfd4aa000 0x0 0x1000>, |
1070 | <0x0 0xfd4ab000 0x0 0x1000>, | |
1071 | <0x0 0xfd4ac000 0x0 0x1000>; | |
44303dfa MS |
1072 | reg-names = "blend", "av_buf", "aud"; |
1073 | xlnx,output-fmt = "rgb"; | |
939cfeaf HK |
1074 | xlnx,vid-fmt = "yuyv"; |
1075 | xlnx,gfx-fmt = "rgb565"; | |
44303dfa MS |
1076 | }; |
1077 | ||
1078 | xlnx_dpdma: dma@fd4c0000 { | |
1079 | compatible = "xlnx,dpdma"; | |
1080 | status = "disabled"; | |
b976fd63 | 1081 | reg = <0x0 0xfd4c0000 0x0 0x1000>; |
44303dfa MS |
1082 | interrupts = <0 122 4>; |
1083 | interrupt-parent = <&gic>; | |
1084 | clock-names = "axi_clk"; | |
1085 | dma-channels = <6>; | |
1086 | #dma-cells = <1>; | |
c926e6fb | 1087 | dma-video0channel { |
44303dfa MS |
1088 | compatible = "xlnx,video0"; |
1089 | }; | |
c926e6fb | 1090 | dma-video1channel { |
44303dfa MS |
1091 | compatible = "xlnx,video1"; |
1092 | }; | |
c926e6fb | 1093 | dma-video2channel { |
44303dfa MS |
1094 | compatible = "xlnx,video2"; |
1095 | }; | |
c926e6fb | 1096 | dma-graphicschannel { |
44303dfa MS |
1097 | compatible = "xlnx,graphics"; |
1098 | }; | |
c926e6fb | 1099 | dma-audio0channel { |
44303dfa MS |
1100 | compatible = "xlnx,audio0"; |
1101 | }; | |
c926e6fb | 1102 | dma-audio1channel { |
44303dfa MS |
1103 | compatible = "xlnx,audio1"; |
1104 | }; | |
1105 | }; | |
1106 | }; | |
1107 | }; |