[people/ms/u-boot.git] / arch / arm / include / asm / arch-pantheon / cpu.h

/*
 * (C) Copyright 2011
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Lei Wen <leiwen@marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _PANTHEON_CPU_H
#define _PANTHEON_CPU_H

#include <asm/io.h>
#include <asm/system.h>

/*
 * Main Power Management (MPMU) Registers
 * Refer Register Datasheet 9.1
 */
struct panthmpmu_registers {
	u8 pad0[0x0024];
	u32 ccgr;	/*0x0024*/
	u8 pad1[0x0200 - 0x024 - 4];
	u32 wdtpcr;	/*0x0200*/
	u8 pad2[0x1020 - 0x200 - 4];
	u32 aprr;	/*0x1020*/
	u32 acgr;	/*0x1024*/
};

/*
 * Application Power Management (APMU) Registers
 * Refer Register Datasheet 9.2
 */
struct panthapmu_registers {
	u8 pad0[0x0054];
	u32 sd1;	/*0x0054*/
	u8 pad1[0x00e0 - 0x054 - 4];
	u32 sd3;	/*0x00e0*/
};

/*
 * APB Clock Reset/Control Registers
 * Refer Register Datasheet 6.14
 */
struct panthapb_registers {
	u32 uart0;	/*0x000*/
	u32 uart1;	/*0x004*/
	u32 gpio;	/*0x008*/
	u8 pad0[0x02c - 0x08 - 4];
	u32 twsi;	/*0x02c*/
	u8 pad1[0x034 - 0x2c - 4];
	u32 timers;	/*0x034*/
};

/*
 * CPU Interface Registers
 * Refer Register Datasheet 4.3
 */
struct panthcpu_registers {
	u32 chip_id;		/* Chip Id Reg */
	u32 pad;
	u32 cpu_conf;		/* CPU Conf Reg */
	u32 pad1;
	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
	u32 pad2;
	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
	u32 mcb_conf;		/* MCB Conf Reg */
	u32 sys_boot_ctl;	/* Sytem Boot Control */
};

/*
 * Functions
 */
u32 panth_sdram_base(int);
u32 panth_sdram_size(int);
int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);

#endif /* _PANTHEON_CPU_H */
Commit	Line	Data
896e2ca9 LW	1	/*
	2	* (C) Copyright 2011
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Lei Wen <leiwen@marvell.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
896e2ca9 LW	7	*/
	8
	9	#ifndef _PANTHEON_CPU_H
	10	#define _PANTHEON_CPU_H
	11
	12	#include <asm/io.h>
	13	#include <asm/system.h>
	14
	15	/*
	16	* Main Power Management (MPMU) Registers
	17	* Refer Register Datasheet 9.1
	18	*/
	19	struct panthmpmu_registers {
	20	u8 pad0[0x0024];
	21	u32 ccgr; /0x0024/
	22	u8 pad1[0x0200 - 0x024 - 4];
	23	u32 wdtpcr; /0x0200/
	24	u8 pad2[0x1020 - 0x200 - 4];
	25	u32 aprr; /0x1020/
	26	u32 acgr; /0x1024/
	27	};
	28
3d90a2ad LW	29	/*
	30	* Application Power Management (APMU) Registers
	31	* Refer Register Datasheet 9.2
	32	*/
	33	struct panthapmu_registers {
	34	u8 pad0[0x0054];
	35	u32 sd1; /0x0054/
	36	u8 pad1[0x00e0 - 0x054 - 4];
	37	u32 sd3; /0x00e0/
	38	};
	39
896e2ca9 LW	40	/*
	41	* APB Clock Reset/Control Registers
	42	* Refer Register Datasheet 6.14
	43	*/
	44	struct panthapb_registers {
	45	u32 uart0; /0x000/
	46	u32 uart1; /0x004/
	47	u32 gpio; /0x008/
aa3b168e LW	48	u8 pad0[0x02c - 0x08 - 4];
	49	u32 twsi; /0x02c/
	50	u8 pad1[0x034 - 0x2c - 4];
896e2ca9 LW	51	u32 timers; /0x034/
	52	};
	53
	54	/*
	55	* CPU Interface Registers
	56	* Refer Register Datasheet 4.3
	57	*/
	58	struct panthcpu_registers {
	59	u32 chip_id; /* Chip Id Reg */
	60	u32 pad;
	61	u32 cpu_conf; /* CPU Conf Reg */
	62	u32 pad1;
	63	u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
	64	u32 pad2;
	65	u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
	66	u32 mcb_conf; /* MCB Conf Reg */
	67	u32 sys_boot_ctl; /* Sytem Boot Control */
	68	};
	69
	70	/*
	71	* Functions
	72	*/
	73	u32 panth_sdram_base(int);
	74	u32 panth_sdram_size(int);
3d90a2ad	75	int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
896e2ca9 LW	76
896e2ca9 LW	77	#endif /* _PANTHEON_CPU_H */