[people/ms/u-boot.git] / arch / arm / mach-imx / mx7 / soc.c

/*
 * Copyright (C) 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/dma.h>
#include <asm/mach-imx/hab.h>
#include <asm/mach-imx/rdc-sema.h>
#include <asm/arch/imx-rdc.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <imx_thermal.h>

#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx7_thermal_plat = {
	.regs = (void *)ANATOP_BASE_ADDR,
	.fuse_bank = 3,
	.fuse_word = 3,
};

U_BOOT_DEVICE(imx7_thermal) = {
	.name = "imx_thermal",
	.platdata = &imx7_thermal_plat,
};
#endif

#if CONFIG_IS_ENABLED(IMX_RDC)
/*
 * In current design, if any peripheral was assigned to both A7 and M4,
 * it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
 * low power mode. So M4 sleep will cause some peripherals fail to work
 * at A7 core side. At default, all resources are in domain 0 - 3.
 *
 * There are 26 peripherals impacted by this IC issue:
 * SIM2(sim2/emvsim2)
 * SIM1(sim1/emvsim1)
 * UART1/UART2/UART3/UART4/UART5/UART6/UART7
 * SAI1/SAI2/SAI3
 * WDOG1/WDOG2/WDOG3/WDOG4
 * GPT1/GPT2/GPT3/GPT4
 * PWM1/PWM2/PWM3/PWM4
 * ENET1/ENET2
 * Software Workaround:
 * Here we setup some resources to domain 0 where M4 codes will move
 * the M4 out of this domain. Then M4 is not able to access them any longer.
 * This is a workaround for ic issue. So the peripherals are not shared
 * by them. This way requires the uboot implemented the RDC driver and
 * set the 26 IPs above to domain 0 only. M4 code will assign resource
 * to its own domain, if it want to use the resource.
 */
static rdc_peri_cfg_t const resources[] = {
	(RDC_PER_SIM1 | RDC_DOMAIN(0)),
	(RDC_PER_SIM2 | RDC_DOMAIN(0)),
	(RDC_PER_UART1 | RDC_DOMAIN(0)),
	(RDC_PER_UART2 | RDC_DOMAIN(0)),
	(RDC_PER_UART3 | RDC_DOMAIN(0)),
	(RDC_PER_UART4 | RDC_DOMAIN(0)),
	(RDC_PER_UART5 | RDC_DOMAIN(0)),
	(RDC_PER_UART6 | RDC_DOMAIN(0)),
	(RDC_PER_UART7 | RDC_DOMAIN(0)),
	(RDC_PER_SAI1 | RDC_DOMAIN(0)),
	(RDC_PER_SAI2 | RDC_DOMAIN(0)),
	(RDC_PER_SAI3 | RDC_DOMAIN(0)),
	(RDC_PER_WDOG1 | RDC_DOMAIN(0)),
	(RDC_PER_WDOG2 | RDC_DOMAIN(0)),
	(RDC_PER_WDOG3 | RDC_DOMAIN(0)),
	(RDC_PER_WDOG4 | RDC_DOMAIN(0)),
	(RDC_PER_GPT1 | RDC_DOMAIN(0)),
	(RDC_PER_GPT2 | RDC_DOMAIN(0)),
	(RDC_PER_GPT3 | RDC_DOMAIN(0)),
	(RDC_PER_GPT4 | RDC_DOMAIN(0)),
	(RDC_PER_PWM1 | RDC_DOMAIN(0)),
	(RDC_PER_PWM2 | RDC_DOMAIN(0)),
	(RDC_PER_PWM3 | RDC_DOMAIN(0)),
	(RDC_PER_PWM4 | RDC_DOMAIN(0)),
	(RDC_PER_ENET1 | RDC_DOMAIN(0)),
	(RDC_PER_ENET2 | RDC_DOMAIN(0)),
};

static void isolate_resource(void)
{
	imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
}
#endif

#if defined(CONFIG_SECURE_BOOT)
struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
	.bank = 1,
	.word = 3,
};
#endif

/*
 * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
 * defines a 2-bit SPEED_GRADING
 */
#define OCOTP_TESTER3_SPEED_SHIFT	8
#define OCOTP_TESTER3_SPEED_800MHZ	0
#define OCOTP_TESTER3_SPEED_500MHZ	1
#define OCOTP_TESTER3_SPEED_1GHZ	2
#define OCOTP_TESTER3_SPEED_1P2GHZ	3

u32 get_cpu_speed_grade_hz(void)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->tester3);
	val >>= OCOTP_TESTER3_SPEED_SHIFT;
	val &= 0x3;

	switch(val) {
	case OCOTP_TESTER3_SPEED_800MHZ:
		return 800000000;
	case OCOTP_TESTER3_SPEED_500MHZ:
		return 500000000;
	case OCOTP_TESTER3_SPEED_1GHZ:
		return 1000000000;
	case OCOTP_TESTER3_SPEED_1P2GHZ:
		return 1200000000;
	}
	return 0;
}

/*
 * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
 * defines a 2-bit SPEED_GRADING
 */
#define OCOTP_TESTER3_TEMP_SHIFT	6

u32 get_cpu_temp_grade(int *minc, int *maxc)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	uint32_t val;

	val = readl(&fuse->tester3);
	val >>= OCOTP_TESTER3_TEMP_SHIFT;
	val &= 0x3;

	if (minc && maxc) {
		if (val == TEMP_AUTOMOTIVE) {
			*minc = -40;
			*maxc = 125;
		} else if (val == TEMP_INDUSTRIAL) {
			*minc = -40;
			*maxc = 105;
		} else if (val == TEMP_EXTCOMMERCIAL) {
			*minc = -20;
			*maxc = 105;
		} else {
			*minc = 0;
			*maxc = 95;
		}
	}
	return val;
}

static bool is_mx7d(void)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[1];
	struct fuse_bank1_regs *fuse =
		(struct fuse_bank1_regs *)bank->fuse_regs;
	int val;

	val = readl(&fuse->tester4);
	if (val & 1)
		return false;
	else
		return true;
}

u32 get_cpu_rev(void)
{
	struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
						 ANATOP_BASE_ADDR;
	u32 reg = readl(&ccm_anatop->digprog);
	u32 type = (reg >> 16) & 0xff;

	if (!is_mx7d())
		type = MXC_CPU_MX7S;

	reg &= 0xff;
	return (type << 12) | reg;
}

#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
	return get_cpu_rev();
}
#endif

/* enable all periherial can be accessed in nosec mode */
static void init_csu(void)
{
	int i = 0;
	for (i = 0; i < CSU_NUM_REGS; i++)
		writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
}

static void imx_enet_mdio_fixup(void)
{
	struct iomuxc_gpr_base_regs *gpr_regs =
		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;

	/*
	 * The management data input/output (MDIO) requires open-drain,
	 * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
	 * this feature. So to TO1.1, need to enable open drain by setting
	 * bits GPR0[8:7].
	 */

	if (soc_rev() >= CHIP_REV_1_1) {
		setbits_le32(&gpr_regs->gpr[0],
			     IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
	}
}

int arch_cpu_init(void)
{
	init_aips();

	init_csu();
	/* Disable PDE bit of WMCR register */
	imx_set_wdog_powerdown(false);

	imx_enet_mdio_fixup();

#ifdef CONFIG_APBH_DMA
	/* Start APBH DMA */
	mxs_dma_init();
#endif

#if CONFIG_IS_ENABLED(IMX_RDC)
	isolate_resource();
#endif

	return 0;
}

#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	if (is_mx7d())
		env_set("soc", "imx7d");
	else
		env_set("soc", "imx7s");
#endif

	return 0;
}
#endif

#ifdef CONFIG_SERIAL_TAG
void get_board_serial(struct tag_serialnr *serialnr)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[0];
	struct fuse_bank0_regs *fuse =
		(struct fuse_bank0_regs *)bank->fuse_regs;

	serialnr->low = fuse->tester0;
	serialnr->high = fuse->tester1;
}
#endif

#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
	struct fuse_bank *bank = &ocotp->bank[9];
	struct fuse_bank9_regs *fuse =
		(struct fuse_bank9_regs *)bank->fuse_regs;

	if (0 == dev_id) {
		u32 value = readl(&fuse->mac_addr1);
		mac[0] = (value >> 8);
		mac[1] = value;

		value = readl(&fuse->mac_addr0);
		mac[2] = value >> 24;
		mac[3] = value >> 16;
		mac[4] = value >> 8;
		mac[5] = value;
	} else {
		u32 value = readl(&fuse->mac_addr2);
		mac[0] = value >> 24;
		mac[1] = value >> 16;
		mac[2] = value >> 8;
		mac[3] = value;

		value = readl(&fuse->mac_addr1);
		mac[4] = value >> 24;
		mac[5] = value >> 16;
	}
}
#endif

#ifdef CONFIG_IMX_BOOTAUX
int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
{
	u32 stack, pc;
	struct src *src_reg = (struct src *)SRC_BASE_ADDR;

	if (!boot_private_data)
		return 1;

	stack = *(u32 *)boot_private_data;
	pc = *(u32 *)(boot_private_data + 4);

	/* Set the stack and pc to M4 bootROM */
	writel(stack, M4_BOOTROM_BASE_ADDR);
	writel(pc, M4_BOOTROM_BASE_ADDR + 4);

	/* Enable M4 */
	clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
			SRC_M4RCR_ENABLE_M4_MASK);

	return 0;
}

int arch_auxiliary_core_check_up(u32 core_id)
{
	uint32_t val;
	struct src *src_reg = (struct src *)SRC_BASE_ADDR;

	val = readl(&src_reg->m4rcr);
	if (val & 0x00000001)
		return 0; /* assert in reset */

	return 1;
}
#endif

void set_wdog_reset(struct wdog_regs *wdog)
{
	u32 reg = readw(&wdog->wcr);
	/*
	 * Output WDOG_B signal to reset external pmic or POR_B decided by
	 * the board desgin. Without external reset, the peripherals/DDR/
	 * PMIC are not reset, that may cause system working abnormal.
	 */
	reg = readw(&wdog->wcr);
	reg |= 1 << 3;
	/*
	 * WDZST bit is write-once only bit. Align this bit in kernel,
	 * otherwise kernel code will have no chance to set this bit.
	 */
	reg |= 1 << 0;
	writew(reg, &wdog->wcr);
}

/*
 * cfg_val will be used for
 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
 * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
 * to SBMR1, which will determine the boot device.
 */
const struct boot_mode soc_boot_modes[] = {
	{"ecspi1:0",	MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
	{"ecspi1:1",	MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
	{"ecspi1:2",	MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
	{"ecspi1:3",	MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},

	{"weim",	MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
	{"qspi1",	MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
	/* 4 bit bus width */
	{"usdhc1",	MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
	{"usdhc2",	MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
	{"usdhc3",	MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
	{"mmc1",	MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
	{"mmc2",	MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
	{"mmc3",	MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
	{NULL,		0},
};

enum boot_device get_boot_device(void)
{
	struct bootrom_sw_info **p =
		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;

	enum boot_device boot_dev = SD1_BOOT;
	u8 boot_type = (*p)->boot_dev_type;
	u8 boot_instance = (*p)->boot_dev_instance;

	switch (boot_type) {
	case BOOT_TYPE_SD:
		boot_dev = boot_instance + SD1_BOOT;
		break;
	case BOOT_TYPE_MMC:
		boot_dev = boot_instance + MMC1_BOOT;
		break;
	case BOOT_TYPE_NAND:
		boot_dev = NAND_BOOT;
		break;
	case BOOT_TYPE_QSPI:
		boot_dev = QSPI_BOOT;
		break;
	case BOOT_TYPE_WEIM:
		boot_dev = WEIM_NOR_BOOT;
		break;
	case BOOT_TYPE_SPINOR:
		boot_dev = SPI_NOR_BOOT;
		break;
	default:
		break;
	}

	return boot_dev;
}

#ifdef CONFIG_ENV_IS_IN_MMC
__weak int board_mmc_get_env_dev(int devno)
{
	return CONFIG_SYS_MMC_ENV_DEV;
}

int mmc_get_env_dev(void)
{
	struct bootrom_sw_info **p =
		(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
	int devno = (*p)->boot_dev_instance;
	u8 boot_type = (*p)->boot_dev_type;

	/* If not boot from sd/mmc, use default value */
	if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
		return CONFIG_SYS_MMC_ENV_DEV;

	return board_mmc_get_env_dev(devno);
}
#endif

void s_init(void)
{
#if !defined CONFIG_SPL_BUILD
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
			"mrc p15, 0, r0, c1, c0, 1\n"
			"orr r0, r0, #1 << 6\n"
			"mcr p15, 0, r0, c1, c0, 1\n");
#endif
	/* clock configuration. */
	clock_init();

	return;
}

void reset_misc(void)
{
#ifdef CONFIG_VIDEO_MXS
	lcdif_power_down();
#endif
}
Commit	Line	Data
c5752f73 AA	1	/*
	2	* Copyright (C) 2015 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/imx-regs.h>
	10	#include <asm/arch/clock.h>
	11	#include <asm/arch/sys_proto.h>
552a848e SB	12	#include <asm/mach-imx/boot_mode.h>
	13	#include <asm/mach-imx/dma.h>
	14	#include <asm/mach-imx/hab.h>
	15	#include <asm/mach-imx/rdc-sema.h>
35c4ce5e	16	#include <asm/arch/imx-rdc.h>
c5752f73 AA	17	#include <asm/arch/crm_regs.h>
	18	#include <dm.h>
	19	#include <imx_thermal.h>
	20
c5752f73 AA	21	#if defined(CONFIG_IMX_THERMAL)
	22	static const struct imx_thermal_plat imx7_thermal_plat = {
	23	.regs = (void *)ANATOP_BASE_ADDR,
	24	.fuse_bank = 3,
	25	.fuse_word = 3,
	26	};
	27
	28	U_BOOT_DEVICE(imx7_thermal) = {
	29	.name = "imx_thermal",
	30	.platdata = &imx7_thermal_plat,
	31	};
	32	#endif
	33
e872f27a	34	#if CONFIG_IS_ENABLED(IMX_RDC)
35c4ce5e PF	35	/*
	36	* In current design, if any peripheral was assigned to both A7 and M4,
	37	* it will receive ipg_stop or ipg_wait when any of the 2 platforms enter
	38	* low power mode. So M4 sleep will cause some peripherals fail to work
	39	* at A7 core side. At default, all resources are in domain 0 - 3.
	40	*
	41	* There are 26 peripherals impacted by this IC issue:
	42	* SIM2(sim2/emvsim2)
	43	* SIM1(sim1/emvsim1)
	44	* UART1/UART2/UART3/UART4/UART5/UART6/UART7
	45	* SAI1/SAI2/SAI3
	46	* WDOG1/WDOG2/WDOG3/WDOG4
	47	* GPT1/GPT2/GPT3/GPT4
	48	* PWM1/PWM2/PWM3/PWM4
	49	* ENET1/ENET2
	50	* Software Workaround:
	51	* Here we setup some resources to domain 0 where M4 codes will move
	52	* the M4 out of this domain. Then M4 is not able to access them any longer.
	53	* This is a workaround for ic issue. So the peripherals are not shared
	54	* by them. This way requires the uboot implemented the RDC driver and
	55	* set the 26 IPs above to domain 0 only. M4 code will assign resource
	56	* to its own domain, if it want to use the resource.
	57	*/
	58	static rdc_peri_cfg_t const resources[] = {
	59	(RDC_PER_SIM1 \| RDC_DOMAIN(0)),
	60	(RDC_PER_SIM2 \| RDC_DOMAIN(0)),
	61	(RDC_PER_UART1 \| RDC_DOMAIN(0)),
	62	(RDC_PER_UART2 \| RDC_DOMAIN(0)),
	63	(RDC_PER_UART3 \| RDC_DOMAIN(0)),
	64	(RDC_PER_UART4 \| RDC_DOMAIN(0)),
	65	(RDC_PER_UART5 \| RDC_DOMAIN(0)),
	66	(RDC_PER_UART6 \| RDC_DOMAIN(0)),
	67	(RDC_PER_UART7 \| RDC_DOMAIN(0)),
	68	(RDC_PER_SAI1 \| RDC_DOMAIN(0)),
	69	(RDC_PER_SAI2 \| RDC_DOMAIN(0)),
	70	(RDC_PER_SAI3 \| RDC_DOMAIN(0)),
	71	(RDC_PER_WDOG1 \| RDC_DOMAIN(0)),
	72	(RDC_PER_WDOG2 \| RDC_DOMAIN(0)),
	73	(RDC_PER_WDOG3 \| RDC_DOMAIN(0)),
	74	(RDC_PER_WDOG4 \| RDC_DOMAIN(0)),
	75	(RDC_PER_GPT1 \| RDC_DOMAIN(0)),
	76	(RDC_PER_GPT2 \| RDC_DOMAIN(0)),
	77	(RDC_PER_GPT3 \| RDC_DOMAIN(0)),
	78	(RDC_PER_GPT4 \| RDC_DOMAIN(0)),
	79	(RDC_PER_PWM1 \| RDC_DOMAIN(0)),
	80	(RDC_PER_PWM2 \| RDC_DOMAIN(0)),
	81	(RDC_PER_PWM3 \| RDC_DOMAIN(0)),
	82	(RDC_PER_PWM4 \| RDC_DOMAIN(0)),
	83	(RDC_PER_ENET1 \| RDC_DOMAIN(0)),
	84	(RDC_PER_ENET2 \| RDC_DOMAIN(0)),
	85	};
	86
	87	static void isolate_resource(void)
	88	{
	89	imx_rdc_setup_peripherals(resources, ARRAY_SIZE(resources));
	90	}
	91	#endif
	92
bb955146 AA	93	#if defined(CONFIG_SECURE_BOOT)
	94	struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
	95	.bank = 1,
	96	.word = 3,
	97	};
	98	#endif
	99
c5752f73 AA	100	/*
	101	* OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
	102	* defines a 2-bit SPEED_GRADING
	103	*/
	104	#define OCOTP_TESTER3_SPEED_SHIFT 8
	105	#define OCOTP_TESTER3_SPEED_800MHZ 0
31b8a901	106	#define OCOTP_TESTER3_SPEED_500MHZ 1
c5752f73	107	#define OCOTP_TESTER3_SPEED_1GHZ 2
9b548bf8	108	#define OCOTP_TESTER3_SPEED_1P2GHZ 3
c5752f73 AA	109
	110	u32 get_cpu_speed_grade_hz(void)
	111	{
	112	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	113	struct fuse_bank *bank = &ocotp->bank[1];
	114	struct fuse_bank1_regs *fuse =
	115	(struct fuse_bank1_regs *)bank->fuse_regs;
	116	uint32_t val;
	117
	118	val = readl(&fuse->tester3);
	119	val >>= OCOTP_TESTER3_SPEED_SHIFT;
	120	val &= 0x3;
	121
	122	switch(val) {
	123	case OCOTP_TESTER3_SPEED_800MHZ:
60a07fb8	124	return 800000000;
31b8a901 FE	125	case OCOTP_TESTER3_SPEED_500MHZ:
31b8a901 FE	126	return 500000000;
c5752f73	127	case OCOTP_TESTER3_SPEED_1GHZ:
60a07fb8	128	return 1000000000;
9b548bf8 FE	129	case OCOTP_TESTER3_SPEED_1P2GHZ:
9b548bf8 FE	130	return 1200000000;
c5752f73 AA	131	}
	132	return 0;
	133	}
	134
	135	/*
	136	* OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
	137	* defines a 2-bit SPEED_GRADING
	138	*/
	139	#define OCOTP_TESTER3_TEMP_SHIFT 6
	140
	141	u32 get_cpu_temp_grade(int minc, int maxc)
	142	{
	143	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	144	struct fuse_bank *bank = &ocotp->bank[1];
	145	struct fuse_bank1_regs *fuse =
	146	(struct fuse_bank1_regs *)bank->fuse_regs;
	147	uint32_t val;
	148
	149	val = readl(&fuse->tester3);
	150	val >>= OCOTP_TESTER3_TEMP_SHIFT;
	151	val &= 0x3;
	152
	153	if (minc && maxc) {
f697c2ac	154	if (val == TEMP_AUTOMOTIVE) {
c5752f73 AA	155	*minc = -40;
	156	*maxc = 125;
	157	} else if (val == TEMP_INDUSTRIAL) {
	158	*minc = -40;
	159	*maxc = 105;
	160	} else if (val == TEMP_EXTCOMMERCIAL) {
	161	*minc = -20;
	162	*maxc = 105;
	163	} else {
	164	*minc = 0;
	165	*maxc = 95;
	166	}
	167	}
	168	return val;
	169	}
	170
e25a0656 FE	171	static bool is_mx7d(void)
	172	{
	173	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	174	struct fuse_bank *bank = &ocotp->bank[1];
	175	struct fuse_bank1_regs *fuse =
	176	(struct fuse_bank1_regs *)bank->fuse_regs;
	177	int val;
	178
	179	val = readl(&fuse->tester4);
	180	if (val & 1)
	181	return false;
	182	else
	183	return true;
	184	}
	185
c5752f73 AA	186	u32 get_cpu_rev(void)
	187	{
	188	struct mxc_ccm_anatop_reg ccm_anatop = (struct mxc_ccm_anatop_reg )
	189	ANATOP_BASE_ADDR;
	190	u32 reg = readl(&ccm_anatop->digprog);
	191	u32 type = (reg >> 16) & 0xff;
	192
e25a0656 FE	193	if (!is_mx7d())
	194	type = MXC_CPU_MX7S;
	195
c5752f73 AA	196	reg &= 0xff;
	197	return (type << 12) \| reg;
	198	}
	199
	200	#ifdef CONFIG_REVISION_TAG
	201	u32 __weak get_board_rev(void)
	202	{
	203	return get_cpu_rev();
	204	}
	205	#endif
	206
7de47036 PF	207	/* enable all periherial can be accessed in nosec mode */
	208	static void init_csu(void)
	209	{
	210	int i = 0;
	211	for (i = 0; i < CSU_NUM_REGS; i++)
	212	writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
	213	}
	214
d9699de8 PF	215	static void imx_enet_mdio_fixup(void)
	216	{
	217	struct iomuxc_gpr_base_regs *gpr_regs =
	218	(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	219
	220	/*
	221	* The management data input/output (MDIO) requires open-drain,
	222	* i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
	223	* this feature. So to TO1.1, need to enable open drain by setting
	224	* bits GPR0[8:7].
	225	*/
	226
	227	if (soc_rev() >= CHIP_REV_1_1) {
	228	setbits_le32(&gpr_regs->gpr[0],
	229	IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
	230	}
	231	}
	232
c5752f73 AA	233	int arch_cpu_init(void)
	234	{
	235	init_aips();
	236
7de47036	237	init_csu();
c5752f73 AA	238	/* Disable PDE bit of WMCR register */
	239	imx_set_wdog_powerdown(false);
	240
d9699de8 PF	241	imx_enet_mdio_fixup();
d9699de8 PF	242
c5752f73 AA	243	#ifdef CONFIG_APBH_DMA
	244	/* Start APBH DMA */
	245	mxs_dma_init();
	246	#endif
	247
e872f27a PF	248	#if CONFIG_IS_ENABLED(IMX_RDC)
	249	isolate_resource();
	250	#endif
35c4ce5e	251
c5752f73 AA	252	return 0;
	253	}
	254
ec7fde3e SA	255	#ifdef CONFIG_ARCH_MISC_INIT
	256	int arch_misc_init(void)
	257	{
	258	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	259	if (is_mx7d())
382bee57	260	env_set("soc", "imx7d");
ec7fde3e	261	else
382bee57	262	env_set("soc", "imx7s");
ec7fde3e SA	263	#endif
	264
	265	return 0;
	266	}
	267	#endif
	268
c5752f73 AA	269	#ifdef CONFIG_SERIAL_TAG
	270	void get_board_serial(struct tag_serialnr *serialnr)
	271	{
	272	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	273	struct fuse_bank *bank = &ocotp->bank[0];
	274	struct fuse_bank0_regs *fuse =
	275	(struct fuse_bank0_regs *)bank->fuse_regs;
	276
	277	serialnr->low = fuse->tester0;
	278	serialnr->high = fuse->tester1;
	279	}
	280	#endif
	281
	282	#if defined(CONFIG_FEC_MXC)
	283	void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
	284	{
	285	struct ocotp_regs ocotp = (struct ocotp_regs )OCOTP_BASE_ADDR;
	286	struct fuse_bank *bank = &ocotp->bank[9];
	287	struct fuse_bank9_regs *fuse =
	288	(struct fuse_bank9_regs *)bank->fuse_regs;
	289
	290	if (0 == dev_id) {
	291	u32 value = readl(&fuse->mac_addr1);
	292	mac[0] = (value >> 8);
	293	mac[1] = value;
	294
	295	value = readl(&fuse->mac_addr0);
	296	mac[2] = value >> 24;
	297	mac[3] = value >> 16;
	298	mac[4] = value >> 8;
	299	mac[5] = value;
	300	} else {
	301	u32 value = readl(&fuse->mac_addr2);
	302	mac[0] = value >> 24;
	303	mac[1] = value >> 16;
	304	mac[2] = value >> 8;
	305	mac[3] = value;
	306
	307	value = readl(&fuse->mac_addr1);
	308	mac[4] = value >> 24;
	309	mac[5] = value >> 16;
	310	}
	311	}
	312	#endif
	313
83703a1c PF	314	#ifdef CONFIG_IMX_BOOTAUX
	315	int arch_auxiliary_core_up(u32 core_id, u32 boot_private_data)
	316	{
	317	u32 stack, pc;
	318	struct src src_reg = (struct src )SRC_BASE_ADDR;
	319
	320	if (!boot_private_data)
	321	return 1;
	322
	323	stack = (u32 )boot_private_data;
	324	pc = (u32 )(boot_private_data + 4);
	325
	326	/* Set the stack and pc to M4 bootROM */
	327	writel(stack, M4_BOOTROM_BASE_ADDR);
	328	writel(pc, M4_BOOTROM_BASE_ADDR + 4);
	329
	330	/* Enable M4 */
	331	clrsetbits_le32(&src_reg->m4rcr, SRC_M4RCR_M4C_NON_SCLR_RST_MASK,
	332	SRC_M4RCR_ENABLE_M4_MASK);
	333
	334	return 0;
	335	}
	336
	337	int arch_auxiliary_core_check_up(u32 core_id)
	338	{
	339	uint32_t val;
	340	struct src src_reg = (struct src )SRC_BASE_ADDR;
	341
	342	val = readl(&src_reg->m4rcr);
	343	if (val & 0x00000001)
	344	return 0; /* assert in reset */
	345
	346	return 1;
	347	}
	348	#endif
	349
c5752f73 AA	350	void set_wdog_reset(struct wdog_regs *wdog)
	351	{
	352	u32 reg = readw(&wdog->wcr);
	353	/*
	354	* Output WDOG_B signal to reset external pmic or POR_B decided by
	355	* the board desgin. Without external reset, the peripherals/DDR/
	356	* PMIC are not reset, that may cause system working abnormal.
	357	*/
	358	reg = readw(&wdog->wcr);
	359	reg \|= 1 << 3;
	360	/*
	361	* WDZST bit is write-once only bit. Align this bit in kernel,
	362	* otherwise kernel code will have no chance to set this bit.
	363	*/
	364	reg \|= 1 << 0;
	365	writew(reg, &wdog->wcr);
	366	}
	367
	368	/*
	369	* cfg_val will be used for
	370	* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
	371	* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
	372	* to SBMR1, which will determine the boot device.
	373	*/
	374	const struct boot_mode soc_boot_modes[] = {
	375	{"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
	376	{"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
	377	{"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
	378	{"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
	379
	380	{"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
	381	{"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
	382	/* 4 bit bus width */
	383	{"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
	384	{"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
	385	{"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
	386	{"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
	387	{"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
	388	{"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
	389	{NULL, 0},
	390	};
	391
	392	enum boot_device get_boot_device(void)
	393	{
	394	struct bootrom_sw_info **p =
	395	(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
	396
	397	enum boot_device boot_dev = SD1_BOOT;
	398	u8 boot_type = (*p)->boot_dev_type;
	399	u8 boot_instance = (*p)->boot_dev_instance;
	400
	401	switch (boot_type) {
	402	case BOOT_TYPE_SD:
	403	boot_dev = boot_instance + SD1_BOOT;
	404	break;
	405	case BOOT_TYPE_MMC:
	406	boot_dev = boot_instance + MMC1_BOOT;
	407	break;
	408	case BOOT_TYPE_NAND:
	409	boot_dev = NAND_BOOT;
	410	break;
	411	case BOOT_TYPE_QSPI:
	412	boot_dev = QSPI_BOOT;
	413	break;
414	case BOOT_TYPE_WEIM:
415	boot_dev = WEIM_NOR_BOOT;
416	break;
417	case BOOT_TYPE_SPINOR:
418	boot_dev = SPI_NOR_BOOT;
419	break;
420	default:
421	break;
422	}
423
424	return boot_dev;
425	}
426
62d8cce9 PF	427	#ifdef CONFIG_ENV_IS_IN_MMC
	428	__weak int board_mmc_get_env_dev(int devno)
	429	{
	430	return CONFIG_SYS_MMC_ENV_DEV;
	431	}
	432
	433	int mmc_get_env_dev(void)
	434	{
	435	struct bootrom_sw_info **p =
	436	(struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
	437	int devno = (*p)->boot_dev_instance;
	438	u8 boot_type = (*p)->boot_dev_type;
	439
	440	/* If not boot from sd/mmc, use default value */
	441	if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC))
	442	return CONFIG_SYS_MMC_ENV_DEV;
	443
	444	return board_mmc_get_env_dev(devno);
	445	}
	446	#endif
	447
c5752f73 AA	448	void s_init(void)
	449	{
	450	#if !defined CONFIG_SPL_BUILD
	451	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	452	asm volatile(
	453	"mrc p15, 0, r0, c1, c0, 1\n"
	454	"orr r0, r0, #1 << 6\n"
	455	"mcr p15, 0, r0, c1, c0, 1\n");
	456	#endif
	457	/* clock configuration. */
	458	clock_init();
	459
	460	return;
	461	}
9f8fa184 PF	462
	463	void reset_misc(void)
	464	{
	465	#ifdef CONFIG_VIDEO_MXS
	466	lcdif_power_down();
	467	#endif
	468	}
	469