projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 7865f4b0 MY |
1 | if ARCH_SOCFPGA |
| 2 | ||
| 77d2f7f5 SG |
3 | config SPL_LIBCOMMON_SUPPORT |
| 4 | default y | |
| 5 | ||
| 1646eba8 SG |
6 | config SPL_LIBDISK_SUPPORT |
| 7 | default y | |
| 8 | ||
| cc4288ef SG |
9 | config SPL_LIBGENERIC_SUPPORT |
| 10 | default y | |
| 11 | ||
| 1fdf7c64 SG |
12 | config SPL_MMC_SUPPORT |
| 13 | default y if DM_MMC | |
| 14 | ||
| d6b9bd89 SG |
15 | config SPL_NAND_SUPPORT |
| 16 | default y if SPL_NAND_DENALI | |
| 17 | ||
| e00f76ce SG |
18 | config SPL_SERIAL_SUPPORT |
| 19 | default y | |
| 20 | ||
| e404ade4 | 21 | config SPL_SPI_FLASH_SUPPORT |
| f35ed9ed SG |
22 | default y if SPL_SPI_SUPPORT |
| 23 | ||
| 24 | config SPL_SPI_SUPPORT | |
| e404ade4 SG |
25 | default y if DM_SPI |
| 26 | ||
| cd9b7317 MV |
27 | config TARGET_SOCFPGA_ARRIA5 |
| 28 | bool | |
| ed77aeb5 | 29 | select TARGET_SOCFPGA_GEN5 |
| cd9b7317 MV |
30 | |
| 31 | config TARGET_SOCFPGA_CYCLONE5 | |
| 32 | bool | |
| ed77aeb5 DN |
33 | select TARGET_SOCFPGA_GEN5 |
| 34 | ||
| 35 | config TARGET_SOCFPGA_GEN5 | |
| 36 | bool | |
| cd9b7317 | 37 | |
| 7865f4b0 MY |
38 | choice |
| 39 | prompt "Altera SOCFPGA board select" | |
| a26cd049 | 40 | optional |
| 7865f4b0 | 41 | |
| cd9b7317 MV |
42 | config TARGET_SOCFPGA_ARRIA5_SOCDK |
| 43 | bool "Altera SOCFPGA SoCDK (Arria V)" | |
| 44 | select TARGET_SOCFPGA_ARRIA5 | |
| 7865f4b0 | 45 | |
| cd9b7317 MV |
46 | config TARGET_SOCFPGA_CYCLONE5_SOCDK |
| 47 | bool "Altera SOCFPGA SoCDK (Cyclone V)" | |
| 48 | select TARGET_SOCFPGA_CYCLONE5 | |
| 7865f4b0 | 49 | |
| d88995a8 MV |
50 | config TARGET_SOCFPGA_DENX_MCVEVK |
| 51 | bool "DENX MCVEVK (Cyclone V)" | |
| 52 | select TARGET_SOCFPGA_CYCLONE5 | |
| 53 | ||
| 856b30da MV |
54 | config TARGET_SOCFPGA_EBV_SOCRATES |
| 55 | bool "EBV SoCrates (Cyclone V)" | |
| 56 | select TARGET_SOCFPGA_CYCLONE5 | |
| 57 | ||
| 35546f6f PM |
58 | config TARGET_SOCFPGA_IS1 |
| 59 | bool "IS1 (Cyclone V)" | |
| 60 | select TARGET_SOCFPGA_CYCLONE5 | |
| 61 | ||
| 569a191a MV |
62 | config TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 63 | bool "samtec VIN|ING FPGA (Cyclone V)" | |
| 64 | select TARGET_SOCFPGA_CYCLONE5 | |
| 65 | ||
| cf0a8dab MV |
66 | config TARGET_SOCFPGA_SR1500 |
| 67 | bool "SR1500 (Cyclone V)" | |
| 68 | select TARGET_SOCFPGA_CYCLONE5 | |
| 69 | ||
| 55c7a765 DN |
70 | config TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 71 | bool "Terasic DE0-Nano-Atlas (Cyclone V)" | |
| 72 | select TARGET_SOCFPGA_CYCLONE5 | |
| 73 | ||
| 952caa28 MV |
74 | config TARGET_SOCFPGA_TERASIC_SOCKIT |
| 75 | bool "Terasic SoCkit (Cyclone V)" | |
| 76 | select TARGET_SOCFPGA_CYCLONE5 | |
| 77 | ||
| 7865f4b0 MY |
78 | endchoice |
| 79 | ||
| 80 | config SYS_BOARD | |
| f0892401 MV |
81 | default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 82 | default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| 55c7a765 | 83 | default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 35546f6f | 84 | default "is1" if TARGET_SOCFPGA_IS1 |
| d88995a8 | 85 | default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
| 952caa28 | 86 | default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 856b30da | 87 | default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
| ae9996c8 | 88 | default "sr1500" if TARGET_SOCFPGA_SR1500 |
| 569a191a | 89 | default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 7865f4b0 MY |
90 | |
| 91 | config SYS_VENDOR | |
| cd9b7317 MV |
92 | default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 93 | default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| d88995a8 | 94 | default "denx" if TARGET_SOCFPGA_DENX_MCVEVK |
| 856b30da | 95 | default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES |
| 569a191a | 96 | default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 55c7a765 | 97 | default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 952caa28 | 98 | default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 7865f4b0 MY |
99 | |
| 100 | config SYS_SOC | |
| 101 | default "socfpga" | |
| 102 | ||
| 103 | config SYS_CONFIG_NAME | |
| 3cbc7b87 DN |
104 | default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK |
| 105 | default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK | |
| 55c7a765 | 106 | default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO |
| 35546f6f | 107 | default "socfpga_is1" if TARGET_SOCFPGA_IS1 |
| d88995a8 | 108 | default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK |
| 952caa28 | 109 | default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT |
| 856b30da | 110 | default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES |
| ae9996c8 | 111 | default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 |
| 569a191a | 112 | default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA |
| 7865f4b0 MY |
113 | |
| 114 | endif |