[people/ms/u-boot.git] / arch / powerpc / cpu / mpc512x / start.S

/*
 * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
 * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
 * Copyright Freescale Semiconductor, Inc. 2004, 2006.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Based on the MPC83xx code.
 */

/*
 *  U-Boot - Startup Code for MPC512x based Embedded Boards
 */

#include <asm-offsets.h>
#include <config.h>
#include <version.h>

#define CONFIG_521X	1		/* needed for Linux kernel header files*/

#include <asm/immap_512x.h>
#include "asm-offsets.h"

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/u-boot.h>

/*
 * Floating Point enable, Machine Check and Recoverable Interr.
 */
#undef	MSR_KERNEL
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif

/* Macros for manipulating CSx_START/STOP */
#define START_REG(start)	((start) >> 16)
#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)

/*
 * Set up GOT: Global Offset Table
 *
 * Use r12 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(__bss_end)
	GOT_ENTRY(__bss_start)
	END_GOT

/*
 * Magic number and version string
 */
	.long	0x27051956		/* U-Boot Magic Number */
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION_STRING, "\0"

/*
 * Vector Table
 */
	.text
	. = EXC_OFF_SYS_RESET

	.globl	_start
	/* Start from here after reset/power on */
_start:
	b	boot_cold

	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG(SRR0, SRR1)
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG(SRR0, SRR1)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
		MSR_KERNEL, COPY_EE)

/* Floating Point Unit unavailable exception */
	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

/* Decrementer */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)

/* Critical interrupt */
	STD_EXCEPTION(0xa00, Critical, UnknownException)

/* System Call */
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)

/* Trace interrupt */
	STD_EXCEPTION(0xd00, Trace, UnknownException)

/* Performance Monitor interrupt */
	STD_EXCEPTION(0xf00, PerfMon, UnknownException)

/* Intruction Translation Miss */
	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)

/* Data Load Translation Miss */
	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)

/* Data Store Translation Miss */
	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)

/* Instruction Address Breakpoint */
	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)

/* System Management interrupt */
	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)

	.globl	_end_of_vectors
_end_of_vectors:

	. = 0x3000
boot_cold:
	/* Save msr contents */
	mfmsr	r5

	/* Set IMMR area to our preferred location */
	lis	r4, CONFIG_DEFAULT_IMMR@h
	lis	r3, CONFIG_SYS_IMMR@h
	ori	r3, r3, CONFIG_SYS_IMMR@l
	stw	r3, IMMRBAR(r4)
	mtspr	MBAR, r3		/* IMMRBAR is mirrored into the MBAR SPR (311) */

	/* Initialise the machine */
	bl	cpu_early_init

	/*
	 * Set up Local Access Windows:
	 *
	 * 1) Boot/CS0 (boot FLASH)
	 * 2) On-chip SRAM (initial stack purposes)
	 */

	/* Boot CS/CS0 window range */
	lis     r3, CONFIG_SYS_IMMR@h
	ori     r3, r3, CONFIG_SYS_IMMR@l

	lis	r4, START_REG(CONFIG_SYS_FLASH_BASE)
	ori	r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
	stw	r4, LPCS0AW(r3)

	/*
	 * The SRAM window has a fixed size (256K), so only the start address
	 * is necessary
	 */
	lis	r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
	stw	r4, SRAMBAR(r3)

	/*
	 * According to MPC5121e RM, configuring local access windows should
	 * be followed by a dummy read of the config register that was
	 * modified last and an isync
	 */
	lwz	r4, SRAMBAR(r3)
	isync

	/*
	 * Set configuration of the Boot/CS0, the SRAM window does not have a
	 * config register so no params can be set for it
	 */
	lis     r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
	ori     r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l

	lis     r4, CONFIG_SYS_CS0_CFG@h
	ori     r4, r4, CONFIG_SYS_CS0_CFG@l
	stw     r4, CS0_CONFIG(r3)

	/* Master enable all CS's */
	lis	r4, CS_CTRL_ME@h
	ori	r4, r4, CS_CTRL_ME@l
	stw	r4, CS_CTRL(r3)

	lis	r4, (CONFIG_SYS_MONITOR_BASE)@h
	ori	r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
	addi	r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r5
	blr

in_flash:
	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
	ori	r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l

	li	r0, 0		/* Make room for stack frame header and	*/
	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/

	/* let the C-code set up the rest			*/
	/*							*/
	/* Be careful to keep code relocatable & stack humble	*/
	/*------------------------------------------------------*/

	GET_GOT			/* initialize GOT access	*/

	/* r3: IMMR */
	lis	r3, CONFIG_SYS_IMMR@h
	/* run low-level CPU init code (in Flash) */
	bl	cpu_init_f

	/* run 1st part of board init code (in Flash) */
	bl	board_init_f

	/* NOTREACHED - board_init_f() does not return */

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28		/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC			/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)	/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

/*
 * This code initialises the machine, it expects original MSR contents to be in r5.
 */
cpu_early_init:
	/* Initialize machine status; enable machine check interrupt */
	/*-----------------------------------------------------------*/

	li	r3, MSR_KERNEL			/* Set ME and RI flags */
	rlwimi	r3, r5, 0, 25, 25		/* preserve IP bit */
#ifdef DEBUG
	rlwimi	r3, r5, 0, 21, 22		/* debugger might set SE, BE bits */
#endif
	mtmsr	r3
	SYNC
	mtspr	SRR1, r3			/* Mirror current MSR state in SRR1 */

	lis	r3, CONFIG_SYS_IMMR@h

#if defined(CONFIG_WATCHDOG)
	/* Initialise the watchdog and reset it */
	/*--------------------------------------*/
	lis r4, CONFIG_SYS_WATCHDOG_VALUE
	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
	stw r4, SWCRR(r3)

	/* reset */
	li	r4, 0x556C
	sth	r4, SWSRR@l(r3)
	li	r4, 0x0
	ori	r4, r4, 0xAA39
	sth	r4, SWSRR@l(r3)
#else
	/* Disable the watchdog */
	/*----------------------*/
	lwz r4, SWCRR(r3)
	/*
	 * Check to see if it's enabled for disabling: once disabled by s/w
	 * it's not possible to re-enable it
	 */
	andi. r4, r4, 0x4
	beq 1f
	xor r4, r4, r4
	stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */

	/* Initialize the Hardware Implementation-dependent Registers */
	/* HID0 also contains cache control			*/
	/*------------------------------------------------------*/
	lis	r3, CONFIG_SYS_HID0_INIT@h
	ori	r3, r3, CONFIG_SYS_HID0_INIT@l
	SYNC
	mtspr	HID0, r3

	lis	r3, CONFIG_SYS_HID0_FINAL@h
	ori	r3, r3, CONFIG_SYS_HID0_FINAL@l
	SYNC
	mtspr	HID0, r3

	lis	r3, CONFIG_SYS_HID2@h
	ori	r3, r3, CONFIG_SYS_HID2@l
	SYNC
	mtspr	HID2, r3
	sync
	blr


/* Cache functions.
 *
 * Note: requires that all cache bits in
 * HID0 are in the low half word.
 */
	.globl	icache_enable
icache_enable:
	mfspr	r3, HID0
	ori	r3, r3, HID0_ICE
	lis	r4, 0
	ori	r4, r4, HID0_ILOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_ICFI
	isync
	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
	isync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	icache_disable
icache_disable:
	mfspr	r3, HID0
	lis	r4, 0
	ori	r4, r4, HID0_ICE|HID0_ILOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_ICFI
	isync
	mtspr	HID0, r4     /* sets invalidate, clears enable and lock*/
	isync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	icache_status
icache_status:
	mfspr	r3, HID0
	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
	blr

	.globl	dcache_enable
dcache_enable:
	mfspr	r3, HID0
	li	r5, HID0_DCFI|HID0_DLOCK
	andc	r3, r3, r5
	mtspr	HID0, r3		/* no invalidate, unlock */
	ori	r3, r3, HID0_DCE
	ori	r5, r3, HID0_DCFI
	mtspr	HID0, r5		/* enable + invalidate */
	mtspr	HID0, r3		/* enable */
	sync
	blr

	.globl	dcache_disable
dcache_disable:
	mfspr	r3, HID0
	lis	r4, 0
	ori	r4, r4, HID0_DCE|HID0_DLOCK
	andc	r3, r3, r4
	ori	r4, r3, HID0_DCI
	sync
	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
	sync
	mtspr	HID0, r3	/* clears invalidate */
	blr

	.globl	dcache_status
dcache_status:
	mfspr	r3, HID0
	rlwinm	r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
	blr

	.globl get_pvr
get_pvr:
	mfspr	r3, PVR
	blr

/*-------------------------------------------------------------------*/

/*
 * void relocate_code (addr_sp, gd, addr_moni)
 *
 * This "function" does not return, instead it continues in RAM
 * after relocating the monitor code.
 *
 * r3 = dest
 * r4 = src
 * r5 = length in bytes
 * r6 = cachelinesize
 */
	.globl	relocate_code
relocate_code:
	mr	r1,  r3		/* Set new stack pointer	*/
	mr	r9,  r4		/* Save copy of Global Data pointer */
	mr	r10, r5		/* Save copy of Destination Address */

	GET_GOT
	mr	r3,  r5				/* Destination Address */
	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address */
	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
	lwz	r5, GOT(__init_end)
	sub	r5, r5, r4
	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size */

	/*
	 * Fix GOT pointer:
	 *
	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
	 *		+ Destination Address
	 *
	 * Offset:
	 */
	sub	r15, r10, r4

	/* First our own GOT */
	add	r12, r12, r15
	/* then the one used by the C code */
	add	r30, r30, r15

	/*
	 * Now relocate code
	 */
	cmplw	cr1,r3,r4
	addi	r0,r5,3
	srwi.	r0,r0,2
	beq	cr1,4f		/* In place copy is not necessary */
	beq	7f		/* Protect against 0 count	  */
	mtctr	r0
	bge	cr1,2f
	la	r8,-4(r4)
	la	r7,-4(r3)

	/* copy */
1:	lwzu	r0,4(r8)
	stwu	r0,4(r7)
	bdnz	1b

	addi	r0,r5,3
	srwi.	r0,r0,2
	mtctr	r0
	la	r8,-4(r4)
	la	r7,-4(r3)

	/* and compare */
20:	lwzu	r20,4(r8)
	lwzu	r21,4(r7)
	xor. r22, r20, r21
	bne  30f
	bdnz	20b
	b 4f

	/* compare failed */
30:	li r3, 0
	blr

2:	slwi	r0,r0,2 /* re copy in reverse order ... y do we needed it? */
	add	r8,r4,r0
	add	r7,r3,r0
3:	lwzu	r0,-4(r8)
	stwu	r0,-4(r7)
	bdnz	3b

/*
 * Now flush the cache: note that we must start from a cache aligned
 * address. Otherwise we might miss one cache line.
 */
4:	cmpwi	r6,0
	add	r5,r3,r5
	beq	7f		/* Always flush prefetch queue in any case */
	subi	r0,r6,1
	andc	r3,r3,r0
	mr	r4,r3
5:	dcbst	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	5b
	sync			/* Wait for all dcbst to complete on bus */
	mr	r4,r3
6:	icbi	0,r4
	add	r4,r4,r6
	cmplw	r4,r5
	blt	6b
7:	sync			/* Wait for all icbi to complete on bus	*/
	isync

/*
 * We are done. Do not return, instead branch to second part of board
 * initialization, now running from RAM.
 */
	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
	mtlr	r0
	blr

in_ram:
	/*
	 * Relocation Function, r12 point to got2+0x8000
	 *
	 * Adjust got2 pointers, no need to check for 0, this code
	 * already puts a few entries in the table.
	 */
	li	r0,__got2_entries@sectoff@l
	la	r3,GOT(_GOT2_TABLE_)
	lwz	r11,GOT(_GOT2_TABLE_)
	mtctr	r0
	sub	r11,r3,r11
	addi	r3,r3,-4
1:	lwzu	r0,4(r3)
	cmpwi	r0,0
	beq-	2f
	add	r0,r0,r11
	stw	r0,0(r3)
2:	bdnz	1b

	/*
	 * Now adjust the fixups and the pointers to the fixups
	 * in case we need to move ourselves again.
	 */
	li	r0,__fixup_entries@sectoff@l
	lwz	r3,GOT(_FIXUP_TABLE_)
	cmpwi	r0,0
	mtctr	r0
	addi	r3,r3,-4
	beq	4f
3:	lwzu	r4,4(r3)
	lwzux	r0,r4,r11
	cmpwi	r0,0
	add	r0,r0,r11
	stw	r4,0(r3)
	beq-	5f
	stw	r0,0(r4)
5:	bdnz	3b
4:
clear_bss:
	/*
	 * Now clear BSS segment
	 */
	lwz	r3,GOT(__bss_start)
	lwz	r4,GOT(__bss_end)

	cmplw	0, r3, r4
	beq	6f

	li	r0, 0
5:
	stw	r0, 0(r3)
	addi	r3, r3, 4
	cmplw	0, r3, r4
	bne	5b
6:
	mr	r3, r9		/* Global Data pointer		*/
	mr	r4, r10		/* Destination Address		*/
	bl	board_init_r

	/*
	 * Copy exception vector code to low memory
	 *
	 * r3: dest_addr
	 * r7: source address, r8: end address, r9: target address
	 */
	.globl	trap_init
trap_init:
	mflr	r4		/* save link register */
	GET_GOT
	lwz	r7, GOT(_start)
	lwz	r8, GOT(_end_of_vectors)

	li	r9, 0x100	/* reset vector at 0x100 */

	cmplw	0, r7, r8
	bgelr			/* return if r7>=r8 - just in case */
1:
	lwz	r0, 0(r7)
	stw	r0, 0(r9)
	addi	r7, r7, 4
	addi	r9, r9, 4
	cmplw	0, r7, r8
	bne	1b

	/*
	 * relocate `hdlr' and `int_return' entries
	 */
	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
2:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	2b

	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	bl	trap_reloc

	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
3:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	3b

	li	r7, .L_Trace - _start + EXC_OFF_SYS_RESET
	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
4:
	bl	trap_reloc
	addi	r7, r7, 0x100		/* next exception vector */
	cmplw	0, r7, r8
	blt	4b

	mfmsr	r3			/* now that the vectors have */
	lis	r7, MSR_IP@h		/* relocated into low memory */
	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off */
	andc	r3, r3, r7		/* (if it was on) */
	SYNC				/* Some chip revs need this... */
	mtmsr	r3
	SYNC

	mtlr	r4			/* restore link register    */
	blr
Commit	Line	Data
8993e54b RJ	1	/*
	2	* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
	3	* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
3b74e7ec	4	* Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
4c2e3da8	5	* Copyright Freescale Semiconductor, Inc. 2004, 2006.
8993e54b	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
8993e54b RJ	8	*
	9	* Based on the MPC83xx code.
	10	*/
	11
	12	/*
	13	* U-Boot - Startup Code for MPC512x based Embedded Boards
	14	*/
	15
25ddd1fb	16	#include <asm-offsets.h>
8993e54b	17	#include <config.h>
8993e54b RJ	18	#include <version.h>
	19
	20	#define CONFIG_521X 1 /* needed for Linux kernel header files*/
	21
3b74e7ec WD	22	#include <asm/immap_512x.h>
	23	#include "asm-offsets.h"
	24
8993e54b RJ	25	#include <ppc_asm.tmpl>
	26	#include <ppc_defs.h>
	27
	28	#include <asm/cache.h>
	29	#include <asm/mmu.h>
d98b0523	30	#include <asm/u-boot.h>
8993e54b	31
8993e54b RJ	32	/*
	33	* Floating Point enable, Machine Check and Recoverable Interr.
	34	*/
	35	#undef MSR_KERNEL
	36	#ifdef DEBUG
	37	#define MSR_KERNEL (MSR_FP\|MSR_RI)
	38	#else
	39	#define MSR_KERNEL (MSR_FP\|MSR_ME\|MSR_RI)
	40	#endif
	41
	42	/* Macros for manipulating CSx_START/STOP */
	43	#define START_REG(start) ((start) >> 16)
	44	#define STOP_REG(start, size) (((start) + (size) - 1) >> 16)
	45
	46	/*
	47	* Set up GOT: Global Offset Table
	48	*
0f8aa159	49	* Use r12 to access the GOT
8993e54b RJ	50	*/
	51	START_GOT
	52	GOT_ENTRY(_GOT2_TABLE_)
	53	GOT_ENTRY(_FIXUP_TABLE_)
	54
	55	GOT_ENTRY(_start)
	56	GOT_ENTRY(_start_of_vectors)
	57	GOT_ENTRY(_end_of_vectors)
	58	GOT_ENTRY(transfer_to_handler)
	59
	60	GOT_ENTRY(__init_end)
3929fb0a	61	GOT_ENTRY(__bss_end)
8993e54b RJ	62	GOT_ENTRY(__bss_start)
	63	END_GOT
	64
	65	/*
	66	* Magic number and version string
	67	*/
	68	.long 0x27051956 /* U-Boot Magic Number */
	69	.globl version_string
	70	version_string:
09c2e90c	71	.ascii U_BOOT_VERSION_STRING, "\0"
8993e54b RJ	72
	73	/*
	74	* Vector Table
	75	*/
	76	.text
	77	. = EXC_OFF_SYS_RESET
	78
	79	.globl _start
	80	/* Start from here after reset/power on */
	81	_start:
8993e54b RJ	82	b boot_cold
	83
	84	.globl _start_of_vectors
	85	_start_of_vectors:
	86
	87	/* Machine check */
	88	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
	89
	90	/* Data Storage exception. */
	91	STD_EXCEPTION(0x300, DataStorage, UnknownException)
	92
	93	/* Instruction Storage exception. */
	94	STD_EXCEPTION(0x400, InstStorage, UnknownException)
	95
	96	/* External Interrupt exception. */
	97	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
	98
	99	/* Alignment exception. */
	100	. = 0x600
	101	Alignment:
	102	EXCEPTION_PROLOG(SRR0, SRR1)
	103	mfspr r4,DAR
	104	stw r4,_DAR(r21)
	105	mfspr r5,DSISR
	106	stw r5,_DSISR(r21)
	107	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887	108	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
8993e54b RJ	109
	110	/* Program check exception */
	111	. = 0x700
	112	ProgramCheck:
	113	EXCEPTION_PROLOG(SRR0, SRR1)
	114	addi r3,r1,STACK_FRAME_OVERHEAD
fc4e1887 JT	115	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
fc4e1887 JT	116	MSR_KERNEL, COPY_EE)
8993e54b RJ	117
	118	/* Floating Point Unit unavailable exception */
	119	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
	120
	121	/* Decrementer */
	122	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
	123
	124	/* Critical interrupt */
	125	STD_EXCEPTION(0xa00, Critical, UnknownException)
	126
	127	/* System Call */
	128	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
	129
	130	/* Trace interrupt */
	131	STD_EXCEPTION(0xd00, Trace, UnknownException)
	132
	133	/* Performance Monitor interrupt */
	134	STD_EXCEPTION(0xf00, PerfMon, UnknownException)
	135
	136	/* Intruction Translation Miss */
	137	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
	138
	139	/* Data Load Translation Miss */
	140	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
	141
	142	/* Data Store Translation Miss */
	143	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
	144
	145	/* Instruction Address Breakpoint */
	146	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
	147
	148	/* System Management interrupt */
	149	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
	150
	151	.globl _end_of_vectors
	152	_end_of_vectors:
	153
	154	. = 0x3000
	155	boot_cold:
	156	/* Save msr contents */
	157	mfmsr r5
	158
	159	/* Set IMMR area to our preferred location */
	160	lis r4, CONFIG_DEFAULT_IMMR@h
6d0f6bcf JCPV	161	lis r3, CONFIG_SYS_IMMR@h
6d0f6bcf JCPV	162	ori r3, r3, CONFIG_SYS_IMMR@l
8993e54b RJ	163	stw r3, IMMRBAR(r4)
	164	mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */
	165
	166	/* Initialise the machine */
	167	bl cpu_early_init
	168
	169	/*
	170	* Set up Local Access Windows:
	171	*
	172	* 1) Boot/CS0 (boot FLASH)
	173	* 2) On-chip SRAM (initial stack purposes)
	174	*/
	175
	176	/* Boot CS/CS0 window range */
6d0f6bcf JCPV	177	lis r3, CONFIG_SYS_IMMR@h
6d0f6bcf JCPV	178	ori r3, r3, CONFIG_SYS_IMMR@l
8993e54b	179
6d0f6bcf JCPV	180	lis r4, START_REG(CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	181	ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
8993e54b RJ	182	stw r4, LPCS0AW(r3)
	183
	184	/*
	185	* The SRAM window has a fixed size (256K), so only the start address
	186	* is necessary
	187	*/
6d0f6bcf	188	lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
8993e54b RJ	189	stw r4, SRAMBAR(r3)
8993e54b RJ	190
b1b54e35	191	/*
8993e54b	192	* According to MPC5121e RM, configuring local access windows should
b1b54e35	193	* be followed by a dummy read of the config register that was
8993e54b	194	* modified last and an isync
b1b54e35	195	*/
8993e54b RJ	196	lwz r4, SRAMBAR(r3)
	197	isync
	198
	199	/*
	200	* Set configuration of the Boot/CS0, the SRAM window does not have a
	201	* config register so no params can be set for it
	202	*/
6d0f6bcf JCPV	203	lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
6d0f6bcf JCPV	204	ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
8993e54b	205
6d0f6bcf JCPV	206	lis r4, CONFIG_SYS_CS0_CFG@h
6d0f6bcf JCPV	207	ori r4, r4, CONFIG_SYS_CS0_CFG@l
b1b54e35	208	stw r4, CS0_CONFIG(r3)
8993e54b RJ	209
	210	/* Master enable all CS's */
	211	lis r4, CS_CTRL_ME@h
	212	ori r4, r4, CS_CTRL_ME@l
	213	stw r4, CS_CTRL(r3)
	214
6d0f6bcf JCPV	215	lis r4, (CONFIG_SYS_MONITOR_BASE)@h
6d0f6bcf JCPV	216	ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
8993e54b RJ	217	addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
	218	mtlr r5
	219	blr
	220
	221	in_flash:
6d0f6bcf JCPV	222	lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
6d0f6bcf JCPV	223	ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
8993e54b RJ	224
	225	li r0, 0 /* Make room for stack frame header and */
	226	stwu r0, -4(r1) /* clear final stack frame so that */
	227	stwu r0, -4(r1) /* stack backtraces terminate cleanly */
	228
	229	/* let the C-code set up the rest */
	230	/* */
	231	/* Be careful to keep code relocatable & stack humble */
	232	/------------------------------------------------------/
	233
	234	GET_GOT /* initialize GOT access */
8c4734e9	235
8993e54b	236	/* r3: IMMR */
6d0f6bcf	237	lis r3, CONFIG_SYS_IMMR@h
8993e54b RJ	238	/* run low-level CPU init code (in Flash) */
	239	bl cpu_init_f
	240
8993e54b RJ	241	/* run 1st part of board init code (in Flash) */
	242	bl board_init_f
	243
	244	/* NOTREACHED - board_init_f() does not return */
	245
	246	/*
	247	* This code finishes saving the registers to the exception frame
	248	* and jumps to the appropriate handler for the exception.
	249	* Register r21 is pointer into trap frame, r1 has new stack pointer.
	250	*/
	251	.globl transfer_to_handler
	252	transfer_to_handler:
	253	stw r22,_NIP(r21)
	254	lis r22,MSR_POW@h
	255	andc r23,r23,r22
	256	stw r23,_MSR(r21)
	257	SAVE_GPR(7, r21)
	258	SAVE_4GPRS(8, r21)
	259	SAVE_8GPRS(12, r21)
	260	SAVE_8GPRS(24, r21)
	261	mflr r23
	262	andi. r24,r23,0x3f00 /* get vector offset */
	263	stw r24,TRAP(r21)
	264	li r22,0
	265	stw r22,RESULT(r21)
	266	lwz r24,0(r23) /* virtual address of handler */
	267	lwz r23,4(r23) /* where to go when done */
	268	mtspr SRR0,r24
	269	mtspr SRR1,r20
	270	mtlr r23
	271	SYNC
	272	rfi /* jump to handler, enable MMU */
	273
	274	int_return:
	275	mfmsr r28 /* Disable interrupts */
	276	li r4,0
	277	ori r4,r4,MSR_EE
	278	andc r28,r28,r4
	279	SYNC /* Some chip revs need this... */
	280	mtmsr r28
	281	SYNC
	282	lwz r2,_CTR(r1)
	283	lwz r0,_LINK(r1)
	284	mtctr r2
	285	mtlr r0
	286	lwz r2,_XER(r1)
	287	lwz r0,_CCR(r1)
	288	mtspr XER,r2
	289	mtcrf 0xFF,r0
	290	REST_10GPRS(3, r1)
	291	REST_10GPRS(13, r1)
	292	REST_8GPRS(23, r1)
	293	REST_GPR(31, r1)
	294	lwz r2,_NIP(r1) /* Restore environment */
	295	lwz r0,_MSR(r1)
	296	mtspr SRR0,r2
	297	mtspr SRR1,r0
	298	lwz r0,GPR0(r1)
	299	lwz r2,GPR2(r1)
	300	lwz r1,GPR1(r1)
	301	SYNC
	302	rfi
	303
	304	/*
305	* This code initialises the machine, it expects original MSR contents to be in r5.
306	*/
307	cpu_early_init:
308	/* Initialize machine status; enable machine check interrupt */
309	/-----------------------------------------------------------/
310
311	li r3, MSR_KERNEL /* Set ME and RI flags */
312	rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */
313	#ifdef DEBUG
314	rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */
315	#endif
316	mtmsr r3
317	SYNC
318	mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */
319
6d0f6bcf	320	lis r3, CONFIG_SYS_IMMR@h
8993e54b RJ	321
	322	#if defined(CONFIG_WATCHDOG)
	323	/* Initialise the watchdog and reset it */
	324	/--------------------------------------/
6d0f6bcf	325	lis r4, CONFIG_SYS_WATCHDOG_VALUE
8993e54b RJ	326	ori r4, r4, (SWCRR_SWEN \| SWCRR_SWRI \| SWCRR_SWPR)
	327	stw r4, SWCRR(r3)
	328
	329	/* reset */
	330	li r4, 0x556C
	331	sth r4, SWSRR@l(r3)
	332	li r4, 0x0
	333	ori r4, r4, 0xAA39
	334	sth r4, SWSRR@l(r3)
	335	#else
	336	/* Disable the watchdog */
	337	/----------------------/
	338	lwz r4, SWCRR(r3)
	339	/*
	340	* Check to see if it's enabled for disabling: once disabled by s/w
	341	* it's not possible to re-enable it
	342	*/
	343	andi. r4, r4, 0x4
	344	beq 1f
	345	xor r4, r4, r4
	346	stw r4, SWCRR(r3)
	347	1:
	348	#endif /* CONFIG_WATCHDOG */
	349
	350	/* Initialize the Hardware Implementation-dependent Registers */
	351	/* HID0 also contains cache control */
	352	/------------------------------------------------------/
6d0f6bcf JCPV	353	lis r3, CONFIG_SYS_HID0_INIT@h
6d0f6bcf JCPV	354	ori r3, r3, CONFIG_SYS_HID0_INIT@l
8993e54b RJ	355	SYNC
	356	mtspr HID0, r3
	357
6d0f6bcf JCPV	358	lis r3, CONFIG_SYS_HID0_FINAL@h
6d0f6bcf JCPV	359	ori r3, r3, CONFIG_SYS_HID0_FINAL@l
8993e54b RJ	360	SYNC
	361	mtspr HID0, r3
	362
6d0f6bcf JCPV	363	lis r3, CONFIG_SYS_HID2@h
6d0f6bcf JCPV	364	ori r3, r3, CONFIG_SYS_HID2@l
8993e54b RJ	365	SYNC
	366	mtspr HID2, r3
	367	sync
	368	blr
	369
	370
	371	/* Cache functions.
	372	*
	373	* Note: requires that all cache bits in
	374	* HID0 are in the low half word.
	375	*/
	376	.globl icache_enable
	377	icache_enable:
	378	mfspr r3, HID0
	379	ori r3, r3, HID0_ICE
	380	lis r4, 0
	381	ori r4, r4, HID0_ILOCK
	382	andc r3, r3, r4
	383	ori r4, r3, HID0_ICFI
	384	isync
	385	mtspr HID0, r4 /* sets enable and invalidate, clears lock */
	386	isync
	387	mtspr HID0, r3 /* clears invalidate */
	388	blr
	389
	390	.globl icache_disable
	391	icache_disable:
	392	mfspr r3, HID0
	393	lis r4, 0
	394	ori r4, r4, HID0_ICE\|HID0_ILOCK
	395	andc r3, r3, r4
	396	ori r4, r3, HID0_ICFI
	397	isync
	398	mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
	399	isync
	400	mtspr HID0, r3 /* clears invalidate */
	401	blr
	402
	403	.globl icache_status
	404	icache_status:
	405	mfspr r3, HID0
	406	rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
	407	blr
	408
	409	.globl dcache_enable
	410	dcache_enable:
	411	mfspr r3, HID0
	412	li r5, HID0_DCFI\|HID0_DLOCK
	413	andc r3, r3, r5
	414	mtspr HID0, r3 /* no invalidate, unlock */
	415	ori r3, r3, HID0_DCE
	416	ori r5, r3, HID0_DCFI
	417	mtspr HID0, r5 /* enable + invalidate */
	418	mtspr HID0, r3 /* enable */
	419	sync
	420	blr
	421
	422	.globl dcache_disable
	423	dcache_disable:
	424	mfspr r3, HID0
	425	lis r4, 0
	426	ori r4, r4, HID0_DCE\|HID0_DLOCK
	427	andc r3, r3, r4
	428	ori r4, r3, HID0_DCI
429	sync
430	mtspr HID0, r4 /* sets invalidate, clears enable and lock */
431	sync
432	mtspr HID0, r3 /* clears invalidate */
433	blr
434
435	.globl dcache_status
436	dcache_status:
437	mfspr r3, HID0
438	rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
439	blr
440
441	.globl get_pvr
442	get_pvr:
443	mfspr r3, PVR
444	blr
445
8993e54b RJ	446	/-------------------------------------------------------------------/
	447
	448	/*
	449	* void relocate_code (addr_sp, gd, addr_moni)
	450	*
	451	* This "function" does not return, instead it continues in RAM
	452	* after relocating the monitor code.
	453	*
	454	* r3 = dest
	455	* r4 = src
	456	* r5 = length in bytes
	457	* r6 = cachelinesize
	458	*/
	459	.globl relocate_code
	460	relocate_code:
	461	mr r1, r3 /* Set new stack pointer */
	462	mr r9, r4 /* Save copy of Global Data pointer */
	463	mr r10, r5 /* Save copy of Destination Address */
	464
0f8aa159	465	GET_GOT
8993e54b	466	mr r3, r5 /* Destination Address */
6d0f6bcf JCPV	467	lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
6d0f6bcf JCPV	468	ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
8993e54b RJ	469	lwz r5, GOT(__init_end)
8993e54b RJ	470	sub r5, r5, r4
6d0f6bcf	471	li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
8993e54b RJ	472
	473	/*
	474	* Fix GOT pointer:
	475	*
6d0f6bcf	476	* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
8993e54b RJ	477	* + Destination Address
	478	*
	479	* Offset:
	480	*/
	481	sub r15, r10, r4
	482
	483	/* First our own GOT */
0f8aa159	484	add r12, r12, r15
8993e54b RJ	485	/* then the one used by the C code */
	486	add r30, r30, r15
	487
	488	/*
	489	* Now relocate code
	490	*/
	491	cmplw cr1,r3,r4
	492	addi r0,r5,3
	493	srwi. r0,r0,2
	494	beq cr1,4f /* In place copy is not necessary */
	495	beq 7f /* Protect against 0 count */
	496	mtctr r0
	497	bge cr1,2f
	498	la r8,-4(r4)
	499	la r7,-4(r3)
	500
	501	/* copy */
	502	1: lwzu r0,4(r8)
	503	stwu r0,4(r7)
	504	bdnz 1b
	505
	506	addi r0,r5,3
	507	srwi. r0,r0,2
	508	mtctr r0
	509	la r8,-4(r4)
	510	la r7,-4(r3)
	511
	512	/* and compare */
	513	20: lwzu r20,4(r8)
	514	lwzu r21,4(r7)
	515	xor. r22, r20, r21
	516	bne 30f
	517	bdnz 20b
	518	b 4f
	519
	520	/* compare failed */
	521	30: li r3, 0
	522	blr
	523
	524	2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
	525	add r8,r4,r0
	526	add r7,r3,r0
	527	3: lwzu r0,-4(r8)
	528	stwu r0,-4(r7)
	529	bdnz 3b
	530
	531	/*
	532	* Now flush the cache: note that we must start from a cache aligned
	533	* address. Otherwise we might miss one cache line.
	534	*/
	535	4: cmpwi r6,0
	536	add r5,r3,r5
	537	beq 7f /* Always flush prefetch queue in any case */
	538	subi r0,r6,1
	539	andc r3,r3,r0
	540	mr r4,r3
	541	5: dcbst 0,r4
	542	add r4,r4,r6
	543	cmplw r4,r5
	544	blt 5b
	545	sync /* Wait for all dcbst to complete on bus */
	546	mr r4,r3
	547	6: icbi 0,r4
	548	add r4,r4,r6
549	cmplw r4,r5
550	blt 6b
551	7: sync /* Wait for all icbi to complete on bus */
552	isync
553
554	/*
555	* We are done. Do not return, instead branch to second part of board
556	* initialization, now running from RAM.
557	*/
558	addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
559	mtlr r0
560	blr
561
562	in_ram:
563	/*
0f8aa159	564	* Relocation Function, r12 point to got2+0x8000
8993e54b RJ	565	*
	566	* Adjust got2 pointers, no need to check for 0, this code
	567	* already puts a few entries in the table.
	568	*/
	569	li r0,__got2_entries@sectoff@l
	570	la r3,GOT(_GOT2_TABLE_)
	571	lwz r11,GOT(_GOT2_TABLE_)
	572	mtctr r0
	573	sub r11,r3,r11
	574	addi r3,r3,-4
	575	1: lwzu r0,4(r3)
afc3ba0f JT	576	cmpwi r0,0
afc3ba0f JT	577	beq- 2f
8993e54b RJ	578	add r0,r0,r11
8993e54b RJ	579	stw r0,0(r3)
afc3ba0f	580	2: bdnz 1b
8993e54b RJ	581
	582	/*
	583	* Now adjust the fixups and the pointers to the fixups
	584	* in case we need to move ourselves again.
	585	*/
afc3ba0f	586	li r0,__fixup_entries@sectoff@l
8993e54b RJ	587	lwz r3,GOT(_FIXUP_TABLE_)
	588	cmpwi r0,0
	589	mtctr r0
	590	addi r3,r3,-4
	591	beq 4f
	592	3: lwzu r4,4(r3)
	593	lwzux r0,r4,r11
d1e0b10a	594	cmpwi r0,0
8993e54b	595	add r0,r0,r11
34bbf618	596	stw r4,0(r3)
d1e0b10a	597	beq- 5f
8993e54b	598	stw r0,0(r4)
d1e0b10a	599	5: bdnz 3b
8993e54b RJ	600	4:
	601	clear_bss:
	602	/*
	603	* Now clear BSS segment
	604	*/
	605	lwz r3,GOT(__bss_start)
3929fb0a	606	lwz r4,GOT(__bss_end)
8993e54b RJ	607
	608	cmplw 0, r3, r4
	609	beq 6f
	610
	611	li r0, 0
	612	5:
	613	stw r0, 0(r3)
	614	addi r3, r3, 4
	615	cmplw 0, r3, r4
	616	bne 5b
	617	6:
	618	mr r3, r9 /* Global Data pointer */
	619	mr r4, r10 /* Destination Address */
	620	bl board_init_r
	621
	622	/*
	623	* Copy exception vector code to low memory
	624	*
	625	* r3: dest_addr
	626	* r7: source address, r8: end address, r9: target address
	627	*/
	628	.globl trap_init
	629	trap_init:
0f8aa159 JT	630	mflr r4 /* save link register */
0f8aa159 JT	631	GET_GOT
8993e54b RJ	632	lwz r7, GOT(_start)
	633	lwz r8, GOT(_end_of_vectors)
	634
	635	li r9, 0x100 /* reset vector at 0x100 */
	636
	637	cmplw 0, r7, r8
	638	bgelr /* return if r7>=r8 - just in case */
8993e54b RJ	639	1:
	640	lwz r0, 0(r7)
	641	stw r0, 0(r9)
	642	addi r7, r7, 4
	643	addi r9, r9, 4
	644	cmplw 0, r7, r8
	645	bne 1b
	646
	647	/*
	648	* relocate `hdlr' and `int_return' entries
	649	*/
	650	li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
	651	li r8, Alignment - _start + EXC_OFF_SYS_RESET
	652	2:
	653	bl trap_reloc
	654	addi r7, r7, 0x100 /* next exception vector */
	655	cmplw 0, r7, r8
	656	blt 2b
	657
	658	li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
	659	bl trap_reloc
	660
	661	li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
	662	bl trap_reloc
	663
	664	li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
	665	li r8, SystemCall - _start + EXC_OFF_SYS_RESET
	666	3:
	667	bl trap_reloc
	668	addi r7, r7, 0x100 /* next exception vector */
	669	cmplw 0, r7, r8
	670	blt 3b
	671
	672	li r7, .L_Trace - _start + EXC_OFF_SYS_RESET
	673	li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
	674	4:
	675	bl trap_reloc
	676	addi r7, r7, 0x100 /* next exception vector */
	677	cmplw 0, r7, r8
	678	blt 4b
	679
	680	mfmsr r3 /* now that the vectors have */
	681	lis r7, MSR_IP@h /* relocated into low memory */
	682	ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
	683	andc r3, r3, r7 /* (if it was on) */
	684	SYNC /* Some chip revs need this... */
	685	mtmsr r3
	686	SYNC
	687
	688	mtlr r4 /* restore link register */
	689	blr