[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c

/*
 * Copyright 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Modified by Xianghua Xiao, X.Xiao@motorola.com
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <ioports.h>
#include <sata.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include "mp.h"

DECLARE_GLOBAL_DATA_PTR;

extern void srio_init(void);

#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
				int open_drain, int assign);
extern void qe_init(uint qe_base);
extern void qe_reset(void);

static void config_qe_ioports(void)
{
	u8      port, pin;
	int     dir, open_drain, assign;
	int     i;

	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
		port		= qe_iop_conf_tab[i].port;
		pin		= qe_iop_conf_tab[i].pin;
		dir		= qe_iop_conf_tab[i].dir;
		open_drain	= qe_iop_conf_tab[i].open_drain;
		assign		= qe_iop_conf_tab[i].assign;
		qe_config_iopin(port, pin, dir, open_drain, assign);
	}
}
#endif

#ifdef CONFIG_CPM2
void config_8560_ioports (volatile ccsr_cpm_t * cpm)
{
	int portnum;

	for (portnum = 0; portnum < 4; portnum++) {
		uint pmsk = 0,
		     ppar = 0,
		     psor = 0,
		     pdir = 0,
		     podr = 0,
		     pdat = 0;
		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
		iop_conf_t *eiopc = iopc + 32;
		uint msk = 1;

		/*
		 * NOTE:
		 * index 0 refers to pin 31,
		 * index 31 refers to pin 0
		 */
		while (iopc < eiopc) {
			if (iopc->conf) {
				pmsk |= msk;
				if (iopc->ppar)
					ppar |= msk;
				if (iopc->psor)
					psor |= msk;
				if (iopc->pdir)
					pdir |= msk;
				if (iopc->podr)
					podr |= msk;
				if (iopc->pdat)
					pdat |= msk;
			}

			msk <<= 1;
			iopc++;
		}

		if (pmsk != 0) {
			volatile ioport_t *iop = ioport_addr (cpm, portnum);
			uint tpmsk = ~pmsk;

			/*
			 * the (somewhat confused) paragraph at the
			 * bottom of page 35-5 warns that there might
			 * be "unknown behaviour" when programming
			 * PSORx and PDIRx, if PPARx = 1, so I
			 * decided this meant I had to disable the
			 * dedicated function first, and enable it
			 * last.
			 */
			iop->ppar &= tpmsk;
			iop->psor = (iop->psor & tpmsk) | psor;
			iop->podr = (iop->podr & tpmsk) | podr;
			iop->pdat = (iop->pdat & tpmsk) | pdat;
			iop->pdir = (iop->pdir & tpmsk) | pdir;
			iop->ppar |= ppar;
		}
	}
}
#endif

#ifdef CONFIG_SYS_FSL_CPC
static void enable_cpc(void)
{
	int i;
	u32 size = 0;

	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
		size += CPC_CFG0_SZ_K(cpccfg0);

#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
#endif

		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
		/* Read back to sync write */
		in_be32(&cpc->cpccsr0);

	}

	printf("Corenet Platform Cache: %d KB enabled\n", size);
}

void invalidate_cpc(void)
{
	int i;
	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;

	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
		/* Flash invalidate the CPC and clear all the locks */
		out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
		while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
			;
	}
}
#else
#define enable_cpc()
#define invalidate_cpc()
#endif /* CONFIG_SYS_FSL_CPC */

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map
 * initialize a bunch of registers
 */

#ifdef CONFIG_FSL_CORENET
static void corenet_tb_init(void)
{
	volatile ccsr_rcpm_t *rcpm =
		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
	volatile ccsr_pic_t *pic =
		(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
	u32 whoami = in_be32(&pic->whoami);

	/* Enable the timebase register for this core */
	out_be32(&rcpm->ctbenrl, (1 << whoami));
}
#endif

void cpu_init_f (void)
{
	extern void m8560_cpm_reset (void);
#ifdef CONFIG_MPC8548
	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	uint svr = get_svr();

	/*
	 * CPU2 errata workaround: A core hang possible while executing
	 * a msync instruction and a snoopable transaction from an I/O
	 * master tagged to make quick forward progress is present.
	 * Fixed in silicon rev 2.1.
	 */
	if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
		out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
#endif

	disable_tlb(14);
	disable_tlb(15);

#ifdef CONFIG_CPM2
	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif

       init_early_memctl_regs();

#if defined(CONFIG_CPM2)
	m8560_cpm_reset();
#endif
#ifdef CONFIG_QE
	/* Config QE ioports */
	config_qe_ioports();
#endif
#if defined(CONFIG_FSL_DMA)
	dma_init();
#endif
#ifdef CONFIG_FSL_CORENET
	corenet_tb_init();
#endif
	init_used_tlb_cams();

	/* Invalidate the CPC before DDR gets enabled */
	invalidate_cpc();
}

/* Implement a dummy function for those platforms w/o SERDES */
static void __fsl_serdes__init(void)
{
	return ;
}
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);

/*
 * Initialize L2 as cache.
 *
 * The newer 8548, etc, parts have twice as much cache, but
 * use the same bit-encoding as the older 8555, etc, parts.
 *
 */
int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
#endif

#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
	flush_dcache();
	mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
	sync();
#endif

	puts ("L2:    ");

#if defined(CONFIG_L2_CACHE)
	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
	volatile uint cache_ctl;
	uint svr, ver;
	uint l2srbar;
	u32 l2siz_field;

	svr = get_svr();
	ver = SVR_SOC_VER(svr);

	asm("msync;isync");
	cache_ctl = l2cache->l2ctl;

#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	if (cache_ctl & MPC85xx_L2CTL_L2E) {
		/* Clear L2 SRAM memory-mapped base address */
		out_be32(&l2cache->l2srbar0, 0x0);
		out_be32(&l2cache->l2srbar1, 0x0);

		/* set MBECCDIS=0, SBECCDIS=0 */
		clrbits_be32(&l2cache->l2errdis,
				(MPC85xx_L2ERRDIS_MBECC |
				 MPC85xx_L2ERRDIS_SBECC));

		/* set L2E=0, L2SRAM=0 */
		clrbits_be32(&l2cache->l2ctl,
				(MPC85xx_L2CTL_L2E |
				 MPC85xx_L2CTL_L2SRAM_ENTIRE));
	}
#endif

	l2siz_field = (cache_ctl >> 28) & 0x3;

	switch (l2siz_field) {
	case 0x0:
		printf(" unknown size (0x%08x)\n", cache_ctl);
		return -1;
		break;
	case 0x1:
		if (ver == SVR_8540 || ver == SVR_8560   ||
		    ver == SVR_8541 || ver == SVR_8541_E ||
		    ver == SVR_8555 || ver == SVR_8555_E) {
			puts("128 KB ");
			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
			cache_ctl = 0xc4000000;
		} else {
			puts("256 KB ");
			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
		}
		break;
	case 0x2:
		if (ver == SVR_8540 || ver == SVR_8560   ||
		    ver == SVR_8541 || ver == SVR_8541_E ||
		    ver == SVR_8555 || ver == SVR_8555_E) {
			puts("256 KB ");
			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
			cache_ctl = 0xc8000000;
		} else {
			puts ("512 KB ");
			/* set L2E=1, L2I=1, & L2SRAM=0 */
			cache_ctl = 0xc0000000;
		}
		break;
	case 0x3:
		puts("1024 KB ");
		/* set L2E=1, L2I=1, & L2SRAM=0 */
		cache_ctl = 0xc0000000;
		break;
	}

	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
		puts("already enabled");
		l2srbar = l2cache->l2srbar0;
#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
			l2cache->l2srbar0 = l2srbar;
			printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
		}
#endif /* CONFIG_SYS_INIT_L2_ADDR */
		puts("\n");
	} else {
		asm("msync;isync");
		l2cache->l2ctl = cache_ctl; /* invalidate & enable */
		asm("msync;isync");
		puts("enabled\n");
	}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
	u32 l2cfg0 = mfspr(SPRN_L2CFG0);

	/* invalidate the L2 cache */
	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
		;

#ifdef CONFIG_SYS_CACHE_STASHING
	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	mtspr(SPRN_L2CSR1, (32 + 1));
#endif

	/* enable the cache */
	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);

	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
		while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
			;
		printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
	}
#else
	puts("disabled\n");
#endif

	enable_cpc();

	/* needs to be in ram since code uses global static vars */
	fsl_serdes_init();

#ifdef CONFIG_SYS_SRIO
	srio_init();
#endif

#if defined(CONFIG_MP)
	setup_mp();
#endif

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
	{
		void *p;
		p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
		setbits_be32(p, 1 << (31 - 14));
	}
#endif

#ifdef CONFIG_SYS_LBC_LCRR
	/*
	 * Modify the CLKDIV field of LCRR register to improve the writing
	 * speed for NOR flash.
	 */
	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
	__raw_readl(&lbc->lcrr);
	isync();
#endif

	return 0;
}

extern void setup_ivors(void);

void arch_preboot_os(void)
{
	u32 msr;

	/*
	 * We are changing interrupt offsets and are about to boot the OS so
	 * we need to make sure we disable all async interrupts. EE is already
	 * disabled by the time we get called.
	 */
	msr = mfmsr();
	msr &= ~(MSR_ME|MSR_CE|MSR_DE);
	mtmsr(msr);

	setup_ivors();
}

#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
int sata_initialize(void)
{
	if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
		return __sata_initialize();

	return 1;
}
#endif

void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
	qe_init(qe_base);
	qe_reset();
#endif
}
Commit	Line	Data
42d1f039	1	/*
a09b9b68	2	* Copyright 2007-2011 Freescale Semiconductor, Inc.
29372ff3	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Modified by Xianghua Xiao, X.Xiao@motorola.com
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <watchdog.h>
	31	#include <asm/processor.h>
	32	#include <ioports.h>
f54fe87a	33	#include <sata.h>
42d1f039	34	#include <asm/io.h>
fd3c9bef	35	#include <asm/cache.h>
87163180	36	#include <asm/mmu.h>
83d40dfd	37	#include <asm/fsl_law.h>
f54fe87a	38	#include <asm/fsl_serdes.h>
ec2b74ff	39	#include "mp.h"
42d1f039	40
d87080b7 WD	41	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	42
a09b9b68 KG	43	extern void srio_init(void);
a09b9b68 KG	44
da9d4610 AF	45	#ifdef CONFIG_QE
	46	extern qe_iop_conf_t qe_iop_conf_tab[];
	47	extern void qe_config_iopin(u8 port, u8 pin, int dir,
	48	int open_drain, int assign);
	49	extern void qe_init(uint qe_base);
	50	extern void qe_reset(void);
	51
	52	static void config_qe_ioports(void)
	53	{
	54	u8 port, pin;
	55	int dir, open_drain, assign;
	56	int i;
	57
	58	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
	59	port = qe_iop_conf_tab[i].port;
	60	pin = qe_iop_conf_tab[i].pin;
	61	dir = qe_iop_conf_tab[i].dir;
	62	open_drain = qe_iop_conf_tab[i].open_drain;
	63	assign = qe_iop_conf_tab[i].assign;
	64	qe_config_iopin(port, pin, dir, open_drain, assign);
	65	}
	66	}
	67	#endif
40d5fa35	68
9c4c5ae3	69	#ifdef CONFIG_CPM2
aafeefbd	70	void config_8560_ioports (volatile ccsr_cpm_t * cpm)
42d1f039 WD	71	{
	72	int portnum;
	73
	74	for (portnum = 0; portnum < 4; portnum++) {
	75	uint pmsk = 0,
	76	ppar = 0,
	77	psor = 0,
	78	pdir = 0,
	79	podr = 0,
	80	pdat = 0;
	81	iop_conf_t iopc = (iop_conf_t ) & iop_conf_tab[portnum][0];
	82	iop_conf_t *eiopc = iopc + 32;
	83	uint msk = 1;
	84
	85	/*
	86	* NOTE:
	87	* index 0 refers to pin 31,
	88	* index 31 refers to pin 0
	89	*/
	90	while (iopc < eiopc) {
	91	if (iopc->conf) {
	92	pmsk \|= msk;
	93	if (iopc->ppar)
	94	ppar \|= msk;
	95	if (iopc->psor)
	96	psor \|= msk;
	97	if (iopc->pdir)
	98	pdir \|= msk;
	99	if (iopc->podr)
	100	podr \|= msk;
	101	if (iopc->pdat)
	102	pdat \|= msk;
	103	}
	104
	105	msk <<= 1;
	106	iopc++;
	107	}
	108
	109	if (pmsk != 0) {
aafeefbd	110	volatile ioport_t *iop = ioport_addr (cpm, portnum);
42d1f039 WD	111	uint tpmsk = ~pmsk;
	112
	113	/*
	114	* the (somewhat confused) paragraph at the
	115	* bottom of page 35-5 warns that there might
	116	* be "unknown behaviour" when programming
	117	* PSORx and PDIRx, if PPARx = 1, so I
	118	* decided this meant I had to disable the
	119	* dedicated function first, and enable it
	120	* last.
	121	*/
	122	iop->ppar &= tpmsk;
	123	iop->psor = (iop->psor & tpmsk) \| psor;
	124	iop->podr = (iop->podr & tpmsk) \| podr;
	125	iop->pdat = (iop->pdat & tpmsk) \| pdat;
	126	iop->pdir = (iop->pdir & tpmsk) \| pdir;
	127	iop->ppar \|= ppar;
	128	}
	129	}
	130	}
	131	#endif
	132
6aba33e9 KG	133	#ifdef CONFIG_SYS_FSL_CPC
	134	static void enable_cpc(void)
	135	{
	136	int i;
	137	u32 size = 0;
	138
	139	cpc_corenet_t cpc = (cpc_corenet_t )CONFIG_SYS_FSL_CPC_ADDR;
	140
	141	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
	142	u32 cpccfg0 = in_be32(&cpc->cpccfg0);
	143	size += CPC_CFG0_SZ_K(cpccfg0);
	144
1d2c2a62 KG	145	#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
	146	setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
	147	#endif
868da593 KG	148	#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
	149	setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
	150	#endif
1d2c2a62	151
6aba33e9 KG	152	out_be32(&cpc->cpccsr0, CPC_CSR0_CE \| CPC_CSR0_PE);
	153	/* Read back to sync write */
	154	in_be32(&cpc->cpccsr0);
	155
	156	}
	157
	158	printf("Corenet Platform Cache: %d KB enabled\n", size);
	159	}
	160
	161	void invalidate_cpc(void)
	162	{
	163	int i;
	164	cpc_corenet_t cpc = (cpc_corenet_t )CONFIG_SYS_FSL_CPC_ADDR;
	165
	166	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
	167	/* Flash invalidate the CPC and clear all the locks */
	168	out_be32(&cpc->cpccsr0, CPC_CSR0_FI \| CPC_CSR0_LFC);
	169	while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI \| CPC_CSR0_LFC))
	170	;
	171	}
	172	}
	173	#else
	174	#define enable_cpc()
	175	#define invalidate_cpc()
	176	#endif /* CONFIG_SYS_FSL_CPC */
	177
42d1f039 WD	178	/*
	179	* Breathe some life into the CPU...
	180	*
	181	* Set up the memory map
	182	* initialize a bunch of registers
	183	*/
	184
3c2a67ee KG	185	#ifdef CONFIG_FSL_CORENET
	186	static void corenet_tb_init(void)
	187	{
	188	volatile ccsr_rcpm_t *rcpm =
	189	(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
	190	volatile ccsr_pic_t *pic =
680c613a	191	(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
3c2a67ee KG	192	u32 whoami = in_be32(&pic->whoami);
	193
	194	/* Enable the timebase register for this core */
	195	out_be32(&rcpm->ctbenrl, (1 << whoami));
	196	}
	197	#endif
	198
42d1f039 WD	199	void cpu_init_f (void)
42d1f039 WD	200	{
42d1f039	201	extern void m8560_cpm_reset (void);
a2cd50ed PT	202	#ifdef CONFIG_MPC8548
	203	ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
	204	uint svr = get_svr();
	205
	206	/*
	207	* CPU2 errata workaround: A core hang possible while executing
	208	* a msync instruction and a snoopable transaction from an I/O
	209	* master tagged to make quick forward progress is present.
	210	* Fixed in silicon rev 2.1.
	211	*/
	212	if ((SVR_MAJ(svr) == 1) \|\| ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
	213	out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) \| (1 << 16));
	214	#endif
42d1f039	215
87163180 KG	216	disable_tlb(14);
	217	disable_tlb(15);
	218
9c4c5ae3	219	#ifdef CONFIG_CPM2
6d0f6bcf	220	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
42d1f039 WD	221	#endif
42d1f039 WD	222
f51cdaf1	223	init_early_memctl_regs();
42d1f039	224
9c4c5ae3	225	#if defined(CONFIG_CPM2)
42d1f039 WD	226	m8560_cpm_reset();
42d1f039 WD	227	#endif
da9d4610 AF	228	#ifdef CONFIG_QE
	229	/* Config QE ioports */
	230	config_qe_ioports();
	231	#endif
79f4333c PT	232	#if defined(CONFIG_FSL_DMA)
	233	dma_init();
	234	#endif
3c2a67ee KG	235	#ifdef CONFIG_FSL_CORENET
	236	corenet_tb_init();
	237	#endif
94e9411b	238	init_used_tlb_cams();
6aba33e9 KG	239
	240	/* Invalidate the CPC before DDR gets enabled */
	241	invalidate_cpc();
42d1f039 WD	242	}
42d1f039 WD	243
35079aa9 KG	244	/* Implement a dummy function for those platforms w/o SERDES */
	245	static void __fsl_serdes__init(void)
	246	{
	247	return ;
	248	}
	249	__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
d9b94f28	250
42d1f039	251	/*
d9b94f28 JL	252	* Initialize L2 as cache.
	253	*
	254	* The newer 8548, etc, parts have twice as much cache, but
	255	* use the same bit-encoding as the older 8555, etc, parts.
	256	*
42d1f039	257	*/
d9b94f28	258	int cpu_init_r(void)
42d1f039	259	{
3f0202ed	260	#ifdef CONFIG_SYS_LBC_LCRR
f51cdaf1	261	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
3f0202ed LC	262	#endif
3f0202ed LC	263
fd3c9bef KG	264	#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
	265	flush_dcache();
	266	mtspr(L1CSR2, (mfspr(L1CSR2) \| L1CSR2_DCWS));
	267	sync();
	268	#endif
	269
6beecfbb WG	270	puts ("L2: ");
6beecfbb WG	271
42d1f039	272	#if defined(CONFIG_L2_CACHE)
6d0f6bcf	273	volatile ccsr_l2cache_t l2cache = (void )CONFIG_SYS_MPC85xx_L2_ADDR;
d9b94f28 JL	274	volatile uint cache_ctl;
d9b94f28 JL	275	uint svr, ver;
29372ff3	276	uint l2srbar;
73f15a06	277	u32 l2siz_field;
d9b94f28 JL	278
d9b94f28 JL	279	svr = get_svr();
f3e04bdc	280	ver = SVR_SOC_VER(svr);
42d1f039	281
d65cfe89	282	asm("msync;isync");
d9b94f28	283	cache_ctl = l2cache->l2ctl;
7da53351 MH	284
	285	#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	286	if (cache_ctl & MPC85xx_L2CTL_L2E) {
	287	/* Clear L2 SRAM memory-mapped base address */
	288	out_be32(&l2cache->l2srbar0, 0x0);
	289	out_be32(&l2cache->l2srbar1, 0x0);
	290
	291	/* set MBECCDIS=0, SBECCDIS=0 */
	292	clrbits_be32(&l2cache->l2errdis,
	293	(MPC85xx_L2ERRDIS_MBECC \|
	294	MPC85xx_L2ERRDIS_SBECC));
	295
	296	/* set L2E=0, L2SRAM=0 */
	297	clrbits_be32(&l2cache->l2ctl,
	298	(MPC85xx_L2CTL_L2E \|
	299	MPC85xx_L2CTL_L2SRAM_ENTIRE));
	300	}
	301	#endif
	302
73f15a06	303	l2siz_field = (cache_ctl >> 28) & 0x3;
d9b94f28	304
73f15a06 KG	305	switch (l2siz_field) {
	306	case 0x0:
	307	printf(" unknown size (0x%08x)\n", cache_ctl);
	308	return -1;
	309	break;
	310	case 0x1:
	311	if (ver == SVR_8540 \|\| ver == SVR_8560 \|\|
	312	ver == SVR_8541 \|\| ver == SVR_8541_E \|\|
	313	ver == SVR_8555 \|\| ver == SVR_8555_E) {
	314	puts("128 KB ");
	315	/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
	316	cache_ctl = 0xc4000000;
d9b94f28	317	} else {
73f15a06 KG	318	puts("256 KB ");
	319	cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
	320	}
	321	break;
	322	case 0x2:
	323	if (ver == SVR_8540 \|\| ver == SVR_8560 \|\|
	324	ver == SVR_8541 \|\| ver == SVR_8541_E \|\|
	325	ver == SVR_8555 \|\| ver == SVR_8555_E) {
6beecfbb	326	puts("256 KB ");
29372ff3 ES	327	/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
29372ff3 ES	328	cache_ctl = 0xc8000000;
73f15a06 KG	329	} else {
	330	puts ("512 KB ");
	331	/* set L2E=1, L2I=1, & L2SRAM=0 */
	332	cache_ctl = 0xc0000000;
d9b94f28	333	}
d65cfe89	334	break;
73f15a06 KG	335	case 0x3:
	336	puts("1024 KB ");
	337	/* set L2E=1, L2I=1, & L2SRAM=0 */
	338	cache_ctl = 0xc0000000;
29372ff3	339	break;
d65cfe89 JL	340	}
d65cfe89 JL	341
76b474e2	342	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
6beecfbb	343	puts("already enabled");
29372ff3	344	l2srbar = l2cache->l2srbar0;
888279b5	345	#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
76b474e2 MH	346	if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
76b474e2 MH	347	&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
6d0f6bcf	348	l2srbar = CONFIG_SYS_INIT_L2_ADDR;
29372ff3	349	l2cache->l2srbar0 = l2srbar;
6d0f6bcf	350	printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
29372ff3	351	}
6d0f6bcf	352	#endif /* CONFIG_SYS_INIT_L2_ADDR */
29372ff3 ES	353	puts("\n");
	354	} else {
	355	asm("msync;isync");
	356	l2cache->l2ctl = cache_ctl; /* invalidate & enable */
	357	asm("msync;isync");
6beecfbb	358	puts("enabled\n");
29372ff3	359	}
1b3e4044 KG	360	#elif defined(CONFIG_BACKSIDE_L2_CACHE)
	361	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
	362
	363	/* invalidate the L2 cache */
25bacf7a KG	364	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI\|L2CSR0_L2LFC));
25bacf7a KG	365	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI\|L2CSR0_L2LFC))
1b3e4044 KG	366	;
1b3e4044 KG	367
82fd1f8d KG	368	#ifdef CONFIG_SYS_CACHE_STASHING
	369	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	370	mtspr(SPRN_L2CSR1, (32 + 1));
	371	#endif
	372
1b3e4044 KG	373	/* enable the cache */
	374	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
	375
654ea1f3 DL	376	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
	377	while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
	378	;
1b3e4044	379	printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
654ea1f3	380	}
42d1f039	381	#else
6beecfbb	382	puts("disabled\n");
42d1f039	383	#endif
6aba33e9 KG	384
	385	enable_cpc();
	386
af025065 KG	387	/* needs to be in ram since code uses global static vars */
af025065 KG	388	fsl_serdes_init();
af025065	389
a09b9b68 KG	390	#ifdef CONFIG_SYS_SRIO
	391	srio_init();
	392	#endif
	393
ec2b74ff KG	394	#if defined(CONFIG_MP)
	395	setup_mp();
	396	#endif
3f0202ed	397
ae026ffd RZ	398	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
	399	{
	400	void *p;
	401	p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
	402	setbits_be32(p, 1 << (31 - 14));
	403	}
	404	#endif
	405
3f0202ed LC	406	#ifdef CONFIG_SYS_LBC_LCRR
	407	/*
	408	* Modify the CLKDIV field of LCRR register to improve the writing
	409	* speed for NOR flash.
	410	*/
	411	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
	412	__raw_readl(&lbc->lcrr);
	413	isync();
	414	#endif
	415
42d1f039 WD	416	return 0;
42d1f039 WD	417	}
26f4cdba KG	418
	419	extern void setup_ivors(void);
	420
	421	void arch_preboot_os(void)
	422	{
15fba327 KG	423	u32 msr;
	424
	425	/*
	426	* We are changing interrupt offsets and are about to boot the OS so
	427	* we need to make sure we disable all async interrupts. EE is already
	428	* disabled by the time we get called.
	429	*/
	430	msr = mfmsr();
	431	msr &= ~(MSR_ME\|MSR_CE\|MSR_DE);
	432	mtmsr(msr);
	433
26f4cdba KG	434	setup_ivors();
26f4cdba KG	435	}
f54fe87a KG	436
	437	#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
	438	int sata_initialize(void)
	439	{
	440	if (is_serdes_configured(SATA1) \|\| is_serdes_configured(SATA2))
	441	return __sata_initialize();
	442
	443	return 1;
	444	}
	445	#endif
f9a33f1c KG	446
	447	void cpu_secondary_init_r(void)
	448	{
	449	#ifdef CONFIG_QE
	450	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
	451	qe_init(qe_base);
	452	qe_reset();
	453	#endif
	454	}