[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

/*
 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* --------------------------------------------------------------- */

void get_sys_info (sys_info_t * sysInfo)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
	u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
	unsigned int cpu;

	const u8 core_cplx_PLL[16] = {
		[ 0] = 0,	/* CC1 PPL / 1 */
		[ 1] = 0,	/* CC1 PPL / 2 */
		[ 2] = 0,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 1,	/* CC2 PPL / 2 */
		[ 6] = 1,	/* CC2 PPL / 4 */
		[ 8] = 2,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_PLL_div[16] = {
		[ 0] = 1,	/* CC1 PPL / 1 */
		[ 1] = 2,	/* CC1 PPL / 2 */
		[ 2] = 4,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 2,	/* CC2 PPL / 2 */
		[ 6] = 4,	/* CC2 PPL / 4 */
		[ 8] = 1,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};
	uint i, freqCC_PLL[6], rcw_tmp;
	uint ratio[6];
	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
	uint mem_pll_rat;

	sysInfo->freqSystemBus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
	sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
#else
	sysInfo->freqDDRBus = sysclk;
#endif

	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
	if (mem_pll_rat > 2)
		sysInfo->freqDDRBus *= mem_pll_rat;
	else
		sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;

	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
	for (i = 0; i < 6; i++) {
		if (ratio[i] > 4)
			freqCC_PLL[i] = sysclk * ratio[i];
		else
			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
	}
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	/*
	 * Each cluster has up to 4 cores, sharing the same PLL selection.
	 * The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are
	 * cluster group A, feeding cores on cluster 1 and cluster 2.
	 * PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3
	 * and cluster 4 if existing.
	 */
	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		int cluster = fsl_qoriq_core_to_cluster(cpu);
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
		if (cplx_pll > 3)
			printf("Unsupported architecture configuration"
				" in function %s\n", __func__);
		cplx_pll += (cluster / 2) * 3;
		sysInfo->freqProcessor[cpu] =
			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	}
#ifdef CONFIG_PPC_B4860
#define FM1_CLK_SEL	0xe0000000
#define FM1_CLK_SHIFT	29
#else
#define PME_CLK_SEL	0xe0000000
#define PME_CLK_SHIFT	29
#define FM1_CLK_SEL	0x1c000000
#define FM1_CLK_SHIFT	26
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
	case 1:
		sysInfo->freqPME = freqCC_PLL[0];
		break;
	case 2:
		sysInfo->freqPME = freqCC_PLL[0] / 2;
		break;
	case 3:
		sysInfo->freqPME = freqCC_PLL[0] / 3;
		break;
	case 4:
		sysInfo->freqPME = freqCC_PLL[0] / 4;
		break;
	case 6:
		sysInfo->freqPME = freqCC_PLL[1] / 2;
		break;
	case 7:
		sysInfo->freqPME = freqCC_PLL[1] / 3;
		break;
	default:
		printf("Error: Unknown PME clock select!\n");
	case 0:
		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
		break;

	}
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
	case 1:
		sysInfo->freqFMan[0] = freqCC_PLL[3];
		break;
	case 2:
		sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
		break;
	case 3:
		sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
		break;
	case 4:
		sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
		break;
	case 5:
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
		break;
	case 6:
		sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
		break;
	case 7:
		sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
		break;
	default:
		printf("Error: Unknown FMan1 clock select!\n");
	case 0:
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
		break;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
#define FM2_CLK_SEL	0x00000038
#define FM2_CLK_SHIFT	3
	rcw_tmp = in_be32(&gur->rcwsr[15]);
	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	case 1:
		sysInfo->freqFMan[1] = freqCC_PLL[4];
		break;
	case 2:
		sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
		break;
	case 3:
		sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
		break;
	case 4:
		sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
		break;
	case 6:
		sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
		break;
	case 7:
		sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
		break;
	default:
		printf("Error: Unknown FMan2 clock select!\n");
	case 0:
		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
		break;
	}
#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
#endif	/* CONFIG_SYS_DPAA_FMAN */

#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];

		sysInfo->freqProcessor[cpu] =
			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	}
#define PME_CLK_SEL	0x80000000
#define FM1_CLK_SEL	0x40000000
#define FM2_CLK_SEL	0x20000000
#define HWA_ASYNC_DIV	0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL	1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
#define HWA_CC_PLL	2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL	2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	if (rcw_tmp & PME_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
	}
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	if (rcw_tmp & FM1_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
	if (rcw_tmp & FM2_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
	}
#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
#endif

#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

#else /* CONFIG_FSL_CORENET */
	uint plat_ratio, e500_ratio, half_freqSystemBus;
	int i;
#ifdef CONFIG_QE
	__maybe_unused u32 qe_ratio;
#endif

	plat_ratio = (gur->porpllsr) & 0x0000003e;
	plat_ratio >>= 1;
	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;

	/* Divide before multiply to avoid integer
	 * overflow for processor speeds above 2GHz */
	half_freqSystemBus = sysInfo->freqSystemBus/2;
	for (i = 0; i < cpu_numcores(); i++) {
		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
		sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
	}

	/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
	sysInfo->freqDDRBus = sysInfo->freqSystemBus;

#ifdef CONFIG_DDR_CLK_FREQ
	{
		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
		if (ddr_ratio != 0x7)
			sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	}
#endif

#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
	sysInfo->freqQE =  sysInfo->freqSystemBus;
#else
	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
#endif

#endif /* CONFIG_FSL_CORENET */

#if defined(CONFIG_FSL_LBC)
	uint lcrr_div;
#if defined(CONFIG_SYS_LBC_LCRR)
	/* We will program LCRR to this value later */
	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
		/* If this is corenet based SoC, bit-representation
		 * for four times the clock divider values.
		 */
		lcrr_div *= 4;
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		lcrr_div *= 2;
#endif
		sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
	} else {
		/* In case anyone cares what the unknown value is */
		sysInfo->freqLocalBus = lcrr_div;
	}
#endif

#if defined(CONFIG_FSL_IFC)
	ccr = in_be32(&ifc_regs->ifc_ccr);
	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;

	sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
#endif
}


int get_clocks (void)
{
	sys_info_t sys_info;
#ifdef CONFIG_MPC8544
	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint sccr, dfbrg;

	/* set VCO = 4 * BRG */
	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
	sccr = cpm->im_cpm_intctl.sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freqProcessor[0];
	gd->bus_clk = sys_info.freqSystemBus;
	gd->mem_clk = sys_info.freqDDRBus;
	gd->arch.lbc_clk = sys_info.freqLocalBus;

#ifdef CONFIG_QE
	gd->arch.qe_clk = sys_info.freqQE;
	gd->arch.brg_clk = gd->arch.qe_clk / 2;
#endif
	/*
	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
	 * there is no pattern that can be used to determine the frequency, so
	 * the only choice is to look up the actual SOC number and use the value
	 * for that SOC. This information is taken from application note
	 * AN2919.
	 */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
	gd->arch.i2c1_clk = sys_info.freqSystemBus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
	else
		gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
#endif
	gd->arch.i2c2_clk = gd->arch.i2c1_clk;

#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
       defined(CONFIG_P1014)
	gd->arch.sdhc_clk = gd->bus_clk;
#else
	gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2)
	gd->arch.vco_out = 2*sys_info.freqSystemBus;
	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	gd->arch.scc_clk = gd->arch.vco_out / 4;
	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
#endif

	if(gd->cpu_clk != 0) return (0);
	else return (1);
}


/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq (ulong dummy)
{
	return gd->mem_clk;
}
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Xianghua Xiao, (X.Xiao@motorola.com)
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	11	*/
	12
	13	#include <common.h>
	14	#include <ppc_asm.tmpl>
a52d2f81	15	#include <linux/compiler.h>
42d1f039	16	#include <asm/processor.h>
ada591d2	17	#include <asm/io.h>
42d1f039	18
d87080b7 WD	19	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	20
42d1f039 WD	21	/* --------------------------------------------------------------- */
42d1f039 WD	22
42d1f039 WD	23	void get_sys_info (sys_info_t * sysInfo)
42d1f039 WD	24	{
6d0f6bcf	25	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
800c73c4 KG	26	#ifdef CONFIG_FSL_IFC
	27	struct fsl_ifc ifc_regs = (void )CONFIG_SYS_IFC_ADDR;
	28	u32 ccr;
	29	#endif
39aaca1f KG	30	#ifdef CONFIG_FSL_CORENET
39aaca1f KG	31	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7	32	unsigned int cpu;
39aaca1f KG	33
	34	const u8 core_cplx_PLL[16] = {
	35	[ 0] = 0, /* CC1 PPL / 1 */
	36	[ 1] = 0, /* CC1 PPL / 2 */
	37	[ 2] = 0, /* CC1 PPL / 4 */
	38	[ 4] = 1, /* CC2 PPL / 1 */
	39	[ 5] = 1, /* CC2 PPL / 2 */
	40	[ 6] = 1, /* CC2 PPL / 4 */
	41	[ 8] = 2, /* CC3 PPL / 1 */
	42	[ 9] = 2, /* CC3 PPL / 2 */
	43	[10] = 2, /* CC3 PPL / 4 */
	44	[12] = 3, /* CC4 PPL / 1 */
	45	[13] = 3, /* CC4 PPL / 2 */
	46	[14] = 3, /* CC4 PPL / 4 */
	47	};
	48
	49	const u8 core_cplx_PLL_div[16] = {
	50	[ 0] = 1, /* CC1 PPL / 1 */
	51	[ 1] = 2, /* CC1 PPL / 2 */
	52	[ 2] = 4, /* CC1 PPL / 4 */
	53	[ 4] = 1, /* CC2 PPL / 1 */
	54	[ 5] = 2, /* CC2 PPL / 2 */
	55	[ 6] = 4, /* CC2 PPL / 4 */
	56	[ 8] = 1, /* CC3 PPL / 1 */
	57	[ 9] = 2, /* CC3 PPL / 2 */
	58	[10] = 4, /* CC3 PPL / 4 */
	59	[12] = 1, /* CC4 PPL / 1 */
	60	[13] = 2, /* CC4 PPL / 2 */
	61	[14] = 4, /* CC4 PPL / 4 */
	62	};
9a653a98 YS	63	uint i, freqCC_PLL[6], rcw_tmp;
9a653a98 YS	64	uint ratio[6];
39aaca1f	65	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a	66	uint mem_pll_rat;
39aaca1f KG	67
39aaca1f KG	68	sysInfo->freqSystemBus = sysclk;
98ffa190 YS	69	#ifdef CONFIG_DDR_CLK_FREQ
	70	sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
	71	#else
39aaca1f	72	sysInfo->freqDDRBus = sysclk;
98ffa190	73	#endif
39aaca1f	74
93cedc71	75	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
f77329cf YS	76	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
	77	FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
	78	& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
ab48ca1a SS	79	if (mem_pll_rat > 2)
	80	sysInfo->freqDDRBus *= mem_pll_rat;
	81	else
	82	sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
39aaca1f	83
ab48ca1a SS	84	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
	85	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
	86	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
	87	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
9a653a98 YS	88	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
	89	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
	90	for (i = 0; i < 6; i++) {
ab48ca1a SS	91	if (ratio[i] > 4)
	92	freqCC_PLL[i] = sysclk * ratio[i];
	93	else
	94	freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
	95	}
9a653a98 YS	96	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	97	/*
	98	* Each cluster has up to 4 cores, sharing the same PLL selection.
f6981439 YS	99	* The cluster assignment is fixed per SoC. PLL1, PLL2, PLL3 are
	100	* cluster group A, feeding cores on cluster 1 and cluster 2.
	101	* PLL4, PLL5, PLL6 are cluster group B, feeding cores on cluster 3
	102	* and cluster 4 if existing.
9a653a98	103	*/
fbb9ecf7	104	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	105	int cluster = fsl_qoriq_core_to_cluster(cpu);
f6981439 YS	106	u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
9a653a98	107	& 0xf;
39aaca1f	108	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
9a653a98 YS	109	if (cplx_pll > 3)
	110	printf("Unsupported architecture configuration"
	111	" in function %s\n", __func__);
f6981439	112	cplx_pll += (cluster / 2) * 3;
fbb9ecf7	113	sysInfo->freqProcessor[cpu] =
39aaca1f KG	114	freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
39aaca1f KG	115	}
0cb3325c SS	116	#ifdef CONFIG_PPC_B4860
	117	#define FM1_CLK_SEL 0xe0000000
	118	#define FM1_CLK_SHIFT 29
	119	#else
9a653a98 YS	120	#define PME_CLK_SEL 0xe0000000
	121	#define PME_CLK_SHIFT 29
	122	#define FM1_CLK_SEL 0x1c000000
	123	#define FM1_CLK_SHIFT 26
0cb3325c	124	#endif
9a653a98 YS	125	rcw_tmp = in_be32(&gur->rcwsr[7]);
	126
	127	#ifdef CONFIG_SYS_DPAA_PME
	128	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
	129	case 1:
	130	sysInfo->freqPME = freqCC_PLL[0];
	131	break;
	132	case 2:
	133	sysInfo->freqPME = freqCC_PLL[0] / 2;
	134	break;
	135	case 3:
	136	sysInfo->freqPME = freqCC_PLL[0] / 3;
	137	break;
	138	case 4:
	139	sysInfo->freqPME = freqCC_PLL[0] / 4;
	140	break;
	141	case 6:
	142	sysInfo->freqPME = freqCC_PLL[1] / 2;
	143	break;
	144	case 7:
	145	sysInfo->freqPME = freqCC_PLL[1] / 3;
	146	break;
	147	default:
	148	printf("Error: Unknown PME clock select!\n");
	149	case 0:
	150	sysInfo->freqPME = sysInfo->freqSystemBus / 2;
	151	break;
	152
	153	}
	154	#endif
	155
990e1a8c HW	156	#ifdef CONFIG_SYS_DPAA_QBMAN
	157	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
	158	#endif
	159
9a653a98 YS	160	#ifdef CONFIG_SYS_DPAA_FMAN
	161	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
	162	case 1:
	163	sysInfo->freqFMan[0] = freqCC_PLL[3];
	164	break;
	165	case 2:
	166	sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
	167	break;
	168	case 3:
	169	sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
	170	break;
	171	case 4:
	172	sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
	173	break;
0cb3325c SS	174	case 5:
	175	sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
	176	break;
9a653a98 YS	177	case 6:
	178	sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
	179	break;
	180	case 7:
	181	sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
	182	break;
	183	default:
	184	printf("Error: Unknown FMan1 clock select!\n");
	185	case 0:
	186	sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
	187	break;
	188	}
	189	#if (CONFIG_SYS_NUM_FMAN) == 2
	190	#define FM2_CLK_SEL 0x00000038
	191	#define FM2_CLK_SHIFT 3
	192	rcw_tmp = in_be32(&gur->rcwsr[15]);
	193	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	194	case 1:
	195	sysInfo->freqFMan[1] = freqCC_PLL[4];
	196	break;
	197	case 2:
	198	sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
	199	break;
	200	case 3:
	201	sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
	202	break;
	203	case 4:
	204	sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
	205	break;
	206	case 6:
	207	sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
	208	break;
	209	case 7:
	210	sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
	211	break;
	212	default:
	213	printf("Error: Unknown FMan2 clock select!\n");
	214	case 0:
	215	sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
	216	break;
	217	}
	218	#endif /* CONFIG_SYS_NUM_FMAN == 2 */
	219	#endif /* CONFIG_SYS_DPAA_FMAN */
39aaca1f	220
9a653a98 YS	221	#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	222
	223	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	224	u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
f6981439 YS	225	& 0xf;
9a653a98 YS	226	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
	227
	228	sysInfo->freqProcessor[cpu] =
	229	freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	230	}
39aaca1f KG	231	#define PME_CLK_SEL 0x80000000
	232	#define FM1_CLK_SEL 0x40000000
	233	#define FM2_CLK_SEL 0x20000000
b5c8753f KG	234	#define HWA_ASYNC_DIV 0x04000000
	235	#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
	236	#define HWA_CC_PLL 1
4905443f TT	237	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
4905443f TT	238	#define HWA_CC_PLL 2
b5c8753f	239	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5	240	#define HWA_CC_PLL 2
b5c8753f KG	241	#else
	242	#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
	243	#endif
39aaca1f KG	244	rcw_tmp = in_be32(&gur->rcwsr[7]);
	245
	246	#ifdef CONFIG_SYS_DPAA_PME
b5c8753f KG	247	if (rcw_tmp & PME_CLK_SEL) {
	248	if (rcw_tmp & HWA_ASYNC_DIV)
	249	sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
	250	else
	251	sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
	252	} else {
693416fe	253	sysInfo->freqPME = sysInfo->freqSystemBus / 2;
b5c8753f	254	}
39aaca1f KG	255	#endif
	256
	257	#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f KG	258	if (rcw_tmp & FM1_CLK_SEL) {
	259	if (rcw_tmp & HWA_ASYNC_DIV)
	260	sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
	261	else
	262	sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
	263	} else {
693416fe	264	sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
b5c8753f	265	}
39aaca1f	266	#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f KG	267	if (rcw_tmp & FM2_CLK_SEL) {
	268	if (rcw_tmp & HWA_ASYNC_DIV)
	269	sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
	270	else
	271	sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
	272	} else {
693416fe	273	sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
b5c8753f	274	}
39aaca1f KG	275	#endif
	276	#endif
	277
3e83fc9b SX	278	#ifdef CONFIG_SYS_DPAA_QBMAN
	279	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
	280	#endif
	281
9a653a98 YS	282	#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	283
	284	#else /* CONFIG_FSL_CORENET */
	285	uint plat_ratio, e500_ratio, half_freqSystemBus;
2fc7eb0c	286	int i;
b3d7f20f	287	#ifdef CONFIG_QE
a52d2f81	288	__maybe_unused u32 qe_ratio;
b3d7f20f	289	#endif
42d1f039 WD	290
	291	plat_ratio = (gur->porpllsr) & 0x0000003e;
	292	plat_ratio >>= 1;
66ed6cca	293	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca AF	294
	295	/* Divide before multiply to avoid integer
	296	* overflow for processor speeds above 2GHz */
	297	half_freqSystemBus = sysInfo->freqSystemBus/2;
0e870980	298	for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c HW	299	e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
	300	sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
	301	}
a3e77fa5 JY	302
a3e77fa5 JY	303	/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
d4357932 KG	304	sysInfo->freqDDRBus = sysInfo->freqSystemBus;
	305
	306	#ifdef CONFIG_DDR_CLK_FREQ
	307	{
c0391111 JJ	308	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	309	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932 KG	310	if (ddr_ratio != 0x7)
	311	sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	312	}
	313	#endif
ada591d2	314
b3d7f20f	315	#ifdef CONFIG_QE
be7bebea	316	#if defined(CONFIG_P1012) \|\| defined(CONFIG_P1021) \|\| defined(CONFIG_P1025)
a52d2f81 HW	317	sysInfo->freqQE = sysInfo->freqSystemBus;
a52d2f81 HW	318	#else
b3d7f20f HW	319	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
	320	>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	321	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
	322	#endif
a52d2f81	323	#endif
b3d7f20f	324
24995d82	325	#ifdef CONFIG_SYS_DPAA_FMAN
939cdcdc	326	sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
24995d82 HW	327	#endif
	328
	329	#endif /* CONFIG_FSL_CORENET */
	330
beba93ed	331	#if defined(CONFIG_FSL_LBC)
9a653a98	332	uint lcrr_div;
ada591d2 TP	333	#if defined(CONFIG_SYS_LBC_LCRR)
	334	/* We will program LCRR to this value later */
	335	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
	336	#else
f51cdaf1	337	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2 TP	338	#endif
ada591d2 TP	339	if (lcrr_div == 2 \|\| lcrr_div == 4 \|\| lcrr_div == 8) {
0fd2fa6c DL	340	#if defined(CONFIG_FSL_CORENET)
	341	/* If this is corenet based SoC, bit-representation
	342	* for four times the clock divider values.
	343	*/
	344	lcrr_div *= 4;
	345	#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
ada591d2 TP	346	!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
	347	/*
	348	* Yes, the entire PQ38 family use the same
	349	* bit-representation for twice the clock divider values.
	350	*/
	351	lcrr_div *= 2;
	352	#endif
	353	sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
	354	} else {
	355	/* In case anyone cares what the unknown value is */
	356	sysInfo->freqLocalBus = lcrr_div;
	357	}
beba93ed	358	#endif
800c73c4 KG	359
	360	#if defined(CONFIG_FSL_IFC)
	361	ccr = in_be32(&ifc_regs->ifc_ccr);
	362	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
	363
	364	sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
	365	#endif
42d1f039 WD	366	}
42d1f039 WD	367
66ed6cca	368
42d1f039 WD	369	int get_clocks (void)
42d1f039 WD	370	{
42d1f039	371	sys_info_t sys_info;
88353a98	372	#ifdef CONFIG_MPC8544
6d0f6bcf	373	volatile ccsr_gur_t gur = (void ) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98	374	#endif
9c4c5ae3	375	#if defined(CONFIG_CPM2)
6d0f6bcf	376	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	377	uint sccr, dfbrg;
	378
	379	/* set VCO = 4 * BRG */
aafeefbd KG	380	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
aafeefbd KG	381	sccr = cpm->im_cpm_intctl.sccr;
42d1f039 WD	382	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	383	#endif
	384	get_sys_info (&sys_info);
2fc7eb0c	385	gd->cpu_clk = sys_info.freqProcessor[0];
42d1f039	386	gd->bus_clk = sys_info.freqSystemBus;
a3e77fa5	387	gd->mem_clk = sys_info.freqDDRBus;
67ac13b1	388	gd->arch.lbc_clk = sys_info.freqLocalBus;
88353a98	389
b3d7f20f	390	#ifdef CONFIG_QE
45bae2e3 SG	391	gd->arch.qe_clk = sys_info.freqQE;
45bae2e3 SG	392	gd->arch.brg_clk = gd->arch.qe_clk / 2;
b3d7f20f	393	#endif
88353a98 TT	394	/*
	395	* The base clock for I2C depends on the actual SOC. Unfortunately,
	396	* there is no pattern that can be used to determine the frequency, so
	397	* the only choice is to look up the actual SOC number and use the value
	398	* for that SOC. This information is taken from application note
	399	* AN2919.
	400	*/
	401	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
	402	defined(CONFIG_MPC8560) \|\| defined(CONFIG_MPC8555)
609e6ec3	403	gd->arch.i2c1_clk = sys_info.freqSystemBus;
88353a98 TT	404	#elif defined(CONFIG_MPC8544)
	405	/*
	406	* On the 8544, the I2C clock is the same as the SEC clock. This can be
	407	* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	408	* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
	409	* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	410	* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	411	*/
	412	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
609e6ec3	413	gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
42653b82	414	else
609e6ec3	415	gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
88353a98 TT	416	#else
88353a98 TT	417	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
609e6ec3	418	gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
88353a98	419	#endif
609e6ec3	420	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
943afa22	421
6b9ea08c	422	#if defined(CONFIG_FSL_ESDHC)
7d640e9b PJ	423	#if defined(CONFIG_MPC8569) \|\| defined(CONFIG_P1010) \|\|\
7d640e9b PJ	424	defined(CONFIG_P1014)
e9adeca3	425	gd->arch.sdhc_clk = gd->bus_clk;
7f52ed5e	426	#else
e9adeca3	427	gd->arch.sdhc_clk = gd->bus_clk / 2;
ef50d6c0	428	#endif
7f52ed5e	429	#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0	430
9c4c5ae3	431	#if defined(CONFIG_CPM2)
748cd059 SG	432	gd->arch.vco_out = 2*sys_info.freqSystemBus;
	433	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	434	gd->arch.scc_clk = gd->arch.vco_out / 4;
	435	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
42d1f039 WD	436	#endif
	437
	438	if(gd->cpu_clk != 0) return (0);
	439	else return (1);
	440	}
	441
	442
	443	/********************************************
	444	* get_bus_freq
	445	* return system bus freq in Hz
	446	*********************************************/
	447	ulong get_bus_freq (ulong dummy)
	448	{
a3e77fa5	449	return gd->bus_clk;
42d1f039	450	}
d4357932 KG	451
	452	/********************************************
	453	* get_ddr_freq
	454	* return ddr bus freq in Hz
	455	*********************************************/
	456	ulong get_ddr_freq (ulong dummy)
	457	{
a3e77fa5	458	return gd->mem_clk;
d4357932	459	}