[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

/*
 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;


#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
#define CONFIG_SYS_FSL_NUM_CC_PLLS	6
#endif
/* --------------------------------------------------------------- */

void get_sys_info(sys_info_t *sys_info)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
	u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
	unsigned int cpu;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif

	const u8 core_cplx_PLL[16] = {
		[ 0] = 0,	/* CC1 PPL / 1 */
		[ 1] = 0,	/* CC1 PPL / 2 */
		[ 2] = 0,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 1,	/* CC2 PPL / 2 */
		[ 6] = 1,	/* CC2 PPL / 4 */
		[ 8] = 2,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_pll_div[16] = {
		[ 0] = 1,	/* CC1 PPL / 1 */
		[ 1] = 2,	/* CC1 PPL / 2 */
		[ 2] = 4,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 2,	/* CC2 PPL / 2 */
		[ 6] = 4,	/* CC2 PPL / 4 */
		[ 8] = 1,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};
	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
	uint rcw_tmp;
#endif
	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
	uint mem_pll_rat;

	sys_info->freq_systembus = sysclk;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
	uint ddr_refclk_sel;
	unsigned int porsr1_sys_clk;
	porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
						& FSL_DCFG_PORSR1_SYSCLK_MASK;
	if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
		sys_info->diff_sysclk = 1;
	else
		sys_info->diff_sysclk = 0;

	/*
	 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
	 * are driven by separate DDR Refclock or single source
	 * differential clock.
	 */
	ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
	/*
	 * For single source clocking, both ddrclock and sysclock
	 * are driven by differential sysclock.
	 */
	if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
	else
#endif
#ifdef CONFIG_DDR_CLK_FREQ
		sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#else
		sys_info->freq_ddrbus = sysclk;
#endif

	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
	if (mem_pll_rat == 0) {
		mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
	}
#endif
	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
	 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
	 * it uses 6.
	 */
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
	if (SVR_MAJ(get_svr()) >= 2)
		mem_pll_rat *= 2;
#endif
	if (mem_pll_rat > 2)
		sys_info->freq_ddrbus *= mem_pll_rat;
	else
		sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;

	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
		if (ratio[i] > 4)
			freq_c_pll[i] = sysclk * ratio[i];
		else
			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
	}
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	/*
	 * As per CHASSIS2 architeture total 12 clusters are posible and
	 * Each cluster has up to 4 cores, sharing the same PLL selection.
	 * The cluster clock assignment is SoC defined.
	 *
	 * Total 4 clock groups are possible with 3 PLLs each.
	 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
	 * clock group B has 3, 4, 6 and so on.
	 *
	 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
	 * depends upon the SoC architeture. Same applies to other
	 * clock groups and clusters.
	 *
	 */
	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		int cluster = fsl_qoriq_core_to_cluster(cpu);
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
		cplx_pll += cc_group[cluster] - 1;
		sys_info->freq_processor[cpu] =
			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
	defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL	0xe0000000
#define FM1_CLK_SHIFT	29
#else
#define PME_CLK_SEL	0xe0000000
#define PME_CLK_SHIFT	29
#define FM1_CLK_SEL	0x1c000000
#define FM1_CLK_SHIFT	26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
	rcw_tmp = in_be32(&gur->rcwsr[7]);
#endif

#ifdef CONFIG_SYS_DPAA_PME
#ifndef CONFIG_PME_PLAT_CLK_DIV
	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
	case 1:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
		break;
	case 2:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
		break;
	case 3:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
		break;
	case 4:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
		break;
	case 6:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
		break;
	case 7:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
		break;
	default:
		printf("Error: Unknown PME clock select!\n");
	case 0:
		sys_info->freq_pme = sys_info->freq_systembus / 2;
		break;

	}
#else
	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;

#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_FM_PLAT_CLK_DIV
	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
	case 1:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
		break;
	case 2:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
		break;
	case 3:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
		break;
	case 4:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
		break;
	case 5:
		sys_info->freq_fman[0] = sys_info->freq_systembus;
		break;
	case 6:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
		break;
	case 7:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
		break;
	default:
		printf("Error: Unknown FMan1 clock select!\n");
	case 0:
		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
		break;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
#ifdef CONFIG_SYS_FM2_CLK
#define FM2_CLK_SEL	0x00000038
#define FM2_CLK_SHIFT	3
	rcw_tmp = in_be32(&gur->rcwsr[15]);
	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	case 1:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
		break;
	case 2:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
		break;
	case 3:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
		break;
	case 4:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
		break;
	case 5:
		sys_info->freq_fman[1] = sys_info->freq_systembus;
		break;
	case 6:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
		break;
	case 7:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
		break;
	default:
		printf("Error: Unknown FMan2 clock select!\n");
	case 0:
		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
		break;
	}
#endif
#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
#else
	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
#endif
#endif

#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];

		sys_info->freq_processor[cpu] =
			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}
#define PME_CLK_SEL	0x80000000
#define FM1_CLK_SEL	0x40000000
#define FM2_CLK_SEL	0x20000000
#define HWA_ASYNC_DIV	0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL	1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
#define HWA_CC_PLL	2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL	2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	if (rcw_tmp & PME_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_pme = sys_info->freq_systembus / 2;
	}
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	if (rcw_tmp & FM1_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
	if (rcw_tmp & FM2_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
	}
#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif

#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

#ifdef CONFIG_U_QE
	sys_info->freq_qe =  sys_info->freq_systembus / 2;
#endif

#else /* CONFIG_FSL_CORENET */
	uint plat_ratio, e500_ratio, half_freq_systembus;
	int i;
#ifdef CONFIG_QE
	__maybe_unused u32 qe_ratio;
#endif

	plat_ratio = (gur->porpllsr) & 0x0000003e;
	plat_ratio >>= 1;
	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;

	/* Divide before multiply to avoid integer
	 * overflow for processor speeds above 2GHz */
	half_freq_systembus = sys_info->freq_systembus/2;
	for (i = 0; i < cpu_numcores(); i++) {
		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
		sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
	}

	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
	sys_info->freq_ddrbus = sys_info->freq_systembus;

#ifdef CONFIG_DDR_CLK_FREQ
	{
		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
		if (ddr_ratio != 0x7)
			sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	}
#endif

#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
	sys_info->freq_qe =  sys_info->freq_systembus;
#else
	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		sys_info->freq_fman[0] = sys_info->freq_systembus;
#endif

#endif /* CONFIG_FSL_CORENET */

#if defined(CONFIG_FSL_LBC)
	uint lcrr_div;
#if defined(CONFIG_SYS_LBC_LCRR)
	/* We will program LCRR to this value later */
	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
		/* If this is corenet based SoC, bit-representation
		 * for four times the clock divider values.
		 */
		lcrr_div *= 4;
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		lcrr_div *= 2;
#endif
		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
	} else {
		/* In case anyone cares what the unknown value is */
		sys_info->freq_localbus = lcrr_div;
	}
#endif

#if defined(CONFIG_FSL_IFC)
	ccr = in_be32(&ifc_regs->ifc_ccr);
	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;

	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
#endif
}


int get_clocks (void)
{
	sys_info_t sys_info;
#ifdef CONFIG_MPC8544
	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint sccr, dfbrg;

	/* set VCO = 4 * BRG */
	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
	sccr = cpm->im_cpm_intctl.sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freq_processor[0];
	gd->bus_clk = sys_info.freq_systembus;
	gd->mem_clk = sys_info.freq_ddrbus;
	gd->arch.lbc_clk = sys_info.freq_localbus;

#ifdef CONFIG_QE
	gd->arch.qe_clk = sys_info.freq_qe;
	gd->arch.brg_clk = gd->arch.qe_clk / 2;
#endif
	/*
	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
	 * there is no pattern that can be used to determine the frequency, so
	 * the only choice is to look up the actual SOC number and use the value
	 * for that SOC. This information is taken from application note
	 * AN2919.
	 */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
	defined(CONFIG_P1022)
	gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
	else
		gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#endif
	gd->arch.i2c2_clk = gd->arch.i2c1_clk;

#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
       defined(CONFIG_P1014)
	gd->arch.sdhc_clk = gd->bus_clk;
#else
	gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2)
	gd->arch.vco_out = 2*sys_info.freq_systembus;
	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	gd->arch.scc_clk = gd->arch.vco_out / 4;
	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
#endif

	if(gd->cpu_clk != 0) return (0);
	else return (1);
}


/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq (ulong dummy)
{
	return gd->mem_clk;
}
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Xianghua Xiao, (X.Xiao@motorola.com)
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	11	*/
	12
	13	#include <common.h>
	14	#include <ppc_asm.tmpl>
a52d2f81	15	#include <linux/compiler.h>
42d1f039	16	#include <asm/processor.h>
ada591d2	17	#include <asm/io.h>
42d1f039	18
d87080b7 WD	19	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	20
ce746fe0 PK	21
	22	#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
	23	#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
	24	#endif
42d1f039 WD	25	/* --------------------------------------------------------------- */
42d1f039 WD	26
997399fa	27	void get_sys_info(sys_info_t *sys_info)
42d1f039	28	{
6d0f6bcf	29	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
800c73c4 KG	30	#ifdef CONFIG_FSL_IFC
	31	struct fsl_ifc ifc_regs = (void )CONFIG_SYS_IFC_ADDR;
	32	u32 ccr;
	33	#endif
39aaca1f KG	34	#ifdef CONFIG_FSL_CORENET
39aaca1f KG	35	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7	36	unsigned int cpu;
ce746fe0 PK	37	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	38	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
	39	#endif
39aaca1f KG	40
	41	const u8 core_cplx_PLL[16] = {
	42	[ 0] = 0, /* CC1 PPL / 1 */
	43	[ 1] = 0, /* CC1 PPL / 2 */
	44	[ 2] = 0, /* CC1 PPL / 4 */
	45	[ 4] = 1, /* CC2 PPL / 1 */
	46	[ 5] = 1, /* CC2 PPL / 2 */
	47	[ 6] = 1, /* CC2 PPL / 4 */
	48	[ 8] = 2, /* CC3 PPL / 1 */
	49	[ 9] = 2, /* CC3 PPL / 2 */
	50	[10] = 2, /* CC3 PPL / 4 */
	51	[12] = 3, /* CC4 PPL / 1 */
	52	[13] = 3, /* CC4 PPL / 2 */
	53	[14] = 3, /* CC4 PPL / 4 */
	54	};
	55
997399fa	56	const u8 core_cplx_pll_div[16] = {
39aaca1f KG	57	[ 0] = 1, /* CC1 PPL / 1 */
	58	[ 1] = 2, /* CC1 PPL / 2 */
	59	[ 2] = 4, /* CC1 PPL / 4 */
	60	[ 4] = 1, /* CC2 PPL / 1 */
	61	[ 5] = 2, /* CC2 PPL / 2 */
	62	[ 6] = 4, /* CC2 PPL / 4 */
	63	[ 8] = 1, /* CC3 PPL / 1 */
	64	[ 9] = 2, /* CC3 PPL / 2 */
	65	[10] = 4, /* CC3 PPL / 4 */
	66	[12] = 1, /* CC4 PPL / 1 */
	67	[13] = 2, /* CC4 PPL / 2 */
	68	[14] = 4, /* CC4 PPL / 4 */
	69	};
ce746fe0 PK	70	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
	71	#if !defined(CONFIG_FM_PLAT_CLK_DIV) \|\| !defined(CONFIG_PME_PLAT_CLK_DIV)
	72	uint rcw_tmp;
	73	#endif
	74	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
39aaca1f	75	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a	76	uint mem_pll_rat;
39aaca1f	77
997399fa	78	sys_info->freq_systembus = sysclk;
b135991a	79	#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
0c12a159	80	uint ddr_refclk_sel;
	81	unsigned int porsr1_sys_clk;
	82	porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
	83	& FSL_DCFG_PORSR1_SYSCLK_MASK;
	84	if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
	85	sys_info->diff_sysclk = 1;
	86	else
	87	sys_info->diff_sysclk = 0;
	88
b135991a PJ	89	/*
	90	* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
	91	* are driven by separate DDR Refclock or single source
	92	* differential clock.
	93	*/
0c12a159	94	ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
b135991a PJ	95	FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
	96	FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
	97	/*
0c12a159	98	* For single source clocking, both ddrclock and sysclock
b135991a PJ	99	* are driven by differential sysclock.
b135991a PJ	100	*/
0c12a159	101	if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
b135991a	102	sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
0c12a159	103	else
b135991a	104	#endif
98ffa190	105	#ifdef CONFIG_DDR_CLK_FREQ
b135991a	106	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
98ffa190	107	#else
b135991a	108	sys_info->freq_ddrbus = sysclk;
98ffa190	109	#endif
39aaca1f	110
997399fa	111	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
f77329cf YS	112	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
	113	FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
	114	& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
c3678b09 YS	115	#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
	116	if (mem_pll_rat == 0) {
	117	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
	118	FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
	119	FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
	120	}
	121	#endif
e88f421e ZRR	122	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
	123	* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
	124	* it uses 6.
	125	*/
	126	#if defined(CONFIG_PPC_T4240) \|\| defined(CONFIG_PPC_T4160)
	127	if (SVR_MAJ(get_svr()) >= 2)
	128	mem_pll_rat *= 2;
	129	#endif
ab48ca1a	130	if (mem_pll_rat > 2)
997399fa	131	sys_info->freq_ddrbus *= mem_pll_rat;
ab48ca1a	132	else
997399fa	133	sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
39aaca1f	134
ce746fe0 PK	135	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
ce746fe0 PK	136	ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
ab48ca1a	137	if (ratio[i] > 4)
ce746fe0	138	freq_c_pll[i] = sysclk * ratio[i];
ab48ca1a	139	else
ce746fe0	140	freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
ab48ca1a	141	}
9a653a98 YS	142	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
9a653a98 YS	143	/*
ce746fe0	144	* As per CHASSIS2 architeture total 12 clusters are posible and
9a653a98	145	* Each cluster has up to 4 cores, sharing the same PLL selection.
ce746fe0 PK	146	* The cluster clock assignment is SoC defined.
	147	*
	148	* Total 4 clock groups are possible with 3 PLLs each.
	149	* as per array indices, clock group A has 0, 1, 2 numbered PLLs &
	150	* clock group B has 3, 4, 6 and so on.
	151	*
	152	* Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
	153	* depends upon the SoC architeture. Same applies to other
	154	* clock groups and clusters.
	155	*
9a653a98	156	*/
fbb9ecf7	157	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	158	int cluster = fsl_qoriq_core_to_cluster(cpu);
f6981439 YS	159	u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
9a653a98	160	& 0xf;
39aaca1f	161	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
ce746fe0	162	cplx_pll += cc_group[cluster] - 1;
997399fa	163	sys_info->freq_processor[cpu] =
ce746fe0	164	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
39aaca1f	165	}
b33bd8cd PK	166	#if defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_B4420) \|\| \
b33bd8cd PK	167	defined(CONFIG_PPC_T2080) \|\| defined(CONFIG_PPC_T2081)
0cb3325c SS	168	#define FM1_CLK_SEL 0xe0000000
	169	#define FM1_CLK_SHIFT 29
	170	#else
9a653a98 YS	171	#define PME_CLK_SEL 0xe0000000
	172	#define PME_CLK_SHIFT 29
	173	#define FM1_CLK_SEL 0x1c000000
	174	#define FM1_CLK_SHIFT 26
0cb3325c	175	#endif
ce746fe0	176	#if !defined(CONFIG_FM_PLAT_CLK_DIV) \|\| !defined(CONFIG_PME_PLAT_CLK_DIV)
9a653a98	177	rcw_tmp = in_be32(&gur->rcwsr[7]);
ce746fe0	178	#endif
9a653a98 YS	179
9a653a98 YS	180	#ifdef CONFIG_SYS_DPAA_PME
ce746fe0	181	#ifndef CONFIG_PME_PLAT_CLK_DIV
9a653a98 YS	182	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
9a653a98 YS	183	case 1:
ce746fe0	184	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
9a653a98 YS	185	break;
9a653a98 YS	186	case 2:
ce746fe0	187	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
9a653a98 YS	188	break;
9a653a98 YS	189	case 3:
ce746fe0	190	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
9a653a98 YS	191	break;
9a653a98 YS	192	case 4:
ce746fe0	193	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
9a653a98 YS	194	break;
9a653a98 YS	195	case 6:
ce746fe0	196	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
9a653a98 YS	197	break;
9a653a98 YS	198	case 7:
ce746fe0	199	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
9a653a98 YS	200	break;
	201	default:
	202	printf("Error: Unknown PME clock select!\n");
	203	case 0:
997399fa	204	sys_info->freq_pme = sys_info->freq_systembus / 2;
9a653a98 YS	205	break;
	206
	207	}
ce746fe0 PK	208	#else
	209	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
	210
	211	#endif
9a653a98 YS	212	#endif
9a653a98 YS	213
990e1a8c	214	#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa	215	sys_info->freq_qman = sys_info->freq_systembus / 2;
990e1a8c HW	216	#endif
990e1a8c HW	217
9a653a98	218	#ifdef CONFIG_SYS_DPAA_FMAN
ce746fe0	219	#ifndef CONFIG_FM_PLAT_CLK_DIV
9a653a98 YS	220	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
9a653a98 YS	221	case 1:
ce746fe0	222	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
9a653a98 YS	223	break;
9a653a98 YS	224	case 2:
ce746fe0	225	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
9a653a98 YS	226	break;
9a653a98 YS	227	case 3:
ce746fe0	228	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
9a653a98 YS	229	break;
9a653a98 YS	230	case 4:
ce746fe0	231	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
9a653a98	232	break;
0cb3325c	233	case 5:
997399fa	234	sys_info->freq_fman[0] = sys_info->freq_systembus;
0cb3325c	235	break;
9a653a98	236	case 6:
ce746fe0	237	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
9a653a98 YS	238	break;
9a653a98 YS	239	case 7:
ce746fe0	240	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
9a653a98 YS	241	break;
	242	default:
	243	printf("Error: Unknown FMan1 clock select!\n");
	244	case 0:
997399fa	245	sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
9a653a98 YS	246	break;
	247	}
	248	#if (CONFIG_SYS_NUM_FMAN) == 2
ce746fe0	249	#ifdef CONFIG_SYS_FM2_CLK
9a653a98 YS	250	#define FM2_CLK_SEL 0x00000038
	251	#define FM2_CLK_SHIFT 3
	252	rcw_tmp = in_be32(&gur->rcwsr[15]);
	253	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	254	case 1:
ce746fe0	255	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
9a653a98 YS	256	break;
9a653a98 YS	257	case 2:
ce746fe0	258	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
9a653a98 YS	259	break;
9a653a98 YS	260	case 3:
ce746fe0	261	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
9a653a98 YS	262	break;
9a653a98 YS	263	case 4:
ce746fe0	264	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
9a653a98	265	break;
c1015c67 SX	266	case 5:
	267	sys_info->freq_fman[1] = sys_info->freq_systembus;
	268	break;
9a653a98	269	case 6:
ce746fe0	270	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
9a653a98 YS	271	break;
9a653a98 YS	272	case 7:
ce746fe0	273	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
9a653a98 YS	274	break;
	275	default:
	276	printf("Error: Unknown FMan2 clock select!\n");
	277	case 0:
997399fa	278	sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
9a653a98 YS	279	break;
9a653a98 YS	280	}
ce746fe0	281	#endif
9a653a98	282	#endif /* CONFIG_SYS_NUM_FMAN == 2 */
ce746fe0 PK	283	#else
	284	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
	285	#endif
	286	#endif
39aaca1f	287
9a653a98 YS	288	#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	289
	290	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	291	u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
f6981439 YS	292	& 0xf;
9a653a98 YS	293	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
9a653a98 YS	294
997399fa	295	sys_info->freq_processor[cpu] =
ce746fe0	296	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
9a653a98	297	}
39aaca1f KG	298	#define PME_CLK_SEL 0x80000000
	299	#define FM1_CLK_SEL 0x40000000
	300	#define FM2_CLK_SEL 0x20000000
b5c8753f KG	301	#define HWA_ASYNC_DIV 0x04000000
	302	#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
	303	#define HWA_CC_PLL 1
4905443f TT	304	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
4905443f TT	305	#define HWA_CC_PLL 2
b5c8753f	306	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5	307	#define HWA_CC_PLL 2
b5c8753f KG	308	#else
	309	#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
	310	#endif
39aaca1f KG	311	rcw_tmp = in_be32(&gur->rcwsr[7]);
	312
	313	#ifdef CONFIG_SYS_DPAA_PME
b5c8753f KG	314	if (rcw_tmp & PME_CLK_SEL) {
b5c8753f KG	315	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	316	sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	317	else
ce746fe0	318	sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	319	} else {
997399fa	320	sys_info->freq_pme = sys_info->freq_systembus / 2;
b5c8753f	321	}
39aaca1f KG	322	#endif
	323
	324	#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f KG	325	if (rcw_tmp & FM1_CLK_SEL) {
b5c8753f KG	326	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	327	sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	328	else
ce746fe0	329	sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	330	} else {
997399fa	331	sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
b5c8753f	332	}
39aaca1f	333	#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f KG	334	if (rcw_tmp & FM2_CLK_SEL) {
b5c8753f KG	335	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	336	sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	337	else
ce746fe0	338	sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	339	} else {
997399fa	340	sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
b5c8753f	341	}
39aaca1f KG	342	#endif
	343	#endif
	344
3e83fc9b	345	#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa	346	sys_info->freq_qman = sys_info->freq_systembus / 2;
3e83fc9b SX	347	#endif
3e83fc9b SX	348
9a653a98 YS	349	#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
9a653a98 YS	350
2a44efeb ZQ	351	#ifdef CONFIG_U_QE
	352	sys_info->freq_qe = sys_info->freq_systembus / 2;
	353	#endif
	354
9a653a98	355	#else /* CONFIG_FSL_CORENET */
997399fa	356	uint plat_ratio, e500_ratio, half_freq_systembus;
2fc7eb0c	357	int i;
b3d7f20f	358	#ifdef CONFIG_QE
a52d2f81	359	__maybe_unused u32 qe_ratio;
b3d7f20f	360	#endif
42d1f039 WD	361
	362	plat_ratio = (gur->porpllsr) & 0x0000003e;
	363	plat_ratio >>= 1;
997399fa	364	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca AF	365
	366	/* Divide before multiply to avoid integer
	367	* overflow for processor speeds above 2GHz */
997399fa	368	half_freq_systembus = sys_info->freq_systembus/2;
0e870980	369	for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c	370	e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
997399fa	371	sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
2fc7eb0c	372	}
a3e77fa5	373
997399fa PK	374	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
997399fa PK	375	sys_info->freq_ddrbus = sys_info->freq_systembus;
d4357932 KG	376
	377	#ifdef CONFIG_DDR_CLK_FREQ
	378	{
c0391111 JJ	379	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	380	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932	381	if (ddr_ratio != 0x7)
997399fa	382	sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
d4357932 KG	383	}
d4357932 KG	384	#endif
ada591d2	385
b3d7f20f	386	#ifdef CONFIG_QE
be7bebea	387	#if defined(CONFIG_P1012) \|\| defined(CONFIG_P1021) \|\| defined(CONFIG_P1025)
997399fa	388	sys_info->freq_qe = sys_info->freq_systembus;
a52d2f81	389	#else
b3d7f20f HW	390	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
b3d7f20f HW	391	>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
997399fa	392	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
b3d7f20f	393	#endif
a52d2f81	394	#endif
b3d7f20f	395
24995d82	396	#ifdef CONFIG_SYS_DPAA_FMAN
997399fa	397	sys_info->freq_fman[0] = sys_info->freq_systembus;
24995d82 HW	398	#endif
	399
	400	#endif /* CONFIG_FSL_CORENET */
	401
beba93ed	402	#if defined(CONFIG_FSL_LBC)
9a653a98	403	uint lcrr_div;
ada591d2 TP	404	#if defined(CONFIG_SYS_LBC_LCRR)
	405	/* We will program LCRR to this value later */
	406	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
	407	#else
f51cdaf1	408	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2 TP	409	#endif
ada591d2 TP	410	if (lcrr_div == 2 \|\| lcrr_div == 4 \|\| lcrr_div == 8) {
0fd2fa6c DL	411	#if defined(CONFIG_FSL_CORENET)
	412	/* If this is corenet based SoC, bit-representation
	413	* for four times the clock divider values.
	414	*/
	415	lcrr_div *= 4;
	416	#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
ada591d2 TP	417	!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
	418	/*
	419	* Yes, the entire PQ38 family use the same
	420	* bit-representation for twice the clock divider values.
	421	*/
	422	lcrr_div *= 2;
	423	#endif
997399fa	424	sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
ada591d2 TP	425	} else {
ada591d2 TP	426	/* In case anyone cares what the unknown value is */
997399fa	427	sys_info->freq_localbus = lcrr_div;
ada591d2	428	}
beba93ed	429	#endif
800c73c4 KG	430
	431	#if defined(CONFIG_FSL_IFC)
	432	ccr = in_be32(&ifc_regs->ifc_ccr);
	433	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
	434
997399fa	435	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
800c73c4	436	#endif
42d1f039 WD	437	}
42d1f039 WD	438
66ed6cca	439
42d1f039 WD	440	int get_clocks (void)
42d1f039 WD	441	{
42d1f039	442	sys_info_t sys_info;
88353a98	443	#ifdef CONFIG_MPC8544
6d0f6bcf	444	volatile ccsr_gur_t gur = (void ) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98	445	#endif
9c4c5ae3	446	#if defined(CONFIG_CPM2)
6d0f6bcf	447	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	448	uint sccr, dfbrg;
	449
	450	/* set VCO = 4 * BRG */
aafeefbd KG	451	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
aafeefbd KG	452	sccr = cpm->im_cpm_intctl.sccr;
42d1f039 WD	453	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	454	#endif
	455	get_sys_info (&sys_info);
997399fa PK	456	gd->cpu_clk = sys_info.freq_processor[0];
	457	gd->bus_clk = sys_info.freq_systembus;
	458	gd->mem_clk = sys_info.freq_ddrbus;
	459	gd->arch.lbc_clk = sys_info.freq_localbus;
88353a98	460
b3d7f20f	461	#ifdef CONFIG_QE
997399fa	462	gd->arch.qe_clk = sys_info.freq_qe;
45bae2e3	463	gd->arch.brg_clk = gd->arch.qe_clk / 2;
b3d7f20f	464	#endif
88353a98 TT	465	/*
	466	* The base clock for I2C depends on the actual SOC. Unfortunately,
	467	* there is no pattern that can be used to determine the frequency, so
	468	* the only choice is to look up the actual SOC number and use the value
	469	* for that SOC. This information is taken from application note
	470	* AN2919.
	471	*/
	472	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
f62b1238 TY	473	defined(CONFIG_MPC8560) \|\| defined(CONFIG_MPC8555) \|\| \
f62b1238 TY	474	defined(CONFIG_P1022)
997399fa	475	gd->arch.i2c1_clk = sys_info.freq_systembus;
88353a98 TT	476	#elif defined(CONFIG_MPC8544)
	477	/*
	478	* On the 8544, the I2C clock is the same as the SEC clock. This can be
	479	* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	480	* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
	481	* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	482	* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	483	*/
	484	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
997399fa	485	gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
42653b82	486	else
997399fa	487	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98 TT	488	#else
88353a98 TT	489	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
997399fa	490	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98	491	#endif
609e6ec3	492	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
943afa22	493
6b9ea08c	494	#if defined(CONFIG_FSL_ESDHC)
7d640e9b PJ	495	#if defined(CONFIG_MPC8569) \|\| defined(CONFIG_P1010) \|\|\
7d640e9b PJ	496	defined(CONFIG_P1014)
e9adeca3	497	gd->arch.sdhc_clk = gd->bus_clk;
7f52ed5e	498	#else
e9adeca3	499	gd->arch.sdhc_clk = gd->bus_clk / 2;
ef50d6c0	500	#endif
7f52ed5e	501	#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0	502
9c4c5ae3	503	#if defined(CONFIG_CPM2)
997399fa	504	gd->arch.vco_out = 2*sys_info.freq_systembus;
748cd059 SG	505	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	506	gd->arch.scc_clk = gd->arch.vco_out / 4;
	507	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
42d1f039 WD	508	#endif
	509
	510	if(gd->cpu_clk != 0) return (0);
	511	else return (1);
	512	}
	513
	514
	515	/********************************************
	516	* get_bus_freq
	517	* return system bus freq in Hz
	518	*********************************************/
	519	ulong get_bus_freq (ulong dummy)
	520	{
a3e77fa5	521	return gd->bus_clk;
42d1f039	522	}
d4357932 KG	523
	524	/********************************************
	525	* get_ddr_freq
	526	* return ddr bus freq in Hz
	527	*********************************************/
	528	ulong get_ddr_freq (ulong dummy)
	529	{
a3e77fa5	530	return gd->mem_clk;
d4357932	531	}