[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

/*
 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;


#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
#define CONFIG_SYS_FSL_NUM_CC_PLLS	6
#endif
/* --------------------------------------------------------------- */

void get_sys_info(sys_info_t *sys_info)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
	u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
	unsigned int cpu;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif

	const u8 core_cplx_PLL[16] = {
		[ 0] = 0,	/* CC1 PPL / 1 */
		[ 1] = 0,	/* CC1 PPL / 2 */
		[ 2] = 0,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 1,	/* CC2 PPL / 2 */
		[ 6] = 1,	/* CC2 PPL / 4 */
		[ 8] = 2,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_pll_div[16] = {
		[ 0] = 1,	/* CC1 PPL / 1 */
		[ 1] = 2,	/* CC1 PPL / 2 */
		[ 2] = 4,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 2,	/* CC2 PPL / 2 */
		[ 6] = 4,	/* CC2 PPL / 4 */
		[ 8] = 1,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};
	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
	uint rcw_tmp;
#endif
	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
	uint mem_pll_rat;

	sys_info->freq_systembus = sysclk;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
	uint ddr_refclk_sel;
	unsigned int porsr1_sys_clk;
	porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
						& FSL_DCFG_PORSR1_SYSCLK_MASK;
	if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
		sys_info->diff_sysclk = 1;
	else
		sys_info->diff_sysclk = 0;

	/*
	 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
	 * are driven by separate DDR Refclock or single source
	 * differential clock.
	 */
	ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
		      FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
	/*
	 * For single source clocking, both ddrclock and sysclock
	 * are driven by differential sysclock.
	 */
	if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
		sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
	else
#endif
#ifdef CONFIG_DDR_CLK_FREQ
		sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#else
		sys_info->freq_ddrbus = sysclk;
#endif

	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
	if (mem_pll_rat == 0) {
		mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
	}
#endif
	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
	 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
	 * it uses 6.
	 */
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
	defined(CONFIG_PPC_T4080)
	if (SVR_MAJ(get_svr()) >= 2)
		mem_pll_rat *= 2;
#endif
	if (mem_pll_rat > 2)
		sys_info->freq_ddrbus *= mem_pll_rat;
	else
		sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;

	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
		if (ratio[i] > 4)
			freq_c_pll[i] = sysclk * ratio[i];
		else
			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
	}
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	/*
	 * As per CHASSIS2 architeture total 12 clusters are posible and
	 * Each cluster has up to 4 cores, sharing the same PLL selection.
	 * The cluster clock assignment is SoC defined.
	 *
	 * Total 4 clock groups are possible with 3 PLLs each.
	 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
	 * clock group B has 3, 4, 6 and so on.
	 *
	 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
	 * depends upon the SoC architeture. Same applies to other
	 * clock groups and clusters.
	 *
	 */
	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		int cluster = fsl_qoriq_core_to_cluster(cpu);
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
		cplx_pll += cc_group[cluster] - 1;
		sys_info->freq_processor[cpu] =
			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}
#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
	defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL	0xe0000000
#define FM1_CLK_SHIFT	29
#else
#define PME_CLK_SEL	0xe0000000
#define PME_CLK_SHIFT	29
#define FM1_CLK_SEL	0x1c000000
#define FM1_CLK_SHIFT	26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
	rcw_tmp = in_be32(&gur->rcwsr[7]);
#endif

#ifdef CONFIG_SYS_DPAA_PME
#ifndef CONFIG_PME_PLAT_CLK_DIV
	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
	case 1:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
		break;
	case 2:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
		break;
	case 3:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
		break;
	case 4:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
		break;
	case 6:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
		break;
	case 7:
		sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
		break;
	default:
		printf("Error: Unknown PME clock select!\n");
	case 0:
		sys_info->freq_pme = sys_info->freq_systembus / 2;
		break;

	}
#else
	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;

#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_FM_PLAT_CLK_DIV
	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
	case 1:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
		break;
	case 2:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
		break;
	case 3:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
		break;
	case 4:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
		break;
	case 5:
		sys_info->freq_fman[0] = sys_info->freq_systembus;
		break;
	case 6:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
		break;
	case 7:
		sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
		break;
	default:
		printf("Error: Unknown FMan1 clock select!\n");
	case 0:
		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
		break;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
#ifdef CONFIG_SYS_FM2_CLK
#define FM2_CLK_SEL	0x00000038
#define FM2_CLK_SHIFT	3
	rcw_tmp = in_be32(&gur->rcwsr[15]);
	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	case 1:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
		break;
	case 2:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
		break;
	case 3:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
		break;
	case 4:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
		break;
	case 5:
		sys_info->freq_fman[1] = sys_info->freq_systembus;
		break;
	case 6:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
		break;
	case 7:
		sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
		break;
	default:
		printf("Error: Unknown FMan2 clock select!\n");
	case 0:
		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
		break;
	}
#endif
#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
#else
	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
#endif
#endif

#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];

		sys_info->freq_processor[cpu] =
			 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
	}
#define PME_CLK_SEL	0x80000000
#define FM1_CLK_SEL	0x40000000
#define FM2_CLK_SEL	0x20000000
#define HWA_ASYNC_DIV	0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL	1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
#define HWA_CC_PLL	2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL	2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	if (rcw_tmp & PME_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_pme = sys_info->freq_systembus / 2;
	}
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	if (rcw_tmp & FM1_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
	if (rcw_tmp & FM2_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
		else
			sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
	} else {
		sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
	}
#endif
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sys_info->freq_qman = sys_info->freq_systembus / 2;
#endif

#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

#ifdef CONFIG_U_QE
	sys_info->freq_qe =  sys_info->freq_systembus / 2;
#endif

#else /* CONFIG_FSL_CORENET */
	uint plat_ratio, e500_ratio, half_freq_systembus;
	int i;
#ifdef CONFIG_QE
	__maybe_unused u32 qe_ratio;
#endif

	plat_ratio = (gur->porpllsr) & 0x0000003e;
	plat_ratio >>= 1;
	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;

	/* Divide before multiply to avoid integer
	 * overflow for processor speeds above 2GHz */
	half_freq_systembus = sys_info->freq_systembus/2;
	for (i = 0; i < cpu_numcores(); i++) {
		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
		sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
	}

	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
	sys_info->freq_ddrbus = sys_info->freq_systembus;

#ifdef CONFIG_DDR_CLK_FREQ
	{
		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
		if (ddr_ratio != 0x7)
			sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	}
#endif

#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
	sys_info->freq_qe =  sys_info->freq_systembus;
#else
	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		sys_info->freq_fman[0] = sys_info->freq_systembus;
#endif

#endif /* CONFIG_FSL_CORENET */

#if defined(CONFIG_FSL_LBC)
	uint lcrr_div;
#if defined(CONFIG_SYS_LBC_LCRR)
	/* We will program LCRR to this value later */
	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
		/* If this is corenet based SoC, bit-representation
		 * for four times the clock divider values.
		 */
		lcrr_div *= 4;
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		lcrr_div *= 2;
#endif
		sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
	} else {
		/* In case anyone cares what the unknown value is */
		sys_info->freq_localbus = lcrr_div;
	}
#endif

#if defined(CONFIG_FSL_IFC)
	ccr = in_be32(&ifc_regs->ifc_ccr);
	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;

	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
#endif
}


int get_clocks (void)
{
	sys_info_t sys_info;
#ifdef CONFIG_MPC8544
	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint sccr, dfbrg;

	/* set VCO = 4 * BRG */
	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
	sccr = cpm->im_cpm_intctl.sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freq_processor[0];
	gd->bus_clk = sys_info.freq_systembus;
	gd->mem_clk = sys_info.freq_ddrbus;
	gd->arch.lbc_clk = sys_info.freq_localbus;

#ifdef CONFIG_QE
	gd->arch.qe_clk = sys_info.freq_qe;
	gd->arch.brg_clk = gd->arch.qe_clk / 2;
#endif
	/*
	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
	 * there is no pattern that can be used to determine the frequency, so
	 * the only choice is to look up the actual SOC number and use the value
	 * for that SOC. This information is taken from application note
	 * AN2919.
	 */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
	defined(CONFIG_P1022)
	gd->arch.i2c1_clk = sys_info.freq_systembus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
	else
		gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
#endif
	gd->arch.i2c2_clk = gd->arch.i2c1_clk;

#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
       defined(CONFIG_P1014)
	gd->arch.sdhc_clk = gd->bus_clk;
#else
	gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2)
	gd->arch.vco_out = 2*sys_info.freq_systembus;
	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	gd->arch.scc_clk = gd->arch.vco_out / 4;
	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
#endif

	if(gd->cpu_clk != 0) return (0);
	else return (1);
}


/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq (ulong dummy)
{
	return gd->mem_clk;
}
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Xianghua Xiao, (X.Xiao@motorola.com)
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	11	*/
	12
	13	#include <common.h>
	14	#include <ppc_asm.tmpl>
a52d2f81	15	#include <linux/compiler.h>
42d1f039	16	#include <asm/processor.h>
ada591d2	17	#include <asm/io.h>
42d1f039	18
d87080b7 WD	19	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	20
ce746fe0 PK	21
	22	#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
	23	#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
	24	#endif
42d1f039 WD	25	/* --------------------------------------------------------------- */
42d1f039 WD	26
997399fa	27	void get_sys_info(sys_info_t *sys_info)
42d1f039	28	{
6d0f6bcf	29	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
800c73c4 KG	30	#ifdef CONFIG_FSL_IFC
	31	struct fsl_ifc ifc_regs = (void )CONFIG_SYS_IFC_ADDR;
	32	u32 ccr;
	33	#endif
39aaca1f KG	34	#ifdef CONFIG_FSL_CORENET
39aaca1f KG	35	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7	36	unsigned int cpu;
ce746fe0 PK	37	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	38	int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
	39	#endif
39aaca1f KG	40
	41	const u8 core_cplx_PLL[16] = {
	42	[ 0] = 0, /* CC1 PPL / 1 */
	43	[ 1] = 0, /* CC1 PPL / 2 */
	44	[ 2] = 0, /* CC1 PPL / 4 */
	45	[ 4] = 1, /* CC2 PPL / 1 */
	46	[ 5] = 1, /* CC2 PPL / 2 */
	47	[ 6] = 1, /* CC2 PPL / 4 */
	48	[ 8] = 2, /* CC3 PPL / 1 */
	49	[ 9] = 2, /* CC3 PPL / 2 */
	50	[10] = 2, /* CC3 PPL / 4 */
	51	[12] = 3, /* CC4 PPL / 1 */
	52	[13] = 3, /* CC4 PPL / 2 */
	53	[14] = 3, /* CC4 PPL / 4 */
	54	};
	55
997399fa	56	const u8 core_cplx_pll_div[16] = {
39aaca1f KG	57	[ 0] = 1, /* CC1 PPL / 1 */
	58	[ 1] = 2, /* CC1 PPL / 2 */
	59	[ 2] = 4, /* CC1 PPL / 4 */
	60	[ 4] = 1, /* CC2 PPL / 1 */
	61	[ 5] = 2, /* CC2 PPL / 2 */
	62	[ 6] = 4, /* CC2 PPL / 4 */
	63	[ 8] = 1, /* CC3 PPL / 1 */
	64	[ 9] = 2, /* CC3 PPL / 2 */
	65	[10] = 4, /* CC3 PPL / 4 */
	66	[12] = 1, /* CC4 PPL / 1 */
	67	[13] = 2, /* CC4 PPL / 2 */
	68	[14] = 4, /* CC4 PPL / 4 */
	69	};
ce746fe0 PK	70	uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
	71	#if !defined(CONFIG_FM_PLAT_CLK_DIV) \|\| !defined(CONFIG_PME_PLAT_CLK_DIV)
	72	uint rcw_tmp;
	73	#endif
	74	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
39aaca1f	75	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a	76	uint mem_pll_rat;
39aaca1f	77
997399fa	78	sys_info->freq_systembus = sysclk;
b135991a	79	#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
0c12a159	80	uint ddr_refclk_sel;
	81	unsigned int porsr1_sys_clk;
	82	porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
	83	& FSL_DCFG_PORSR1_SYSCLK_MASK;
	84	if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
	85	sys_info->diff_sysclk = 1;
	86	else
	87	sys_info->diff_sysclk = 0;
	88
b135991a PJ	89	/*
	90	* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
	91	* are driven by separate DDR Refclock or single source
	92	* differential clock.
	93	*/
0c12a159	94	ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
b135991a PJ	95	FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
	96	FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
	97	/*
0c12a159	98	* For single source clocking, both ddrclock and sysclock
b135991a PJ	99	* are driven by differential sysclock.
b135991a PJ	100	*/
0c12a159	101	if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
b135991a	102	sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
0c12a159	103	else
b135991a	104	#endif
98ffa190	105	#ifdef CONFIG_DDR_CLK_FREQ
b135991a	106	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
98ffa190	107	#else
b135991a	108	sys_info->freq_ddrbus = sysclk;
98ffa190	109	#endif
39aaca1f	110
997399fa	111	sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
f77329cf YS	112	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
	113	FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
	114	& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
c3678b09 YS	115	#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
	116	if (mem_pll_rat == 0) {
	117	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
	118	FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
	119	FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
	120	}
	121	#endif
e88f421e ZRR	122	/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
	123	* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
	124	* it uses 6.
	125	*/
5122dfae SL	126	#if defined(CONFIG_PPC_T4240) \|\| defined(CONFIG_PPC_T4160) \|\| \
5122dfae SL	127	defined(CONFIG_PPC_T4080)
e88f421e ZRR	128	if (SVR_MAJ(get_svr()) >= 2)
	129	mem_pll_rat *= 2;
	130	#endif
ab48ca1a	131	if (mem_pll_rat > 2)
997399fa	132	sys_info->freq_ddrbus *= mem_pll_rat;
ab48ca1a	133	else
997399fa	134	sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
39aaca1f	135
ce746fe0 PK	136	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
ce746fe0 PK	137	ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
ab48ca1a	138	if (ratio[i] > 4)
ce746fe0	139	freq_c_pll[i] = sysclk * ratio[i];
ab48ca1a	140	else
ce746fe0	141	freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
ab48ca1a	142	}
9a653a98 YS	143	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
9a653a98 YS	144	/*
ce746fe0	145	* As per CHASSIS2 architeture total 12 clusters are posible and
9a653a98	146	* Each cluster has up to 4 cores, sharing the same PLL selection.
ce746fe0 PK	147	* The cluster clock assignment is SoC defined.
	148	*
	149	* Total 4 clock groups are possible with 3 PLLs each.
	150	* as per array indices, clock group A has 0, 1, 2 numbered PLLs &
	151	* clock group B has 3, 4, 6 and so on.
	152	*
	153	* Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
	154	* depends upon the SoC architeture. Same applies to other
	155	* clock groups and clusters.
	156	*
9a653a98	157	*/
fbb9ecf7	158	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	159	int cluster = fsl_qoriq_core_to_cluster(cpu);
f6981439 YS	160	u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
9a653a98	161	& 0xf;
39aaca1f	162	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
ce746fe0	163	cplx_pll += cc_group[cluster] - 1;
997399fa	164	sys_info->freq_processor[cpu] =
ce746fe0	165	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
39aaca1f	166	}
b33bd8cd PK	167	#if defined(CONFIG_PPC_B4860) \|\| defined(CONFIG_PPC_B4420) \|\| \
b33bd8cd PK	168	defined(CONFIG_PPC_T2080) \|\| defined(CONFIG_PPC_T2081)
0cb3325c SS	169	#define FM1_CLK_SEL 0xe0000000
	170	#define FM1_CLK_SHIFT 29
	171	#else
9a653a98 YS	172	#define PME_CLK_SEL 0xe0000000
	173	#define PME_CLK_SHIFT 29
	174	#define FM1_CLK_SEL 0x1c000000
	175	#define FM1_CLK_SHIFT 26
0cb3325c	176	#endif
ce746fe0	177	#if !defined(CONFIG_FM_PLAT_CLK_DIV) \|\| !defined(CONFIG_PME_PLAT_CLK_DIV)
9a653a98	178	rcw_tmp = in_be32(&gur->rcwsr[7]);
ce746fe0	179	#endif
9a653a98 YS	180
9a653a98 YS	181	#ifdef CONFIG_SYS_DPAA_PME
ce746fe0	182	#ifndef CONFIG_PME_PLAT_CLK_DIV
9a653a98 YS	183	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
9a653a98 YS	184	case 1:
ce746fe0	185	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
9a653a98 YS	186	break;
9a653a98 YS	187	case 2:
ce746fe0	188	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
9a653a98 YS	189	break;
9a653a98 YS	190	case 3:
ce746fe0	191	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
9a653a98 YS	192	break;
9a653a98 YS	193	case 4:
ce746fe0	194	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
9a653a98 YS	195	break;
9a653a98 YS	196	case 6:
ce746fe0	197	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
9a653a98 YS	198	break;
9a653a98 YS	199	case 7:
ce746fe0	200	sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
9a653a98 YS	201	break;
	202	default:
	203	printf("Error: Unknown PME clock select!\n");
	204	case 0:
997399fa	205	sys_info->freq_pme = sys_info->freq_systembus / 2;
9a653a98 YS	206	break;
	207
	208	}
ce746fe0 PK	209	#else
	210	sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
	211
	212	#endif
9a653a98 YS	213	#endif
9a653a98 YS	214
990e1a8c	215	#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa	216	sys_info->freq_qman = sys_info->freq_systembus / 2;
990e1a8c HW	217	#endif
990e1a8c HW	218
9a653a98	219	#ifdef CONFIG_SYS_DPAA_FMAN
ce746fe0	220	#ifndef CONFIG_FM_PLAT_CLK_DIV
9a653a98 YS	221	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
9a653a98 YS	222	case 1:
ce746fe0	223	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
9a653a98 YS	224	break;
9a653a98 YS	225	case 2:
ce746fe0	226	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
9a653a98 YS	227	break;
9a653a98 YS	228	case 3:
ce746fe0	229	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
9a653a98 YS	230	break;
9a653a98 YS	231	case 4:
ce746fe0	232	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
9a653a98	233	break;
0cb3325c	234	case 5:
997399fa	235	sys_info->freq_fman[0] = sys_info->freq_systembus;
0cb3325c	236	break;
9a653a98	237	case 6:
ce746fe0	238	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
9a653a98 YS	239	break;
9a653a98 YS	240	case 7:
ce746fe0	241	sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
9a653a98 YS	242	break;
	243	default:
	244	printf("Error: Unknown FMan1 clock select!\n");
	245	case 0:
997399fa	246	sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
9a653a98 YS	247	break;
	248	}
	249	#if (CONFIG_SYS_NUM_FMAN) == 2
ce746fe0	250	#ifdef CONFIG_SYS_FM2_CLK
9a653a98 YS	251	#define FM2_CLK_SEL 0x00000038
	252	#define FM2_CLK_SHIFT 3
	253	rcw_tmp = in_be32(&gur->rcwsr[15]);
	254	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	255	case 1:
ce746fe0	256	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
9a653a98 YS	257	break;
9a653a98 YS	258	case 2:
ce746fe0	259	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
9a653a98 YS	260	break;
9a653a98 YS	261	case 3:
ce746fe0	262	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
9a653a98 YS	263	break;
9a653a98 YS	264	case 4:
ce746fe0	265	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
9a653a98	266	break;
c1015c67 SX	267	case 5:
	268	sys_info->freq_fman[1] = sys_info->freq_systembus;
	269	break;
9a653a98	270	case 6:
ce746fe0	271	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
9a653a98 YS	272	break;
9a653a98 YS	273	case 7:
ce746fe0	274	sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
9a653a98 YS	275	break;
	276	default:
	277	printf("Error: Unknown FMan2 clock select!\n");
	278	case 0:
997399fa	279	sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
9a653a98 YS	280	break;
9a653a98 YS	281	}
ce746fe0	282	#endif
9a653a98	283	#endif /* CONFIG_SYS_NUM_FMAN == 2 */
ce746fe0 PK	284	#else
	285	sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
	286	#endif
	287	#endif
39aaca1f	288
9a653a98 YS	289	#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	290
	291	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
f6981439 YS	292	u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
f6981439 YS	293	& 0xf;
9a653a98 YS	294	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
9a653a98 YS	295
997399fa	296	sys_info->freq_processor[cpu] =
ce746fe0	297	freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
9a653a98	298	}
39aaca1f KG	299	#define PME_CLK_SEL 0x80000000
	300	#define FM1_CLK_SEL 0x40000000
	301	#define FM2_CLK_SEL 0x20000000
b5c8753f KG	302	#define HWA_ASYNC_DIV 0x04000000
	303	#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
	304	#define HWA_CC_PLL 1
4905443f TT	305	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
4905443f TT	306	#define HWA_CC_PLL 2
b5c8753f	307	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5	308	#define HWA_CC_PLL 2
b5c8753f KG	309	#else
	310	#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
	311	#endif
39aaca1f KG	312	rcw_tmp = in_be32(&gur->rcwsr[7]);
	313
	314	#ifdef CONFIG_SYS_DPAA_PME
b5c8753f KG	315	if (rcw_tmp & PME_CLK_SEL) {
b5c8753f KG	316	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	317	sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	318	else
ce746fe0	319	sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	320	} else {
997399fa	321	sys_info->freq_pme = sys_info->freq_systembus / 2;
b5c8753f	322	}
39aaca1f KG	323	#endif
	324
	325	#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f KG	326	if (rcw_tmp & FM1_CLK_SEL) {
b5c8753f KG	327	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	328	sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	329	else
ce746fe0	330	sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	331	} else {
997399fa	332	sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
b5c8753f	333	}
39aaca1f	334	#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f KG	335	if (rcw_tmp & FM2_CLK_SEL) {
b5c8753f KG	336	if (rcw_tmp & HWA_ASYNC_DIV)
ce746fe0	337	sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
b5c8753f	338	else
ce746fe0	339	sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
b5c8753f	340	} else {
997399fa	341	sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
b5c8753f	342	}
39aaca1f KG	343	#endif
	344	#endif
	345
3e83fc9b	346	#ifdef CONFIG_SYS_DPAA_QBMAN
997399fa	347	sys_info->freq_qman = sys_info->freq_systembus / 2;
3e83fc9b SX	348	#endif
3e83fc9b SX	349
9a653a98 YS	350	#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
9a653a98 YS	351
2a44efeb ZQ	352	#ifdef CONFIG_U_QE
	353	sys_info->freq_qe = sys_info->freq_systembus / 2;
	354	#endif
	355
9a653a98	356	#else /* CONFIG_FSL_CORENET */
997399fa	357	uint plat_ratio, e500_ratio, half_freq_systembus;
2fc7eb0c	358	int i;
b3d7f20f	359	#ifdef CONFIG_QE
a52d2f81	360	__maybe_unused u32 qe_ratio;
b3d7f20f	361	#endif
42d1f039 WD	362
	363	plat_ratio = (gur->porpllsr) & 0x0000003e;
	364	plat_ratio >>= 1;
997399fa	365	sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca AF	366
	367	/* Divide before multiply to avoid integer
	368	* overflow for processor speeds above 2GHz */
997399fa	369	half_freq_systembus = sys_info->freq_systembus/2;
0e870980	370	for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c	371	e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
997399fa	372	sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
2fc7eb0c	373	}
a3e77fa5	374
997399fa PK	375	/* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
997399fa PK	376	sys_info->freq_ddrbus = sys_info->freq_systembus;
d4357932 KG	377
	378	#ifdef CONFIG_DDR_CLK_FREQ
	379	{
c0391111 JJ	380	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	381	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932	382	if (ddr_ratio != 0x7)
997399fa	383	sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
d4357932 KG	384	}
d4357932 KG	385	#endif
ada591d2	386
b3d7f20f	387	#ifdef CONFIG_QE
be7bebea	388	#if defined(CONFIG_P1012) \|\| defined(CONFIG_P1021) \|\| defined(CONFIG_P1025)
997399fa	389	sys_info->freq_qe = sys_info->freq_systembus;
a52d2f81	390	#else
b3d7f20f HW	391	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
b3d7f20f HW	392	>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
997399fa	393	sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
b3d7f20f	394	#endif
a52d2f81	395	#endif
b3d7f20f	396
24995d82	397	#ifdef CONFIG_SYS_DPAA_FMAN
997399fa	398	sys_info->freq_fman[0] = sys_info->freq_systembus;
24995d82 HW	399	#endif
	400
	401	#endif /* CONFIG_FSL_CORENET */
	402
beba93ed	403	#if defined(CONFIG_FSL_LBC)
9a653a98	404	uint lcrr_div;
ada591d2 TP	405	#if defined(CONFIG_SYS_LBC_LCRR)
	406	/* We will program LCRR to this value later */
	407	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
	408	#else
f51cdaf1	409	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2 TP	410	#endif
ada591d2 TP	411	if (lcrr_div == 2 \|\| lcrr_div == 4 \|\| lcrr_div == 8) {
0fd2fa6c DL	412	#if defined(CONFIG_FSL_CORENET)
	413	/* If this is corenet based SoC, bit-representation
	414	* for four times the clock divider values.
	415	*/
	416	lcrr_div *= 4;
	417	#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
ada591d2 TP	418	!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
	419	/*
	420	* Yes, the entire PQ38 family use the same
	421	* bit-representation for twice the clock divider values.
	422	*/
	423	lcrr_div *= 2;
	424	#endif
997399fa	425	sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
ada591d2 TP	426	} else {
ada591d2 TP	427	/* In case anyone cares what the unknown value is */
997399fa	428	sys_info->freq_localbus = lcrr_div;
ada591d2	429	}
beba93ed	430	#endif
800c73c4 KG	431
	432	#if defined(CONFIG_FSL_IFC)
	433	ccr = in_be32(&ifc_regs->ifc_ccr);
	434	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
	435
997399fa	436	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
800c73c4	437	#endif
42d1f039 WD	438	}
42d1f039 WD	439
66ed6cca	440
42d1f039 WD	441	int get_clocks (void)
42d1f039 WD	442	{
42d1f039	443	sys_info_t sys_info;
88353a98	444	#ifdef CONFIG_MPC8544
6d0f6bcf	445	volatile ccsr_gur_t gur = (void ) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98	446	#endif
9c4c5ae3	447	#if defined(CONFIG_CPM2)
6d0f6bcf	448	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	449	uint sccr, dfbrg;
	450
	451	/* set VCO = 4 * BRG */
aafeefbd KG	452	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
aafeefbd KG	453	sccr = cpm->im_cpm_intctl.sccr;
42d1f039 WD	454	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	455	#endif
	456	get_sys_info (&sys_info);
997399fa PK	457	gd->cpu_clk = sys_info.freq_processor[0];
	458	gd->bus_clk = sys_info.freq_systembus;
	459	gd->mem_clk = sys_info.freq_ddrbus;
	460	gd->arch.lbc_clk = sys_info.freq_localbus;
88353a98	461
b3d7f20f	462	#ifdef CONFIG_QE
997399fa	463	gd->arch.qe_clk = sys_info.freq_qe;
45bae2e3	464	gd->arch.brg_clk = gd->arch.qe_clk / 2;
b3d7f20f	465	#endif
88353a98 TT	466	/*
	467	* The base clock for I2C depends on the actual SOC. Unfortunately,
	468	* there is no pattern that can be used to determine the frequency, so
	469	* the only choice is to look up the actual SOC number and use the value
	470	* for that SOC. This information is taken from application note
	471	* AN2919.
	472	*/
	473	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
f62b1238 TY	474	defined(CONFIG_MPC8560) \|\| defined(CONFIG_MPC8555) \|\| \
f62b1238 TY	475	defined(CONFIG_P1022)
997399fa	476	gd->arch.i2c1_clk = sys_info.freq_systembus;
88353a98 TT	477	#elif defined(CONFIG_MPC8544)
	478	/*
	479	* On the 8544, the I2C clock is the same as the SEC clock. This can be
	480	* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	481	* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
	482	* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	483	* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	484	*/
	485	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
997399fa	486	gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
42653b82	487	else
997399fa	488	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98 TT	489	#else
88353a98 TT	490	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
997399fa	491	gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
88353a98	492	#endif
609e6ec3	493	gd->arch.i2c2_clk = gd->arch.i2c1_clk;
943afa22	494
6b9ea08c	495	#if defined(CONFIG_FSL_ESDHC)
7d640e9b PJ	496	#if defined(CONFIG_MPC8569) \|\| defined(CONFIG_P1010) \|\|\
7d640e9b PJ	497	defined(CONFIG_P1014)
e9adeca3	498	gd->arch.sdhc_clk = gd->bus_clk;
7f52ed5e	499	#else
e9adeca3	500	gd->arch.sdhc_clk = gd->bus_clk / 2;
ef50d6c0	501	#endif
7f52ed5e	502	#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0	503
9c4c5ae3	504	#if defined(CONFIG_CPM2)
997399fa	505	gd->arch.vco_out = 2*sys_info.freq_systembus;
748cd059 SG	506	gd->arch.cpm_clk = gd->arch.vco_out / 2;
	507	gd->arch.scc_clk = gd->arch.vco_out / 4;
	508	gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
42d1f039 WD	509	#endif
	510
	511	if(gd->cpu_clk != 0) return (0);
	512	else return (1);
	513	}
	514
	515
	516	/********************************************
	517	* get_bus_freq
	518	* return system bus freq in Hz
	519	*********************************************/
	520	ulong get_bus_freq (ulong dummy)
	521	{
a3e77fa5	522	return gd->bus_clk;
42d1f039	523	}
d4357932 KG	524
	525	/********************************************
	526	* get_ddr_freq
	527	* return ddr bus freq in Hz
	528	*********************************************/
	529	ulong get_ddr_freq (ulong dummy)
	530	{
a3e77fa5	531	return gd->mem_clk;
d4357932	532	}