[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / cpu.c

/*
 * (C) Copyright 2000-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * CPU specific code
 *
 * written or collected and sometimes rewritten by
 * Magnus Damm <damm@bitsmart.com>
 *
 * minor modifications by
 * Wolfgang Denk <wd@denx.de>
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <asm/ppc4xx.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

void board_reset(void);

/*
 * To provide an interface to detect CPU number for boards that support
 * more then one CPU, we implement the "weak" default functions here.
 *
 * Returns CPU number
 */
int __get_cpu_num(void)
{
	return NA_OR_UNKNOWN_CPU;
}
int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));

#if defined(CONFIG_PCI)
#if defined(CONFIG_405GP) || \
    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)

#define PCI_ASYNC

static int pci_async_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	unsigned long val;

	mfsdr(SDR0_SDSTP1, val);
	return (val & SDR0_SDSTP1_PAME_MASK);
#endif
}
#endif
#endif /* CONFIG_PCI */

#if defined(CONFIG_PCI) && \
    !defined(CONFIG_405) && !defined(CONFIG_405EX)
int pci_arbiter_enabled(void)
{
#if defined(CONFIG_405GP)
	return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_405EP)
	return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
#endif

#if defined(CONFIG_440GP)
	return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	unsigned long val;

	mfsdr(SDR0_XCR0, val);
	return (val & SDR0_XCR0_PAE_MASK);
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	unsigned long val;

	mfsdr(SDR0_PCI0, val);
	return (val & SDR0_PCI0_PAE_MASK);
#endif
}
#endif

#if defined(CONFIG_405EP)
#define I2C_BOOTROM

static int i2c_bootrom_enabled(void)
{
#if defined(CONFIG_405EP)
	return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
#else
	unsigned long val;

	mfsdr(SDR0_SDCS0, val);
	return (val & SDR0_SDCS_SDD);
#endif
}
#endif

#if defined(CONFIG_440GX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (16 bits)",
	"EBC (8 bits)",
	"EBC (32 bits)",
	"EBC (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"Reserved",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
#endif

#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define SDR0_PINSTP_SHIFT	30
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
#endif

#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"PCI",
	"NAND (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"I2C (Addr 0x54)",
	"PCI",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"PCI",
	"I2C (Addr 0x54)",
	"PCI",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"PCI",
	"PCI",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",	/* A8 */
	"I2C (Addr 0x52)",	/* A4 */
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
#endif

#if defined(CONFIG_460SX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (32 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",      /* A8 */
	"I2C (Addr 0x52)",      /* A4 */
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
#endif

#if defined(CONFIG_405EZ)
#define SDR0_PINSTP_SHIFT	28
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"SPI (fast)",
	"NAND (512 page, 4 addr cycle)",
	"I2C (Addr 0x50)",
	"EBC (32 bits)",
	"I2C (Addr 0x50)",
	"NAND (2K page, 5 addr cycle)",
	"I2C (Addr 0x50)",
	"EBC (16 bits)",
	"Reserved",
	"NAND (2K page, 4 addr cycle)",
	"I2C (Addr 0x50)",
	"NAND (512 page, 3 addr cycle)",
	"I2C (Addr 0x50)",
	"SPI (slow)",
	"I2C (Addr 0x50)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
				 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
#endif

#if defined(CONFIG_405EX)
#define SDR0_PINSTP_SHIFT	29
static char *bootstrap_str[] = {
	"EBC (8 bits)",
	"EBC (16 bits)",
	"EBC (16 bits)",
	"NAND (8 bits)",
	"NAND (8 bits)",
	"I2C (Addr 0x54)",
	"EBC (8 bits)",
	"I2C (Addr 0x52)",
};
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
#endif

#if defined(SDR0_PINSTP_SHIFT)
static int bootstrap_option(void)
{
	unsigned long val;

	mfsdr(SDR0_PINSTP, val);
	return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
}
#endif /* SDR0_PINSTP_SHIFT */


#if defined(CONFIG_440GP)
static int do_chip_reset (unsigned long sys0, unsigned long sys1)
{
	/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
	 * reset.
	 */
	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000);	/* Set SWE */
	mtdcr (CPC0_SYS0, sys0);
	mtdcr (CPC0_SYS1, sys1);
	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000);	/* Clr SWE */
	mtspr (SPRN_DBCR0, 0x20000000);	/* Reset the chip */

	return 1;
}
#endif /* CONFIG_440GP */


int checkcpu (void)
{
#if !defined(CONFIG_405)	/* not used on Xilinx 405 FPGA implementations */
	uint pvr = get_pvr();
	ulong clock = gd->cpu_clk;
	char buf[32];
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
	u32 reg;
#endif

	char addstr[64] = "";
	sys_info_t sys_info;
	int cpu_num;

	cpu_num = get_cpu_num();
	if (cpu_num >= 0)
		printf("CPU%d:  ", cpu_num);
	else
		puts("CPU:   ");

	get_sys_info(&sys_info);

#if defined(CONFIG_XILINX_440)
	puts("IBM PowerPC ");
#else
	puts("AMCC PowerPC ");
#endif

	switch (pvr) {

#if !defined(CONFIG_440)
	case PVR_405GP_RB:
		puts("405GP Rev. B");
		break;

	case PVR_405GP_RC:
		puts("405GP Rev. C");
		break;

	case PVR_405GP_RD:
		puts("405GP Rev. D");
		break;

	case PVR_405GP_RE:
		puts("405GP Rev. E");
		break;

	case PVR_405GPR_RB:
		puts("405GPr Rev. B");
		break;

	case PVR_405EP_RB:
		puts("405EP Rev. B");
		break;

	case PVR_405EZ_RA:
		puts("405EZ Rev. A");
		break;

	case PVR_405EX1_RA:
		puts("405EX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EXR2_RA:
		puts("405EXr Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EX1_RC:
		puts("405EX Rev. C");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EX2_RC:
		puts("405EX Rev. C");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EXR1_RC:
		puts("405EXr Rev. C");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EXR2_RC:
		puts("405EXr Rev. C");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EX1_RD:
		puts("405EX Rev. D");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EX2_RD:
		puts("405EX Rev. D");
		strcpy(addstr, "No Security support");
		break;

	case PVR_405EXR1_RD:
		puts("405EXr Rev. D");
		strcpy(addstr, "Security support");
		break;

	case PVR_405EXR2_RD:
		puts("405EXr Rev. D");
		strcpy(addstr, "No Security support");
		break;

#else /* CONFIG_440 */

#if defined(CONFIG_440GP)
	case PVR_440GP_RB:
		puts("440GP Rev. B");
		/* See errata 1.12: CHIP_4 */
		if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
		    (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
			puts (  "\n\t CPC0_SYSx DCRs corrupted. "
				"Resetting chip ...\n");
			udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
			do_chip_reset ( mfdcr(CPC0_STRP0),
					mfdcr(CPC0_STRP1) );
		}
		break;

	case PVR_440GP_RC:
		puts("440GP Rev. C");
		break;
#endif /* CONFIG_440GP */

	case PVR_440GX_RA:
		puts("440GX Rev. A");
		break;

	case PVR_440GX_RB:
		puts("440GX Rev. B");
		break;

	case PVR_440GX_RC:
		puts("440GX Rev. C");
		break;

	case PVR_440GX_RF:
		puts("440GX Rev. F");
		break;

	case PVR_440EP_RA:
		puts("440EP Rev. A");
		break;

#ifdef CONFIG_440EP
	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
		puts("440EP Rev. B");
		break;

	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
		puts("440EP Rev. C");
		break;
#endif /*  CONFIG_440EP */

#ifdef CONFIG_440GR
	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
		puts("440GR Rev. A");
		break;

	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
		puts("440GR Rev. B");
		break;
#endif /* CONFIG_440GR */

#ifdef CONFIG_440EPX
	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("440EPx Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("440EPx Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;
#endif /* CONFIG_440EPX */

#ifdef CONFIG_440GRX
	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("440GRx Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
		puts("440GRx Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;
#endif /* CONFIG_440GRX */

	case PVR_440SP_6_RAB:
		puts("440SP Rev. A/B");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SP_RAB:
		puts("440SP Rev. A/B");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SP_6_RC:
		puts("440SP Rev. C");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SP_RC:
		puts("440SP Rev. C");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SPe_6_RA:
		puts("440SPe Rev. A");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SPe_RA:
		puts("440SPe Rev. A");
		strcpy(addstr, "No RAID 6 support");
		break;

	case PVR_440SPe_6_RB:
		puts("440SPe Rev. B");
		strcpy(addstr, "RAID 6 support");
		break;

	case PVR_440SPe_RB:
		puts("440SPe Rev. B");
		strcpy(addstr, "No RAID 6 support");
		break;

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
	case PVR_460EX_RA:
		puts("460EX Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;

	case PVR_460EX_SE_RA:
		puts("460EX Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_460EX_RB:
		puts("460EX Rev. B");
		mfsdr(SDR0_ECID3, reg);
		if (reg & 0x00100000)
			strcpy(addstr, "No Security/Kasumi support");
		else
			strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_460GT_RA:
		puts("460GT Rev. A");
		strcpy(addstr, "No Security/Kasumi support");
		break;

	case PVR_460GT_SE_RA:
		puts("460GT Rev. A");
		strcpy(addstr, "Security/Kasumi support");
		break;

	case PVR_460GT_RB:
		puts("460GT Rev. B");
		mfsdr(SDR0_ECID3, reg);
		if (reg & 0x00100000)
			strcpy(addstr, "No Security/Kasumi support");
		else
			strcpy(addstr, "Security/Kasumi support");
		break;
#endif

	case PVR_460SX_RA:
		puts("460SX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_460SX_RA_V1:
		puts("460SX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_460GX_RA:
		puts("460GX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_460GX_RA_V1:
		puts("460GX Rev. A");
		strcpy(addstr, "No Security support");
		break;

	case PVR_APM821XX_RA:
		puts("APM821XX Rev. A");
		strcpy(addstr, "Security support");
		break;

	case PVR_VIRTEX5:
		puts("440x5 VIRTEX5");
		break;
#endif /* CONFIG_440 */

	default:
		printf (" UNKNOWN (PVR=%08x)", pvr);
		break;
	}

	printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
		strmhz(buf, clock),
		sys_info.freqPLB / 1000000,
		get_OPB_freq() / 1000000,
		sys_info.freqEBC / 1000000);
#if defined(CONFIG_PCI) && \
	(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
	 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
	printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
#endif
	printf(")\n");

	if (addstr[0] != 0)
		printf("       %s\n", addstr);

#if defined(I2C_BOOTROM)
	printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
#endif	/* I2C_BOOTROM */
#if defined(SDR0_PINSTP_SHIFT)
	printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
	printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
	putc('\n');
#endif	/* SDR0_PINSTP_SHIFT */

#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
	printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
#endif

#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
	if (pci_async_enabled()) {
		printf (", PCI async ext clock used");
	} else {
		printf (", PCI sync clock at %lu MHz",
		       sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	}
#endif

#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
	putc('\n');
#endif

#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
	printf("       16 KiB I-Cache 16 KiB D-Cache");
#elif defined(CONFIG_440)
	printf("       32 KiB I-Cache 32 KiB D-Cache");
#else
	printf("       16 KiB I-Cache %d KiB D-Cache",
	       ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif

#endif /* !defined(CONFIG_405) */

	putc ('\n');

	return 0;
}

int ppc440spe_revB() {
	unsigned int pvr;

	pvr = get_pvr();
	if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
		return 1;
	else
		return 0;
}

/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#if defined(CONFIG_BOARD_RESET)
	board_reset();
#else
#if defined(CONFIG_SYS_4xx_RESET_TYPE)
	mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
#else
	/*
	 * Initiate system reset in debug control register DBCR
	 */
	mtspr(SPRN_DBCR0, 0x30000000);
#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
#endif /* defined(CONFIG_BOARD_RESET) */

	return 1;
}


/*
 * Get timebase clock frequency
 */
unsigned long get_tbclk (void)
{
	sys_info_t  sys_info;

	get_sys_info(&sys_info);
	return (sys_info.freqProcessor);
}


#if defined(CONFIG_WATCHDOG)
void watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_4xx_watchdog();
	if (re_enable) enable_interrupts();
}

void reset_4xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit
	 */
	mtspr(SPRN_TSR, 0x40000000);
}
#endif	/* CONFIG_WATCHDOG */

/*
 * Initializes on-chip ethernet controllers.
 * to override, implement board_eth_init()
 */
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_PPC4xx_EMAC)
	ppc_4xx_eth_initialize(bis);
#endif
	return 0;
}
Commit	Line	Data
c609719b	1	/*
dbbd1257	2	* (C) Copyright 2000-2007
c609719b WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
c609719b WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
c609719b WD	9	* CPU specific code
	10	*
	11	* written or collected and sometimes rewritten by
	12	* Magnus Damm <damm@bitsmart.com>
	13	*
	14	* minor modifications by
	15	* Wolfgang Denk <wd@denx.de>
	16	*/
	17
	18	#include <common.h>
	19	#include <watchdog.h>
	20	#include <command.h>
	21	#include <asm/cache.h>
b36df561	22	#include <asm/ppc4xx.h>
25a85906	23	#include <netdev.h>
c609719b	24
d87080b7	25	DECLARE_GLOBAL_DATA_PTR;
d87080b7	26
f3443867	27	void board_reset(void);
f3443867	28
c9c11d75 AG	29	/*
	30	* To provide an interface to detect CPU number for boards that support
	31	* more then one CPU, we implement the "weak" default functions here.
	32	*
	33	* Returns CPU number
	34	*/
	35	int __get_cpu_num(void)
	36	{
	37	return NA_OR_UNKNOWN_CPU;
	38	}
	39	int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
	40
20b3c4b5	41	#if defined(CONFIG_PCI)
887e2ec9 SR	42	#if defined(CONFIG_405GP) \|\| \
	43	defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
	44	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
6e7fb6ea SR	45
	46	#define PCI_ASYNC
	47
c7f69c34	48	static int pci_async_enabled(void)
6e7fb6ea SR	49	{
6e7fb6ea SR	50	#if defined(CONFIG_405GP)
d1c3b275	51	return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
3d9569b2 SR	52	#endif
3d9569b2 SR	53
887e2ec9	54	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
2801b2d2 SR	55	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
2801b2d2 SR	56	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
6e7fb6ea SR	57	unsigned long val;
6e7fb6ea SR	58
d1c3b275	59	mfsdr(SDR0_SDSTP1, val);
6e7fb6ea SR	60	return (val & SDR0_SDSTP1_PAME_MASK);
	61	#endif
	62	}
	63	#endif
20b3c4b5	64	#endif /* CONFIG_PCI */
6e7fb6ea	65
99bcad18	66	#if defined(CONFIG_PCI) && \
dbbd1257	67	!defined(CONFIG_405) && !defined(CONFIG_405EX)
a760b020	68	int pci_arbiter_enabled(void)
6e7fb6ea SR	69	{
6e7fb6ea SR	70	#if defined(CONFIG_405GP)
d1c3b275	71	return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
6e7fb6ea	72	#endif
3d9569b2	73
6e7fb6ea	74	#if defined(CONFIG_405EP)
d1c3b275	75	return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
3d9569b2 SR	76	#endif
	77
	78	#if defined(CONFIG_440GP)
d1c3b275	79	return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
6e7fb6ea SR	80	#endif
6e7fb6ea SR	81
7372ca68	82	#if defined(CONFIG_440GX) \|\| defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
6e7fb6ea	83	unsigned long val;
3d9569b2	84
5e7abce9 SR	85	mfsdr(SDR0_XCR0, val);
5e7abce9 SR	86	return (val & SDR0_XCR0_PAE_MASK);
7372ca68 SR	87	#endif
7372ca68 SR	88	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR) \|\| \
2801b2d2 SR	89	defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX) \|\| \
2801b2d2 SR	90	defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
7372ca68 SR	91	unsigned long val;
7372ca68 SR	92
d1c3b275	93	mfsdr(SDR0_PCI0, val);
5e7abce9	94	return (val & SDR0_PCI0_PAE_MASK);
3d9569b2	95	#endif
6e7fb6ea SR	96	}
	97	#endif
	98
c7f69c34	99	#if defined(CONFIG_405EP)
6e7fb6ea	100	#define I2C_BOOTROM
3d9569b2	101
c7f69c34	102	static int i2c_bootrom_enabled(void)
6e7fb6ea SR	103	{
6e7fb6ea SR	104	#if defined(CONFIG_405EP)
d1c3b275	105	return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
887e2ec9	106	#else
6e7fb6ea SR	107	unsigned long val;
6e7fb6ea SR	108
d1c3b275	109	mfsdr(SDR0_SDCS0, val);
6e7fb6ea SR	110	return (val & SDR0_SDCS_SDD);
	111	#endif
	112	}
90e6f41c	113	#endif
887e2ec9 SR	114
	115	#if defined(CONFIG_440GX)
	116	#define SDR0_PINSTP_SHIFT 29
	117	static char *bootstrap_str[] = {
	118	"EBC (16 bits)",
	119	"EBC (8 bits)",
	120	"EBC (32 bits)",
	121	"EBC (8 bits)",
	122	"PCI",
	123	"I2C (Addr 0x54)",
	124	"Reserved",
	125	"I2C (Addr 0x50)",
	126	};
e3cbe1f9	127	static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
887e2ec9 SR	128	#endif
	129
	130	#if defined(CONFIG_440SP) \|\| defined(CONFIG_440SPE)
	131	#define SDR0_PINSTP_SHIFT 30
	132	static char *bootstrap_str[] = {
	133	"EBC (8 bits)",
	134	"PCI",
	135	"I2C (Addr 0x54)",
	136	"I2C (Addr 0x50)",
	137	};
e3cbe1f9	138	static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
887e2ec9 SR	139	#endif
	140
	141	#if defined(CONFIG_440EP) \|\| defined(CONFIG_440GR)
	142	#define SDR0_PINSTP_SHIFT 29
	143	static char *bootstrap_str[] = {
	144	"EBC (8 bits)",
	145	"PCI",
	146	"NAND (8 bits)",
	147	"EBC (16 bits)",
	148	"EBC (16 bits)",
	149	"I2C (Addr 0x54)",
	150	"PCI",
	151	"I2C (Addr 0x52)",
	152	};
e3cbe1f9	153	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
887e2ec9 SR	154	#endif
	155
	156	#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
	157	#define SDR0_PINSTP_SHIFT 29
	158	static char *bootstrap_str[] = {
	159	"EBC (8 bits)",
	160	"EBC (16 bits)",
	161	"EBC (16 bits)",
	162	"NAND (8 bits)",
	163	"PCI",
	164	"I2C (Addr 0x54)",
	165	"PCI",
	166	"I2C (Addr 0x52)",
	167	};
e3cbe1f9	168	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
887e2ec9 SR	169	#endif
887e2ec9 SR	170
2801b2d2 SR	171	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	172	#define SDR0_PINSTP_SHIFT 29
	173	static char *bootstrap_str[] = {
	174	"EBC (8 bits)",
	175	"EBC (16 bits)",
	176	"PCI",
	177	"PCI",
	178	"EBC (16 bits)",
	179	"NAND (8 bits)",
	180	"I2C (Addr 0x54)", /* A8 */
	181	"I2C (Addr 0x52)", /* A4 */
	182	};
d98964aa	183	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
2801b2d2 SR	184	#endif
2801b2d2 SR	185
7d307936 FK	186	#if defined(CONFIG_460SX)
	187	#define SDR0_PINSTP_SHIFT 29
	188	static char *bootstrap_str[] = {
	189	"EBC (8 bits)",
	190	"EBC (16 bits)",
	191	"EBC (32 bits)",
	192	"NAND (8 bits)",
	193	"I2C (Addr 0x54)", /* A8 */
	194	"I2C (Addr 0x52)", /* A4 */
	195	};
	196	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
	197	#endif
	198
90e6f41c SR	199	#if defined(CONFIG_405EZ)
	200	#define SDR0_PINSTP_SHIFT 28
	201	static char *bootstrap_str[] = {
	202	"EBC (8 bits)",
	203	"SPI (fast)",
	204	"NAND (512 page, 4 addr cycle)",
	205	"I2C (Addr 0x50)",
	206	"EBC (32 bits)",
	207	"I2C (Addr 0x50)",
	208	"NAND (2K page, 5 addr cycle)",
	209	"I2C (Addr 0x50)",
	210	"EBC (16 bits)",
	211	"Reserved",
	212	"NAND (2K page, 4 addr cycle)",
	213	"I2C (Addr 0x50)",
	214	"NAND (512 page, 3 addr cycle)",
	215	"I2C (Addr 0x50)",
	216	"SPI (slow)",
	217	"I2C (Addr 0x50)",
	218	};
e3cbe1f9 BM	219	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
e3cbe1f9 BM	220	'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
90e6f41c SR	221	#endif
90e6f41c SR	222
dbbd1257 SR	223	#if defined(CONFIG_405EX)
	224	#define SDR0_PINSTP_SHIFT 29
	225	static char *bootstrap_str[] = {
	226	"EBC (8 bits)",
	227	"EBC (16 bits)",
	228	"EBC (16 bits)",
	229	"NAND (8 bits)",
	230	"NAND (8 bits)",
	231	"I2C (Addr 0x54)",
	232	"EBC (8 bits)",
	233	"I2C (Addr 0x52)",
	234	};
	235	static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
	236	#endif
	237
887e2ec9 SR	238	#if defined(SDR0_PINSTP_SHIFT)
	239	static int bootstrap_option(void)
	240	{
	241	unsigned long val;
	242
d1c3b275	243	mfsdr(SDR0_PINSTP, val);
90e6f41c	244	return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
887e2ec9 SR	245	}
887e2ec9 SR	246	#endif /* SDR0_PINSTP_SHIFT */
3d9569b2 SR	247
3d9569b2 SR	248
5e7abce9	249	#if defined(CONFIG_440GP)
c7f69c34 SR	250	static int do_chip_reset (unsigned long sys0, unsigned long sys1)
c7f69c34 SR	251	{
d1c3b275	252	/* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
c7f69c34 SR	253	* reset.
c7f69c34 SR	254	*/
d1c3b275 SR	255	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) \| 0x80000000); /* Set SWE */
	256	mtdcr (CPC0_SYS0, sys0);
	257	mtdcr (CPC0_SYS1, sys1);
	258	mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
58ea142f	259	mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
c7f69c34 SR	260
	261	return 1;
	262	}
5e7abce9	263	#endif /* CONFIG_440GP */
c609719b	264
c609719b WD	265
	266	int checkcpu (void)
	267	{
3d9569b2	268	#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
3d9569b2	269	uint pvr = get_pvr();
c609719b WD	270	ulong clock = gd->cpu_clk;
c609719b WD	271	char buf[32];
89bcc487 SR	272	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	273	u32 reg;
	274	#endif
c609719b	275
ba999c53	276	char addstr[64] = "";
3d9569b2	277	sys_info_t sys_info;
c9c11d75	278	int cpu_num;
c609719b	279
c9c11d75 AG	280	cpu_num = get_cpu_num();
	281	if (cpu_num >= 0)
	282	printf("CPU%d: ", cpu_num);
	283	else
	284	puts("CPU: ");
c609719b WD	285
	286	get_sys_info(&sys_info);
	287
d865fd09	288	#if defined(CONFIG_XILINX_440)
e02d4496	289	puts("IBM PowerPC ");
d865fd09	290	#else
e02d4496	291	puts("AMCC PowerPC ");
c609719b	292	#endif
3d9569b2	293
c609719b	294	switch (pvr) {
e02d4496 SR	295
e02d4496 SR	296	#if !defined(CONFIG_440)
c609719b	297	case PVR_405GP_RB:
e02d4496	298	puts("405GP Rev. B");
c609719b	299	break;
3d9569b2	300
c609719b	301	case PVR_405GP_RC:
e02d4496	302	puts("405GP Rev. C");
c609719b	303	break;
3d9569b2	304
c609719b	305	case PVR_405GP_RD:
e02d4496	306	puts("405GP Rev. D");
c609719b	307	break;
3d9569b2	308
3fb85889	309	case PVR_405GP_RE:
e02d4496	310	puts("405GP Rev. E");
c609719b	311	break;
c609719b	312
3d9569b2	313	case PVR_405GPR_RB:
e02d4496	314	puts("405GPr Rev. B");
3d9569b2	315	break;
c609719b	316
3d9569b2	317	case PVR_405EP_RB:
e02d4496	318	puts("405EP Rev. B");
3d9569b2	319	break;
c609719b	320
e01bd218	321	case PVR_405EZ_RA:
e02d4496	322	puts("405EZ Rev. A");
e01bd218 SR	323	break;
e01bd218 SR	324
dbbd1257	325	case PVR_405EX1_RA:
e02d4496	326	puts("405EX Rev. A");
dbbd1257 SR	327	strcpy(addstr, "Security support");
	328	break;
	329
dbbd1257	330	case PVR_405EXR2_RA:
e02d4496	331	puts("405EXr Rev. A");
dbbd1257 SR	332	strcpy(addstr, "No Security support");
	333	break;
	334
70fab190	335	case PVR_405EX1_RC:
e02d4496	336	puts("405EX Rev. C");
70fab190 SR	337	strcpy(addstr, "Security support");
	338	break;
	339
	340	case PVR_405EX2_RC:
e02d4496	341	puts("405EX Rev. C");
70fab190 SR	342	strcpy(addstr, "No Security support");
	343	break;
	344
	345	case PVR_405EXR1_RC:
e02d4496	346	puts("405EXr Rev. C");
70fab190 SR	347	strcpy(addstr, "Security support");
	348	break;
	349
	350	case PVR_405EXR2_RC:
e02d4496	351	puts("405EXr Rev. C");
70fab190 SR	352	strcpy(addstr, "No Security support");
	353	break;
	354
56f14818	355	case PVR_405EX1_RD:
e02d4496	356	puts("405EX Rev. D");
56f14818 SR	357	strcpy(addstr, "Security support");
	358	break;
	359
	360	case PVR_405EX2_RD:
e02d4496	361	puts("405EX Rev. D");
56f14818 SR	362	strcpy(addstr, "No Security support");
	363	break;
	364
	365	case PVR_405EXR1_RD:
e02d4496	366	puts("405EXr Rev. D");
56f14818 SR	367	strcpy(addstr, "Security support");
	368	break;
	369
	370	case PVR_405EXR2_RD:
e02d4496	371	puts("405EXr Rev. D");
56f14818 SR	372	strcpy(addstr, "No Security support");
	373	break;
	374
e02d4496 SR	375	#else /* CONFIG_440 */
e02d4496 SR	376
5e7abce9	377	#if defined(CONFIG_440GP)
8bde7f77	378	case PVR_440GP_RB:
e02d4496	379	puts("440GP Rev. B");
4d816774	380	/* See errata 1.12: CHIP_4 */
d1c3b275 SR	381	if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) \|\|
d1c3b275 SR	382	(mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
4d816774 WD	383	puts ( "\n\t CPC0_SYSx DCRs corrupted. "
	384	"Resetting chip ...\n");
	385	udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
d1c3b275 SR	386	do_chip_reset ( mfdcr(CPC0_STRP0),
d1c3b275 SR	387	mfdcr(CPC0_STRP1) );
4d816774	388	}
c609719b	389	break;
3d9569b2	390
8bde7f77	391	case PVR_440GP_RC:
e02d4496	392	puts("440GP Rev. C");
ba56f625	393	break;
5e7abce9	394	#endif /* CONFIG_440GP */
3d9569b2	395
ba56f625	396	case PVR_440GX_RA:
e02d4496	397	puts("440GX Rev. A");
ba56f625	398	break;
3d9569b2	399
ba56f625	400	case PVR_440GX_RB:
e02d4496	401	puts("440GX Rev. B");
c609719b	402	break;
3d9569b2	403
0a7c5391	404	case PVR_440GX_RC:
e02d4496	405	puts("440GX Rev. C");
0a7c5391	406	break;
3d9569b2	407
57275b69	408	case PVR_440GX_RF:
e02d4496	409	puts("440GX Rev. F");
57275b69	410	break;
3d9569b2	411
c157d8e2	412	case PVR_440EP_RA:
e02d4496	413	puts("440EP Rev. A");
c157d8e2	414	break;
3d9569b2	415
9a8d82fd SR	416	#ifdef CONFIG_440EP
9a8d82fd SR	417	case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
e02d4496	418	puts("440EP Rev. B");
c157d8e2	419	break;
512f8d5d SR	420
512f8d5d SR	421	case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
e02d4496	422	puts("440EP Rev. C");
512f8d5d	423	break;
9a8d82fd	424	#endif /* CONFIG_440EP */
3d9569b2	425
9a8d82fd SR	426	#ifdef CONFIG_440GR
9a8d82fd SR	427	case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
e02d4496	428	puts("440GR Rev. A");
9a8d82fd	429	break;
512f8d5d	430
5770a1e4	431	case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
e02d4496	432	puts("440GR Rev. B");
512f8d5d	433	break;
9a8d82fd	434	#endif /* CONFIG_440GR */
3d9569b2	435
2902fada SR	436	#ifdef CONFIG_440EPX
2902fada SR	437	case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
e02d4496	438	puts("440EPx Rev. A");
edf0b543	439	strcpy(addstr, "Security/Kasumi support");
887e2ec9 SR	440	break;
887e2ec9 SR	441
2902fada	442	case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
e02d4496	443	puts("440EPx Rev. A");
edf0b543	444	strcpy(addstr, "No Security/Kasumi support");
887e2ec9	445	break;
2902fada	446	#endif /* CONFIG_440EPX */
887e2ec9	447
2902fada SR	448	#ifdef CONFIG_440GRX
2902fada SR	449	case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
e02d4496	450	puts("440GRx Rev. A");
edf0b543	451	strcpy(addstr, "Security/Kasumi support");
887e2ec9 SR	452	break;
887e2ec9 SR	453
2902fada	454	case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
e02d4496	455	puts("440GRx Rev. A");
edf0b543	456	strcpy(addstr, "No Security/Kasumi support");
887e2ec9	457	break;
2902fada	458	#endif /* CONFIG_440GRX */
887e2ec9	459
95981778	460	case PVR_440SP_6_RAB:
e02d4496	461	puts("440SP Rev. A/B");
95981778	462	strcpy(addstr, "RAID 6 support");
6e7fb6ea SR	463	break;
6e7fb6ea SR	464
95981778	465	case PVR_440SP_RAB:
e02d4496	466	puts("440SP Rev. A/B");
95981778 SR	467	strcpy(addstr, "No RAID 6 support");
	468	break;
	469
	470	case PVR_440SP_6_RC:
e02d4496	471	puts("440SP Rev. C");
95981778	472	strcpy(addstr, "RAID 6 support");
6e7fb6ea SR	473	break;
6e7fb6ea SR	474
e732faec	475	case PVR_440SP_RC:
e02d4496	476	puts("440SP Rev. C");
95981778 SR	477	strcpy(addstr, "No RAID 6 support");
	478	break;
	479
	480	case PVR_440SPe_6_RA:
e02d4496	481	puts("440SPe Rev. A");
95981778	482	strcpy(addstr, "RAID 6 support");
e732faec SR	483	break;
e732faec SR	484
6c5879f3	485	case PVR_440SPe_RA:
e02d4496	486	puts("440SPe Rev. A");
95981778 SR	487	strcpy(addstr, "No RAID 6 support");
	488	break;
	489
	490	case PVR_440SPe_6_RB:
e02d4496	491	puts("440SPe Rev. B");
95981778	492	strcpy(addstr, "RAID 6 support");
6c5879f3	493	break;
fe84b48a	494
6c5879f3	495	case PVR_440SPe_RB:
e02d4496	496	puts("440SPe Rev. B");
95981778	497	strcpy(addstr, "No RAID 6 support");
6c5879f3	498	break;
fe84b48a	499
89bcc487	500	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
2801b2d2	501	case PVR_460EX_RA:
e02d4496	502	puts("460EX Rev. A");
2801b2d2 SR	503	strcpy(addstr, "No Security/Kasumi support");
	504	break;
	505
	506	case PVR_460EX_SE_RA:
e02d4496	507	puts("460EX Rev. A");
2801b2d2 SR	508	strcpy(addstr, "Security/Kasumi support");
	509	break;
	510
89bcc487	511	case PVR_460EX_RB:
e02d4496	512	puts("460EX Rev. B");
89bcc487 SR	513	mfsdr(SDR0_ECID3, reg);
	514	if (reg & 0x00100000)
	515	strcpy(addstr, "No Security/Kasumi support");
	516	else
	517	strcpy(addstr, "Security/Kasumi support");
	518	break;
	519
2801b2d2	520	case PVR_460GT_RA:
e02d4496	521	puts("460GT Rev. A");
2801b2d2 SR	522	strcpy(addstr, "No Security/Kasumi support");
	523	break;
	524
	525	case PVR_460GT_SE_RA:
e02d4496	526	puts("460GT Rev. A");
2801b2d2 SR	527	strcpy(addstr, "Security/Kasumi support");
	528	break;
	529
89bcc487	530	case PVR_460GT_RB:
e02d4496	531	puts("460GT Rev. B");
89bcc487 SR	532	mfsdr(SDR0_ECID3, reg);
	533	if (reg & 0x00100000)
	534	strcpy(addstr, "No Security/Kasumi support");
	535	else
	536	strcpy(addstr, "Security/Kasumi support");
	537	break;
	538	#endif
	539
7d307936	540	case PVR_460SX_RA:
e02d4496	541	puts("460SX Rev. A");
7d307936 FK	542	strcpy(addstr, "Security support");
	543	break;
	544
	545	case PVR_460SX_RA_V1:
e02d4496	546	puts("460SX Rev. A");
7d307936 FK	547	strcpy(addstr, "No Security support");
	548	break;
	549
	550	case PVR_460GX_RA:
e02d4496	551	puts("460GX Rev. A");
7d307936 FK	552	strcpy(addstr, "Security support");
	553	break;
	554
	555	case PVR_460GX_RA_V1:
e02d4496	556	puts("460GX Rev. A");
7d307936 FK	557	strcpy(addstr, "No Security support");
	558	break;
	559
1b8fec13 TM	560	case PVR_APM821XX_RA:
	561	puts("APM821XX Rev. A");
	562	strcpy(addstr, "Security support");
	563	break;
	564
d865fd09	565	case PVR_VIRTEX5:
e02d4496	566	puts("440x5 VIRTEX5");
d865fd09	567	break;
e02d4496	568	#endif /* CONFIG_440 */
d865fd09	569
8bde7f77	570	default:
17f50f22	571	printf (" UNKNOWN (PVR=%08x)", pvr);
c609719b WD	572	break;
c609719b WD	573	}
3d9569b2	574
08c6a262 SR	575	printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
08c6a262 SR	576	strmhz(buf, clock),
e01bd218 SR	577	sys_info.freqPLB / 1000000,
e01bd218 SR	578	get_OPB_freq() / 1000000,
dbbd1257	579	sys_info.freqEBC / 1000000);
08c6a262 SR	580	#if defined(CONFIG_PCI) && \
	581	(defined(CONFIG_440EP) \|\| defined(CONFIG_440EPX) \|\| \
	582	defined(CONFIG_440GR) \|\| defined(CONFIG_440GRX))
	583	printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
	584	#endif
	585	printf(")\n");
3d9569b2	586
edf0b543 SR	587	if (addstr[0] != 0)
	588	printf(" %s\n", addstr);
	589
6e7fb6ea SR	590	#if defined(I2C_BOOTROM)
6e7fb6ea SR	591	printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
90e6f41c	592	#endif /* I2C_BOOTROM */
887e2ec9	593	#if defined(SDR0_PINSTP_SHIFT)
e3cbe1f9	594	printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
cf940988	595	printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
cf940988	596	putc('\n');
ba999c53	597	#endif /* SDR0_PINSTP_SHIFT */
3d9569b2	598
dbbd1257	599	#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
6e7fb6ea	600	printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
3d9569b2 SR	601	#endif
3d9569b2 SR	602
1bbae2b8	603	#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
6e7fb6ea	604	if (pci_async_enabled()) {
3d9569b2 SR	605	printf (", PCI async ext clock used");
	606	} else {
	607	printf (", PCI sync clock at %lu MHz",
	608	sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
	609	}
c609719b	610	#endif
3d9569b2	611
dbbd1257	612	#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
3d9569b2 SR	613	putc('\n');
	614	#endif
	615
dbbd1257	616	#if defined(CONFIG_405EP) \|\| defined(CONFIG_405EZ) \|\| defined(CONFIG_405EX)
6b44d9e5	617	printf(" 16 KiB I-Cache 16 KiB D-Cache");
3d9569b2	618	#elif defined(CONFIG_440)
6b44d9e5	619	printf(" 32 KiB I-Cache 32 KiB D-Cache");
3d9569b2	620	#else
6b44d9e5 SK	621	printf(" 16 KiB I-Cache %d KiB D-Cache",
6b44d9e5 SK	622	((pvr \| 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
3d9569b2	623	#endif
3d9569b2 SR	624
	625	#endif /* !defined(CONFIG_405) */
	626
	627	putc ('\n');
c609719b WD	628
	629	return 0;
	630	}
	631
692519b1 RJ	632	int ppc440spe_revB() {
	633	unsigned int pvr;
	634
	635	pvr = get_pvr();
5a5c5698	636	if ((pvr == PVR_440SPe_6_RB) \|\| (pvr == PVR_440SPe_RB))
692519b1 RJ	637	return 1;
	638	else
	639	return 0;
	640	}
c609719b WD	641
	642	/* ------------------------------------------------------------------------- */
	643
54841ab5	644	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
c609719b	645	{
1f94d162 SR	646	#if defined(CONFIG_BOARD_RESET)
1f94d162 SR	647	board_reset();
1729b92c	648	#else
6d0f6bcf	649	#if defined(CONFIG_SYS_4xx_RESET_TYPE)
58ea142f	650	mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
c157d8e2	651	#else
8bde7f77 WD	652	/*
	653	* Initiate system reset in debug control register DBCR
	654	*/
58ea142f	655	mtspr(SPRN_DBCR0, 0x30000000);
6d0f6bcf	656	#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
f3443867	657	#endif /* defined(CONFIG_BOARD_RESET) */
c157d8e2	658
c609719b WD	659	return 1;
	660	}
	661
c609719b WD	662
	663	/*
	664	* Get timebase clock frequency
	665	*/
	666	unsigned long get_tbclk (void)
	667	{
c609719b WD	668	sys_info_t sys_info;
	669
	670	get_sys_info(&sys_info);
	671	return (sys_info.freqProcessor);
c609719b WD	672	}
	673
	674
	675	#if defined(CONFIG_WATCHDOG)
c7f69c34	676	void watchdog_reset(void)
c609719b WD	677	{
	678	int re_enable = disable_interrupts();
	679	reset_4xx_watchdog();
	680	if (re_enable) enable_interrupts();
	681	}
	682
c7f69c34	683	void reset_4xx_watchdog(void)
c609719b WD	684	{
	685	/*
	686	* Clear TSR(WIS) bit
	687	*/
58ea142f	688	mtspr(SPRN_TSR, 0x40000000);
c609719b WD	689	}
c609719b WD	690	#endif /* CONFIG_WATCHDOG */
25a85906 BW	691
	692	/*
	693	* Initializes on-chip ethernet controllers.
	694	* to override, implement board_eth_init()
	695	*/
	696	int cpu_eth_init(bd_t *bis)
	697	{
	698	#if defined(CONFIG_PPC4xx_EMAC)
	699	ppc_4xx_eth_initialize(bis);
	700	#endif
	701	return 0;
	702	}