arch/powerpc/cpu/ppc4xx/cpu.c

   1 /*
   2  * (C) Copyright 2000-2007
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * CPU specific code
  10  *
  11  * written or collected and sometimes rewritten by
  12  * Magnus Damm <damm@bitsmart.com>
  13  *
  14  * minor modifications by
  15  * Wolfgang Denk <wd@denx.de>
  16  */
  17
  18 #include <common.h>
  19 #include <watchdog.h>
  20 #include <command.h>
  21 #include <asm/cache.h>
  22 #include <asm/ppc4xx.h>
  23 #include <netdev.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 void board_reset(void);
  28
  29 /*
  30  * To provide an interface to detect CPU number for boards that support
  31  * more then one CPU, we implement the "weak" default functions here.
  32  *
  33  * Returns CPU number
  34  */
  35 int __get_cpu_num(void)
  36 {
  37         return NA_OR_UNKNOWN_CPU;
  38 }
  39 int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
  40
  41 #if defined(CONFIG_PCI)
  42 #if defined(CONFIG_405GP) || \
  43     defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  44     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  45
  46 #define PCI_ASYNC
  47
  48 static int pci_async_enabled(void)
  49 {
  50 #if defined(CONFIG_405GP)
  51         return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
  52 #endif
  53
  54 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  55     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  56     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  57         unsigned long val;
  58
  59         mfsdr(SDR0_SDSTP1, val);
  60         return (val & SDR0_SDSTP1_PAME_MASK);
  61 #endif
  62 }
  63 #endif
  64 #endif /* CONFIG_PCI */
  65
  66 #if defined(CONFIG_PCI) && \
  67     !defined(CONFIG_405) && !defined(CONFIG_405EX)
  68 int pci_arbiter_enabled(void)
  69 {
  70 #if defined(CONFIG_405GP)
  71         return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
  72 #endif
  73
  74 #if defined(CONFIG_405EP)
  75         return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
  76 #endif
  77
  78 #if defined(CONFIG_440GP)
  79         return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
  80 #endif
  81
  82 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  83         unsigned long val;
  84
  85         mfsdr(SDR0_XCR0, val);
  86         return (val & SDR0_XCR0_PAE_MASK);
  87 #endif
  88 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  89     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  90     defined(CONFIG_460EX) || defined(CONFIG_460GT)
  91         unsigned long val;
  92
  93         mfsdr(SDR0_PCI0, val);
  94         return (val & SDR0_PCI0_PAE_MASK);
  95 #endif
  96 }
  97 #endif
  98
  99 #if defined(CONFIG_405EP)
 100 #define I2C_BOOTROM
 101
 102 static int i2c_bootrom_enabled(void)
 103 {
 104 #if defined(CONFIG_405EP)
 105         return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
 106 #else
 107         unsigned long val;
 108
 109         mfsdr(SDR0_SDCS0, val);
 110         return (val & SDR0_SDCS_SDD);
 111 #endif
 112 }
 113 #endif
 114
 115 #if defined(CONFIG_440GX)
 116 #define SDR0_PINSTP_SHIFT       29
 117 static char *bootstrap_str[] = {
 118         "EBC (16 bits)",
 119         "EBC (8 bits)",
 120         "EBC (32 bits)",
 121         "EBC (8 bits)",
 122         "PCI",
 123         "I2C (Addr 0x54)",
 124         "Reserved",
 125         "I2C (Addr 0x50)",
 126 };
 127 static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
 128 #endif
 129
 130 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 131 #define SDR0_PINSTP_SHIFT       30
 132 static char *bootstrap_str[] = {
 133         "EBC (8 bits)",
 134         "PCI",
 135         "I2C (Addr 0x54)",
 136         "I2C (Addr 0x50)",
 137 };
 138 static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
 139 #endif
 140
 141 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 142 #define SDR0_PINSTP_SHIFT       29
 143 static char *bootstrap_str[] = {
 144         "EBC (8 bits)",
 145         "PCI",
 146         "NAND (8 bits)",
 147         "EBC (16 bits)",
 148         "EBC (16 bits)",
 149         "I2C (Addr 0x54)",
 150         "PCI",
 151         "I2C (Addr 0x52)",
 152 };
 153 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 154 #endif
 155
 156 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 157 #define SDR0_PINSTP_SHIFT       29
 158 static char *bootstrap_str[] = {
 159         "EBC (8 bits)",
 160         "EBC (16 bits)",
 161         "EBC (16 bits)",
 162         "NAND (8 bits)",
 163         "PCI",
 164         "I2C (Addr 0x54)",
 165         "PCI",
 166         "I2C (Addr 0x52)",
 167 };
 168 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 169 #endif
 170
 171 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 172 #define SDR0_PINSTP_SHIFT       29
 173 static char *bootstrap_str[] = {
 174         "EBC (8 bits)",
 175         "EBC (16 bits)",
 176         "PCI",
 177         "PCI",
 178         "EBC (16 bits)",
 179         "NAND (8 bits)",
 180         "I2C (Addr 0x54)",      /* A8 */
 181         "I2C (Addr 0x52)",      /* A4 */
 182 };
 183 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
 184 #endif
 185
 186 #if defined(CONFIG_460SX)
 187 #define SDR0_PINSTP_SHIFT       29
 188 static char *bootstrap_str[] = {
 189         "EBC (8 bits)",
 190         "EBC (16 bits)",
 191         "EBC (32 bits)",
 192         "NAND (8 bits)",
 193         "I2C (Addr 0x54)",      /* A8 */
 194         "I2C (Addr 0x52)",      /* A4 */
 195 };
 196 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
 197 #endif
 198
 199 #if defined(CONFIG_405EZ)
 200 #define SDR0_PINSTP_SHIFT       28
 201 static char *bootstrap_str[] = {
 202         "EBC (8 bits)",
 203         "SPI (fast)",
 204         "NAND (512 page, 4 addr cycle)",
 205         "I2C (Addr 0x50)",
 206         "EBC (32 bits)",
 207         "I2C (Addr 0x50)",
 208         "NAND (2K page, 5 addr cycle)",
 209         "I2C (Addr 0x50)",
 210         "EBC (16 bits)",
 211         "Reserved",
 212         "NAND (2K page, 4 addr cycle)",
 213         "I2C (Addr 0x50)",
 214         "NAND (512 page, 3 addr cycle)",
 215         "I2C (Addr 0x50)",
 216         "SPI (slow)",
 217         "I2C (Addr 0x50)",
 218 };
 219 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
 220                                  'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
 221 #endif
 222
 223 #if defined(CONFIG_405EX)
 224 #define SDR0_PINSTP_SHIFT       29
 225 static char *bootstrap_str[] = {
 226         "EBC (8 bits)",
 227         "EBC (16 bits)",
 228         "EBC (16 bits)",
 229         "NAND (8 bits)",
 230         "NAND (8 bits)",
 231         "I2C (Addr 0x54)",
 232         "EBC (8 bits)",
 233         "I2C (Addr 0x52)",
 234 };
 235 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 236 #endif
 237
 238 #if defined(SDR0_PINSTP_SHIFT)
 239 static int bootstrap_option(void)
 240 {
 241         unsigned long val;
 242
 243         mfsdr(SDR0_PINSTP, val);
 244         return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
 245 }
 246 #endif /* SDR0_PINSTP_SHIFT */
 247
 248
 249 #if defined(CONFIG_440GP)
 250 static int do_chip_reset (unsigned long sys0, unsigned long sys1)
 251 {
 252         /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
 253          * reset.
 254          */
 255         mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000);        /* Set SWE */
 256         mtdcr (CPC0_SYS0, sys0);
 257         mtdcr (CPC0_SYS1, sys1);
 258         mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000);       /* Clr SWE */
 259         mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
 260
 261         return 1;
 262 }
 263 #endif /* CONFIG_440GP */
 264
 265
 266 int checkcpu (void)
 267 {
 268 #if !defined(CONFIG_405)        /* not used on Xilinx 405 FPGA implementations */
 269         uint pvr = get_pvr();
 270         ulong clock = gd->cpu_clk;
 271         char buf[32];
 272 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 273         u32 reg;
 274 #endif
 275
 276         char addstr[64] = "";
 277         sys_info_t sys_info;
 278         int cpu_num;
 279
 280         cpu_num = get_cpu_num();
 281         if (cpu_num >= 0)
 282                 printf("CPU%d:  ", cpu_num);
 283         else
 284                 puts("CPU:   ");
 285
 286         get_sys_info(&sys_info);
 287
 288 #if defined(CONFIG_XILINX_440)
 289         puts("IBM PowerPC ");
 290 #else
 291         puts("AMCC PowerPC ");
 292 #endif
 293
 294         switch (pvr) {
 295
 296 #if !defined(CONFIG_440)
 297         case PVR_405GP_RB:
 298                 puts("405GP Rev. B");
 299                 break;
 300
 301         case PVR_405GP_RC:
 302                 puts("405GP Rev. C");
 303                 break;
 304
 305         case PVR_405GP_RD:
 306                 puts("405GP Rev. D");
 307                 break;
 308
 309         case PVR_405GP_RE:
 310                 puts("405GP Rev. E");
 311                 break;
 312
 313         case PVR_405GPR_RB:
 314                 puts("405GPr Rev. B");
 315                 break;
 316
 317         case PVR_405EP_RB:
 318                 puts("405EP Rev. B");
 319                 break;
 320
 321         case PVR_405EZ_RA:
 322                 puts("405EZ Rev. A");
 323                 break;
 324
 325         case PVR_405EX1_RA:
 326                 puts("405EX Rev. A");
 327                 strcpy(addstr, "Security support");
 328                 break;
 329
 330         case PVR_405EXR2_RA:
 331                 puts("405EXr Rev. A");
 332                 strcpy(addstr, "No Security support");
 333                 break;
 334
 335         case PVR_405EX1_RC:
 336                 puts("405EX Rev. C");
 337                 strcpy(addstr, "Security support");
 338                 break;
 339
 340         case PVR_405EX2_RC:
 341                 puts("405EX Rev. C");
 342                 strcpy(addstr, "No Security support");
 343                 break;
 344
 345         case PVR_405EXR1_RC:
 346                 puts("405EXr Rev. C");
 347                 strcpy(addstr, "Security support");
 348                 break;
 349
 350         case PVR_405EXR2_RC:
 351                 puts("405EXr Rev. C");
 352                 strcpy(addstr, "No Security support");
 353                 break;
 354
 355         case PVR_405EX1_RD:
 356                 puts("405EX Rev. D");
 357                 strcpy(addstr, "Security support");
 358                 break;
 359
 360         case PVR_405EX2_RD:
 361                 puts("405EX Rev. D");
 362                 strcpy(addstr, "No Security support");
 363                 break;
 364
 365         case PVR_405EXR1_RD:
 366                 puts("405EXr Rev. D");
 367                 strcpy(addstr, "Security support");
 368                 break;
 369
 370         case PVR_405EXR2_RD:
 371                 puts("405EXr Rev. D");
 372                 strcpy(addstr, "No Security support");
 373                 break;
 374
 375 #else /* CONFIG_440 */
 376
 377 #if defined(CONFIG_440GP)
 378         case PVR_440GP_RB:
 379                 puts("440GP Rev. B");
 380                 /* See errata 1.12: CHIP_4 */
 381                 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
 382                     (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
 383                         puts (  "\n\t CPC0_SYSx DCRs corrupted. "
 384                                 "Resetting chip ...\n");
 385                         udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
 386                         do_chip_reset ( mfdcr(CPC0_STRP0),
 387                                         mfdcr(CPC0_STRP1) );
 388                 }
 389                 break;
 390
 391         case PVR_440GP_RC:
 392                 puts("440GP Rev. C");
 393                 break;
 394 #endif /* CONFIG_440GP */
 395
 396         case PVR_440GX_RA:
 397                 puts("440GX Rev. A");
 398                 break;
 399
 400         case PVR_440GX_RB:
 401                 puts("440GX Rev. B");
 402                 break;
 403
 404         case PVR_440GX_RC:
 405                 puts("440GX Rev. C");
 406                 break;
 407
 408         case PVR_440GX_RF:
 409                 puts("440GX Rev. F");
 410                 break;
 411
 412         case PVR_440EP_RA:
 413                 puts("440EP Rev. A");
 414                 break;
 415
 416 #ifdef CONFIG_440EP
 417         case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
 418                 puts("440EP Rev. B");
 419                 break;
 420
 421         case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
 422                 puts("440EP Rev. C");
 423                 break;
 424 #endif /*  CONFIG_440EP */
 425
 426 #ifdef CONFIG_440GR
 427         case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
 428                 puts("440GR Rev. A");
 429                 break;
 430
 431         case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
 432                 puts("440GR Rev. B");
 433                 break;
 434 #endif /* CONFIG_440GR */
 435
 436 #ifdef CONFIG_440EPX
 437         case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 438                 puts("440EPx Rev. A");
 439                 strcpy(addstr, "Security/Kasumi support");
 440                 break;
 441
 442         case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 443                 puts("440EPx Rev. A");
 444                 strcpy(addstr, "No Security/Kasumi support");
 445                 break;
 446 #endif /* CONFIG_440EPX */
 447
 448 #ifdef CONFIG_440GRX
 449         case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 450                 puts("440GRx Rev. A");
 451                 strcpy(addstr, "Security/Kasumi support");
 452                 break;
 453
 454         case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 455                 puts("440GRx Rev. A");
 456                 strcpy(addstr, "No Security/Kasumi support");
 457                 break;
 458 #endif /* CONFIG_440GRX */
 459
 460         case PVR_440SP_6_RAB:
 461                 puts("440SP Rev. A/B");
 462                 strcpy(addstr, "RAID 6 support");
 463                 break;
 464
 465         case PVR_440SP_RAB:
 466                 puts("440SP Rev. A/B");
 467                 strcpy(addstr, "No RAID 6 support");
 468                 break;
 469
 470         case PVR_440SP_6_RC:
 471                 puts("440SP Rev. C");
 472                 strcpy(addstr, "RAID 6 support");
 473                 break;
 474
 475         case PVR_440SP_RC:
 476                 puts("440SP Rev. C");
 477                 strcpy(addstr, "No RAID 6 support");
 478                 break;
 479
 480         case PVR_440SPe_6_RA:
 481                 puts("440SPe Rev. A");
 482                 strcpy(addstr, "RAID 6 support");
 483                 break;
 484
 485         case PVR_440SPe_RA:
 486                 puts("440SPe Rev. A");
 487                 strcpy(addstr, "No RAID 6 support");
 488                 break;
 489
 490         case PVR_440SPe_6_RB:
 491                 puts("440SPe Rev. B");
 492                 strcpy(addstr, "RAID 6 support");
 493                 break;
 494
 495         case PVR_440SPe_RB:
 496                 puts("440SPe Rev. B");
 497                 strcpy(addstr, "No RAID 6 support");
 498                 break;
 499
 500 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 501         case PVR_460EX_RA:
 502                 puts("460EX Rev. A");
 503                 strcpy(addstr, "No Security/Kasumi support");
 504                 break;
 505
 506         case PVR_460EX_SE_RA:
 507                 puts("460EX Rev. A");
 508                 strcpy(addstr, "Security/Kasumi support");
 509                 break;
 510
 511         case PVR_460EX_RB:
 512                 puts("460EX Rev. B");
 513                 mfsdr(SDR0_ECID3, reg);
 514                 if (reg & 0x00100000)
 515                         strcpy(addstr, "No Security/Kasumi support");
 516                 else
 517                         strcpy(addstr, "Security/Kasumi support");
 518                 break;
 519
 520         case PVR_460GT_RA:
 521                 puts("460GT Rev. A");
 522                 strcpy(addstr, "No Security/Kasumi support");
 523                 break;
 524
 525         case PVR_460GT_SE_RA:
 526                 puts("460GT Rev. A");
 527                 strcpy(addstr, "Security/Kasumi support");
 528                 break;
 529
 530         case PVR_460GT_RB:
 531                 puts("460GT Rev. B");
 532                 mfsdr(SDR0_ECID3, reg);
 533                 if (reg & 0x00100000)
 534                         strcpy(addstr, "No Security/Kasumi support");
 535                 else
 536                         strcpy(addstr, "Security/Kasumi support");
 537                 break;
 538 #endif
 539
 540         case PVR_460SX_RA:
 541                 puts("460SX Rev. A");
 542                 strcpy(addstr, "Security support");
 543                 break;
 544
 545         case PVR_460SX_RA_V1:
 546                 puts("460SX Rev. A");
 547                 strcpy(addstr, "No Security support");
 548                 break;
 549
 550         case PVR_460GX_RA:
 551                 puts("460GX Rev. A");
 552                 strcpy(addstr, "Security support");
 553                 break;
 554
 555         case PVR_460GX_RA_V1:
 556                 puts("460GX Rev. A");
 557                 strcpy(addstr, "No Security support");
 558                 break;
 559
 560         case PVR_APM821XX_RA:
 561                 puts("APM821XX Rev. A");
 562                 strcpy(addstr, "Security support");
 563                 break;
 564
 565         case PVR_VIRTEX5:
 566                 puts("440x5 VIRTEX5");
 567                 break;
 568 #endif /* CONFIG_440 */
 569
 570         default:
 571                 printf (" UNKNOWN (PVR=%08x)", pvr);
 572                 break;
 573         }
 574
 575         printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
 576                 strmhz(buf, clock),
 577                 sys_info.freqPLB / 1000000,
 578                 get_OPB_freq() / 1000000,
 579                 sys_info.freqEBC / 1000000);
 580 #if defined(CONFIG_PCI) && \
 581         (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
 582          defined(CONFIG_440GR) || defined(CONFIG_440GRX))
 583         printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
 584 #endif
 585         printf(")\n");
 586
 587         if (addstr[0] != 0)
 588                 printf("       %s\n", addstr);
 589
 590 #if defined(I2C_BOOTROM)
 591         printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
 592 #endif  /* I2C_BOOTROM */
 593 #if defined(SDR0_PINSTP_SHIFT)
 594         printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
 595         printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
 596         putc('\n');
 597 #endif  /* SDR0_PINSTP_SHIFT */
 598
 599 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 600         printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
 601 #endif
 602
 603 #if defined(CONFIG_PCI) && defined(PCI_ASYNC)
 604         if (pci_async_enabled()) {
 605                 printf (", PCI async ext clock used");
 606         } else {
 607                 printf (", PCI sync clock at %lu MHz",
 608                        sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
 609         }
 610 #endif
 611
 612 #if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 613         putc('\n');
 614 #endif
 615
 616 #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
 617         printf("       16 KiB I-Cache 16 KiB D-Cache");
 618 #elif defined(CONFIG_440)
 619         printf("       32 KiB I-Cache 32 KiB D-Cache");
 620 #else
 621         printf("       16 KiB I-Cache %d KiB D-Cache",
 622                ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
 623 #endif
 624
 625 #endif /* !defined(CONFIG_405) */
 626
 627         putc ('\n');
 628
 629         return 0;
 630 }
 631
 632 int ppc440spe_revB() {
 633         unsigned int pvr;
 634
 635         pvr = get_pvr();
 636         if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
 637                 return 1;
 638         else
 639                 return 0;
 640 }
 641
 642 /* ------------------------------------------------------------------------- */
 643
 644 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 645 {
 646 #if defined(CONFIG_BOARD_RESET)
 647         board_reset();
 648 #else
 649 #if defined(CONFIG_SYS_4xx_RESET_TYPE)
 650         mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
 651 #else
 652         /*
 653          * Initiate system reset in debug control register DBCR
 654          */
 655         mtspr(SPRN_DBCR0, 0x30000000);
 656 #endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
 657 #endif /* defined(CONFIG_BOARD_RESET) */
 658
 659         return 1;
 660 }
 661
 662
 663 /*
 664  * Get timebase clock frequency
 665  */
 666 unsigned long get_tbclk (void)
 667 {
 668         sys_info_t  sys_info;
 669
 670         get_sys_info(&sys_info);
 671         return (sys_info.freqProcessor);
 672 }
 673
 674
 675 #if defined(CONFIG_WATCHDOG)
 676 void watchdog_reset(void)
 677 {
 678         int re_enable = disable_interrupts();
 679         reset_4xx_watchdog();
 680         if (re_enable) enable_interrupts();
 681 }
 682
 683 void reset_4xx_watchdog(void)
 684 {
 685         /*
 686          * Clear TSR(WIS) bit
 687          */
 688         mtspr(SPRN_TSR, 0x40000000);
 689 }
 690 #endif  /* CONFIG_WATCHDOG */
 691
 692 /*
 693  * Initializes on-chip ethernet controllers.
 694  * to override, implement board_eth_init()
 695  */
 696 int cpu_eth_init(bd_t *bis)
 697 {
 698 #if defined(CONFIG_PPC4xx_EMAC)
 699         ppc_4xx_eth_initialize(bis);
 700 #endif
 701         return 0;
 702 }