[people/ms/u-boot.git] / arch / x86 / Kconfig

menu "x86 architecture"
	depends on X86

config SYS_ARCH
	default "x86"

choice
	prompt "Mainboard vendor"
	default VENDOR_EMULATION

config VENDOR_COREBOOT
	bool "coreboot"

config VENDOR_EFI
	bool "efi"

config VENDOR_EMULATION
	bool "emulation"

config VENDOR_GOOGLE
	bool "Google"

config VENDOR_INTEL
	bool "Intel"

endchoice

# board-specific options below
source "board/coreboot/Kconfig"
source "board/efi/Kconfig"
source "board/emulation/Kconfig"
source "board/google/Kconfig"
source "board/intel/Kconfig"

# platform-specific options below
source "arch/x86/cpu/baytrail/Kconfig"
source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig"
source "arch/x86/cpu/qemu/Kconfig"
source "arch/x86/cpu/quark/Kconfig"
source "arch/x86/cpu/queensbay/Kconfig"

# architecture-specific options below

config SYS_MALLOC_F_LEN
	default 0x800

config RAMBASE
	hex
	default 0x100000

config XIP_ROM_SIZE
	hex
	depends on X86_RESET_VECTOR
	default ROM_SIZE

config CPU_ADDR_BITS
	int
	default 36

config HPET_ADDRESS
	hex
	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

config SMM_TSEG
	bool
	default n

config SMM_TSEG_SIZE
	hex

config X86_RESET_VECTOR
	bool
	default n

config RESET_SEG_START
	hex
	depends on X86_RESET_VECTOR
	default 0xffff0000

config RESET_SEG_SIZE
	hex
	depends on X86_RESET_VECTOR
	default 0x10000

config RESET_VEC_LOC
	hex
	depends on X86_RESET_VECTOR
	default 0xfffffff0

config SYS_X86_START16
	hex
	depends on X86_RESET_VECTOR
	default 0xfffff800

config DM_PCI_COMPAT
	default y	# Until we finish moving over to the new API

config BOARD_ROMSIZE_KB_512
	bool
config BOARD_ROMSIZE_KB_1024
	bool
config BOARD_ROMSIZE_KB_2048
	bool
config BOARD_ROMSIZE_KB_4096
	bool
config BOARD_ROMSIZE_KB_8192
	bool
config BOARD_ROMSIZE_KB_16384
	bool

choice
	prompt "ROM chip size"
	depends on X86_RESET_VECTOR
	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
	help
	  Select the size of the ROM chip you intend to flash U-Boot on.

	  The build system will take care of creating a u-boot.rom file
	  of the matching size.

config UBOOT_ROMSIZE_KB_512
	bool "512 KB"
	help
	  Choose this option if you have a 512 KB ROM chip.

config UBOOT_ROMSIZE_KB_1024
	bool "1024 KB (1 MB)"
	help
	  Choose this option if you have a 1024 KB (1 MB) ROM chip.

config UBOOT_ROMSIZE_KB_2048
	bool "2048 KB (2 MB)"
	help
	  Choose this option if you have a 2048 KB (2 MB) ROM chip.

config UBOOT_ROMSIZE_KB_4096
	bool "4096 KB (4 MB)"
	help
	  Choose this option if you have a 4096 KB (4 MB) ROM chip.

config UBOOT_ROMSIZE_KB_8192
	bool "8192 KB (8 MB)"
	help
	  Choose this option if you have a 8192 KB (8 MB) ROM chip.

config UBOOT_ROMSIZE_KB_16384
	bool "16384 KB (16 MB)"
	help
	  Choose this option if you have a 16384 KB (16 MB) ROM chip.

endchoice

# Map the config names to an integer (KB).
config UBOOT_ROMSIZE_KB
	int
	default 512 if UBOOT_ROMSIZE_KB_512
	default 1024 if UBOOT_ROMSIZE_KB_1024
	default 2048 if UBOOT_ROMSIZE_KB_2048
	default 4096 if UBOOT_ROMSIZE_KB_4096
	default 8192 if UBOOT_ROMSIZE_KB_8192
	default 16384 if UBOOT_ROMSIZE_KB_16384

# Map the config names to a hex value (bytes).
config ROM_SIZE
	hex
	default 0x80000 if UBOOT_ROMSIZE_KB_512
	default 0x100000 if UBOOT_ROMSIZE_KB_1024
	default 0x200000 if UBOOT_ROMSIZE_KB_2048
	default 0x400000 if UBOOT_ROMSIZE_KB_4096
	default 0x800000 if UBOOT_ROMSIZE_KB_8192
	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
	default 0x1000000 if UBOOT_ROMSIZE_KB_16384

config HAVE_INTEL_ME
	bool "Platform requires Intel Management Engine"
	help
	  Newer higher-end devices have an Intel Management Engine (ME)
	  which is a very large binary blob (typically 1.5MB) which is
	  required for the platform to work. This enforces a particular
	  SPI flash format. You will need to supply the me.bin file in
	  your board directory.

config X86_RAMTEST
	bool "Perform a simple RAM test after SDRAM initialisation"
	help
	  If there is something wrong with SDRAM then the platform will
	  often crash within U-Boot or the kernel. This option enables a
	  very simple RAM test that quickly checks whether the SDRAM seems
	  to work correctly. It is not exhaustive but can save time by
	  detecting obvious failures.

config HAVE_FSP
	bool "Add an Firmware Support Package binary"
	depends on !EFI
	help
	  Select this option to add an Firmware Support Package binary to
	  the resulting U-Boot image. It is a binary blob which U-Boot uses
	  to set up SDRAM and other chipset specific initialization.

	  Note: Without this binary U-Boot will not be able to set up its
	  SDRAM so will not boot.

config FSP_FILE
	string "Firmware Support Package binary filename"
	depends on HAVE_FSP
	default "fsp.bin"
	help
	  The filename of the file to use as Firmware Support Package binary
	  in the board directory.

config FSP_ADDR
	hex "Firmware Support Package binary location"
	depends on HAVE_FSP
	default 0xfffc0000
	help
	  FSP is not Position Independent Code (PIC) and the whole FSP has to
	  be rebased if it is placed at a location which is different from the
	  perferred base address specified during the FSP build. Use Intel's
	  Binary Configuration Tool (BCT) to do the rebase.

	  The default base address of 0xfffc0000 indicates that the binary must
	  be located at offset 0xc0000 from the beginning of a 1MB flash device.

config FSP_TEMP_RAM_ADDR
	hex
	depends on HAVE_FSP
	default 0x2000000
	help
	  Stack top address which is used in fsp_init() after DRAM is ready and
	  CAR is disabled.

config FSP_SYS_MALLOC_F_LEN
	hex
	depends on HAVE_FSP
	default 0x100000
	help
	  Additional size of malloc() pool before relocation.

config ENABLE_MRC_CACHE
	bool "Enable MRC cache"
	depends on !EFI && !SYS_COREBOOT
	help
	  Enable this feature to cause MRC data to be cached in NV storage
	  to be used for speeding up boot time on future reboots and/or
	  power cycles.

config SMP
	bool "Enable Symmetric Multiprocessing"
	default n
	help
	  Enable use of more than one CPU in U-Boot and the Operating System
	  when loaded. Each CPU will be started up and information can be
	  obtained using the 'cpu' command. If this option is disabled, then
	  only one CPU will be enabled regardless of the number of CPUs
	  available.

config MAX_CPUS
	int "Maximum number of CPUs permitted"
	depends on SMP
	default 4
	help
	  When using multi-CPU chips it is possible for U-Boot to start up
	  more than one CPU. The stack memory used by all of these CPUs is
	  pre-allocated so at present U-Boot wants to know the maximum
	  number of CPUs that may be present. Set this to at least as high
	  as the number of CPUs in your system (it uses about 4KB of RAM for
	  each CPU).

config AP_STACK_SIZE
	hex
	depends on SMP
	default 0x1000
	help
	  Each additional CPU started by U-Boot requires its own stack. This
	  option sets the stack size used by each CPU and directly affects
	  the memory used by this initialisation process. Typically 4KB is
	  enough space.

config HAVE_VGA_BIOS
	bool "Add a VGA BIOS image"
	help
	  Select this option if you have a VGA BIOS image that you would
	  like to add to your ROM.

config VGA_BIOS_FILE
	string "VGA BIOS image filename"
	depends on HAVE_VGA_BIOS
	default "vga.bin"
	help
	  The filename of the VGA BIOS image in the board directory.

config VGA_BIOS_ADDR
	hex "VGA BIOS image location"
	depends on HAVE_VGA_BIOS
	default 0xfff90000
	help
	  The location of VGA BIOS image in the SPI flash. For example, base
	  address of 0xfff90000 indicates that the image will be put at offset
	  0x90000 from the beginning of a 1MB flash device.

menu "System tables"
	depends on !EFI && !SYS_COREBOOT

config GENERATE_PIRQ_TABLE
	bool "Generate a PIRQ table"
	default n
	help
	  Generate a PIRQ routing table for this board. The PIRQ routing table
	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
	  It specifies the interrupt router information as well how all the PCI
	  devices' interrupt pins are wired to PIRQs.

config GENERATE_SFI_TABLE
	bool "Generate a SFI (Simple Firmware Interface) table"
	help
	  The Simple Firmware Interface (SFI) provides a lightweight method
	  for platform firmware to pass information to the operating system
	  via static tables in memory.  Kernel SFI support is required to
	  boot on SFI-only platforms.  If you have ACPI tables then these are
	  used instead.

	  U-Boot writes this table in write_sfi_table() just before booting
	  the OS.

	  For more information, see http://simplefirmware.org

config GENERATE_MP_TABLE
	bool "Generate an MP (Multi-Processor) table"
	default n
	help
	  Generate an MP (Multi-Processor) table for this board. The MP table
	  provides a way for the operating system to support for symmetric
	  multiprocessing as well as symmetric I/O interrupt handling with
	  the local APIC and I/O APIC.

config GENERATE_ACPI_TABLE
	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
	default n
	help
	  The Advanced Configuration and Power Interface (ACPI) specification
	  provides an open standard for device configuration and management
	  by the operating system. It defines platform-independent interfaces
	  for configuration and power management monitoring.

config GENERATE_SMBIOS_TABLE
	bool "Generate an SMBIOS (System Management BIOS) table"
	default y
	help
	  The System Management BIOS (SMBIOS) specification addresses how
	  motherboard and system vendors present management information about
	  their products in a standard format by extending the BIOS interface
	  on Intel architecture systems.

	  Check http://www.dmtf.org/standards/smbios for details.

endmenu

config MAX_PIRQ_LINKS
	int
	default 8
	help
	  This variable specifies the number of PIRQ interrupt links which are
	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
	  Some newer chipsets offer more than four links, commonly up to PIRQH.

config IRQ_SLOT_COUNT
	int
	default 128
	help
	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
	  which in turns forms a table of exact 4KiB. The default value 128
	  should be enough for most boards. If this does not fit your board,
	  change it according to your needs.

config PCIE_ECAM_BASE
	hex
	default 0xe0000000
	help
	  This is the memory-mapped address of PCI configuration space, which
	  is only available through the Enhanced Configuration Access
	  Mechanism (ECAM) with PCI Express. It can be set up almost
	  anywhere. Before it is set up, it is possible to access PCI
	  configuration space through I/O access, but memory access is more
	  convenient. Using this, PCI can be scanned and configured. This
	  should be set to a region that does not conflict with memory
	  assigned to PCI devices - i.e. the memory and prefetch regions, as
	  passed to pci_set_region().

config PCIE_ECAM_SIZE
	hex
	default 0x10000000
	help
	  This is the size of memory-mapped address of PCI configuration space,
	  which is only available through the Enhanced Configuration Access
	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
	  so a default 0x10000000 size covers all of the 256 buses which is the
	  maximum number of PCI buses as defined by the PCI specification.

config I8259_PIC
	bool
	default y
	help
	  Intel 8259 ISA compatible chipset incorporates two 8259 (master and
	  slave) interrupt controllers. Include this to have U-Boot set up
	  the interrupt correctly.

config I8254_TIMER
	bool
	default y
	help
	  Intel 8254 timer contains three counters which have fixed uses.
	  Include this to have U-Boot set up the timer correctly.

config I8042_KEYB
	default y

config DM_KEYBOARD
	default y

source "arch/x86/lib/efi/Kconfig"

endmenu
Commit	Line	Data
dd84058d MY	1	menu "x86 architecture"
	2	depends on X86
	3
	4	config SYS_ARCH
dd84058d MY	5	default "x86"
	6
	7	choice
65c4ac0a	8	prompt "Mainboard vendor"
99a309f3	9	default VENDOR_EMULATION
dd84058d	10
65c4ac0a BM	11	config VENDOR_COREBOOT
65c4ac0a BM	12	bool "coreboot"
3a1a18ff	13
3dcdd17b BS	14	config VENDOR_EFI
	15	bool "efi"
	16
a65b25d1 BM	17	config VENDOR_EMULATION
	18	bool "emulation"
	19
65c4ac0a BM	20	config VENDOR_GOOGLE
65c4ac0a BM	21	bool "Google"
3a1a18ff	22
65c4ac0a BM	23	config VENDOR_INTEL
65c4ac0a BM	24	bool "Intel"
ef46bea0	25
dd84058d MY	26	endchoice
dd84058d MY	27
65c4ac0a BM	28	# board-specific options below
65c4ac0a BM	29	source "board/coreboot/Kconfig"
3e9aa320	30	source "board/efi/Kconfig"
a65b25d1	31	source "board/emulation/Kconfig"
65c4ac0a BM	32	source "board/google/Kconfig"
	33	source "board/intel/Kconfig"
	34
029194a3 BM	35	# platform-specific options below
	36	source "arch/x86/cpu/baytrail/Kconfig"
	37	source "arch/x86/cpu/coreboot/Kconfig"
	38	source "arch/x86/cpu/ivybridge/Kconfig"
a65b25d1	39	source "arch/x86/cpu/qemu/Kconfig"
029194a3 BM	40	source "arch/x86/cpu/quark/Kconfig"
	41	source "arch/x86/cpu/queensbay/Kconfig"
	42
	43	# architecture-specific options below
	44
b724bd7d SG	45	config SYS_MALLOC_F_LEN
	46	default 0x800
	47
70a09c6c SG	48	config RAMBASE
	49	hex
	50	default 0x100000
	51
70a09c6c SG	52	config XIP_ROM_SIZE
70a09c6c SG	53	hex
7698d36a	54	depends on X86_RESET_VECTOR
bbd43d65	55	default ROM_SIZE
70a09c6c SG	56
	57	config CPU_ADDR_BITS
	58	int
	59	default 36
	60
65dd74a6 SG	61	config HPET_ADDRESS
	62	hex
	63	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
	64
	65	config SMM_TSEG
	66	bool
	67	default n
	68
	69	config SMM_TSEG_SIZE
	70	hex
	71
8cb20ccc BM	72	config X86_RESET_VECTOR
	73	bool
	74	default n
	75
343fb990 BM	76	config RESET_SEG_START
	77	hex
	78	depends on X86_RESET_VECTOR
	79	default 0xffff0000
	80
	81	config RESET_SEG_SIZE
	82	hex
	83	depends on X86_RESET_VECTOR
	84	default 0x10000
	85
	86	config RESET_VEC_LOC
	87	hex
	88	depends on X86_RESET_VECTOR
	89	default 0xfffffff0
	90
8cb20ccc BM	91	config SYS_X86_START16
	92	hex
	93	depends on X86_RESET_VECTOR
	94	default 0xfffff800
	95
3ba5f74a SG	96	config DM_PCI_COMPAT
	97	default y # Until we finish moving over to the new API
	98
64542f46 BM	99	config BOARD_ROMSIZE_KB_512
	100	bool
	101	config BOARD_ROMSIZE_KB_1024
	102	bool
	103	config BOARD_ROMSIZE_KB_2048
	104	bool
	105	config BOARD_ROMSIZE_KB_4096
	106	bool
	107	config BOARD_ROMSIZE_KB_8192
	108	bool
	109	config BOARD_ROMSIZE_KB_16384
	110	bool
	111
	112	choice
	113	prompt "ROM chip size"
7698d36a	114	depends on X86_RESET_VECTOR
64542f46 BM	115	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
	116	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
	117	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
	118	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
	119	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
	120	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
	121	help
	122	Select the size of the ROM chip you intend to flash U-Boot on.
	123
	124	The build system will take care of creating a u-boot.rom file
	125	of the matching size.
	126
	127	config UBOOT_ROMSIZE_KB_512
	128	bool "512 KB"
	129	help
	130	Choose this option if you have a 512 KB ROM chip.
	131
	132	config UBOOT_ROMSIZE_KB_1024
	133	bool "1024 KB (1 MB)"
	134	help
	135	Choose this option if you have a 1024 KB (1 MB) ROM chip.
	136
	137	config UBOOT_ROMSIZE_KB_2048
	138	bool "2048 KB (2 MB)"
	139	help
	140	Choose this option if you have a 2048 KB (2 MB) ROM chip.
	141
	142	config UBOOT_ROMSIZE_KB_4096
	143	bool "4096 KB (4 MB)"
	144	help
	145	Choose this option if you have a 4096 KB (4 MB) ROM chip.
	146
	147	config UBOOT_ROMSIZE_KB_8192
	148	bool "8192 KB (8 MB)"
	149	help
	150	Choose this option if you have a 8192 KB (8 MB) ROM chip.
	151
	152	config UBOOT_ROMSIZE_KB_16384
	153	bool "16384 KB (16 MB)"
	154	help
	155	Choose this option if you have a 16384 KB (16 MB) ROM chip.
	156
	157	endchoice
	158
	159	# Map the config names to an integer (KB).
	160	config UBOOT_ROMSIZE_KB
	161	int
	162	default 512 if UBOOT_ROMSIZE_KB_512
	163	default 1024 if UBOOT_ROMSIZE_KB_1024
	164	default 2048 if UBOOT_ROMSIZE_KB_2048
	165	default 4096 if UBOOT_ROMSIZE_KB_4096
	166	default 8192 if UBOOT_ROMSIZE_KB_8192
	167	default 16384 if UBOOT_ROMSIZE_KB_16384
	168
	169	# Map the config names to a hex value (bytes).
fce7b276 SG	170	config ROM_SIZE
fce7b276 SG	171	hex
64542f46 BM	172	default 0x80000 if UBOOT_ROMSIZE_KB_512
	173	default 0x100000 if UBOOT_ROMSIZE_KB_1024
	174	default 0x200000 if UBOOT_ROMSIZE_KB_2048
	175	default 0x400000 if UBOOT_ROMSIZE_KB_4096
	176	default 0x800000 if UBOOT_ROMSIZE_KB_8192
	177	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
	178	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
fce7b276 SG	179
	180	config HAVE_INTEL_ME
	181	bool "Platform requires Intel Management Engine"
	182	help
	183	Newer higher-end devices have an Intel Management Engine (ME)
	184	which is a very large binary blob (typically 1.5MB) which is
	185	required for the platform to work. This enforces a particular
	186	SPI flash format. You will need to supply the me.bin file in
	187	your board directory.
	188
65dd74a6 SG	189	config X86_RAMTEST
	190	bool "Perform a simple RAM test after SDRAM initialisation"
	191	help
	192	If there is something wrong with SDRAM then the platform will
	193	often crash within U-Boot or the kernel. This option enables a
	194	very simple RAM test that quickly checks whether the SDRAM seems
	195	to work correctly. It is not exhaustive but can save time by
	196	detecting obvious failures.
	197
8ce24cd9 SG	198	config HAVE_FSP
8ce24cd9 SG	199	bool "Add an Firmware Support Package binary"
e49cceac	200	depends on !EFI
8ce24cd9 SG	201	help
	202	Select this option to add an Firmware Support Package binary to
	203	the resulting U-Boot image. It is a binary blob which U-Boot uses
	204	to set up SDRAM and other chipset specific initialization.
	205
	206	Note: Without this binary U-Boot will not be able to set up its
	207	SDRAM so will not boot.
	208
	209	config FSP_FILE
	210	string "Firmware Support Package binary filename"
	211	depends on HAVE_FSP
	212	default "fsp.bin"
	213	help
	214	The filename of the file to use as Firmware Support Package binary
	215	in the board directory.
	216
	217	config FSP_ADDR
	218	hex "Firmware Support Package binary location"
	219	depends on HAVE_FSP
	220	default 0xfffc0000
	221	help
	222	FSP is not Position Independent Code (PIC) and the whole FSP has to
	223	be rebased if it is placed at a location which is different from the
	224	perferred base address specified during the FSP build. Use Intel's
	225	Binary Configuration Tool (BCT) to do the rebase.
	226
	227	The default base address of 0xfffc0000 indicates that the binary must
	228	be located at offset 0xc0000 from the beginning of a 1MB flash device.
	229
	230	config FSP_TEMP_RAM_ADDR
	231	hex
d04e30b8	232	depends on HAVE_FSP
8ce24cd9 SG	233	default 0x2000000
8ce24cd9 SG	234	help
48aa6c26	235	Stack top address which is used in fsp_init() after DRAM is ready and
8ce24cd9 SG	236	CAR is disabled.
8ce24cd9 SG	237
57b10f59 BM	238	config FSP_SYS_MALLOC_F_LEN
	239	hex
	240	depends on HAVE_FSP
	241	default 0x100000
	242	help
	243	Additional size of malloc() pool before relocation.
	244
e2d76e95 BM	245	config ENABLE_MRC_CACHE
	246	bool "Enable MRC cache"
	247	depends on !EFI && !SYS_COREBOOT
	248	help
	249	Enable this feature to cause MRC data to be cached in NV storage
	250	to be used for speeding up boot time on future reboots and/or
	251	power cycles.
	252
45b5a378 SG	253	config SMP
	254	bool "Enable Symmetric Multiprocessing"
	255	default n
	256	help
	257	Enable use of more than one CPU in U-Boot and the Operating System
	258	when loaded. Each CPU will be started up and information can be
	259	obtained using the 'cpu' command. If this option is disabled, then
	260	only one CPU will be enabled regardless of the number of CPUs
	261	available.
	262
4c71322b BM	263	config MAX_CPUS
	264	int "Maximum number of CPUs permitted"
	265	depends on SMP
	266	default 4
	267	help
	268	When using multi-CPU chips it is possible for U-Boot to start up
	269	more than one CPU. The stack memory used by all of these CPUs is
	270	pre-allocated so at present U-Boot wants to know the maximum
	271	number of CPUs that may be present. Set this to at least as high
	272	as the number of CPUs in your system (it uses about 4KB of RAM for
	273	each CPU).
	274
45b5a378 SG	275	config AP_STACK_SIZE
45b5a378 SG	276	hex
063374d2	277	depends on SMP
45b5a378 SG	278	default 0x1000
	279	help
	280	Each additional CPU started by U-Boot requires its own stack. This
	281	option sets the stack size used by each CPU and directly affects
	282	the memory used by this initialisation process. Typically 4KB is
	283	enough space.
	284
786a08e0 BM	285	config HAVE_VGA_BIOS
	286	bool "Add a VGA BIOS image"
	287	help
	288	Select this option if you have a VGA BIOS image that you would
	289	like to add to your ROM.
	290
	291	config VGA_BIOS_FILE
	292	string "VGA BIOS image filename"
	293	depends on HAVE_VGA_BIOS
	294	default "vga.bin"
	295	help
	296	The filename of the VGA BIOS image in the board directory.
	297
	298	config VGA_BIOS_ADDR
	299	hex "VGA BIOS image location"
	300	depends on HAVE_VGA_BIOS
	301	default 0xfff90000
	302	help
	303	The location of VGA BIOS image in the SPI flash. For example, base
	304	address of 0xfff90000 indicates that the image will be put at offset
	305	0x90000 from the beginning of a 1MB flash device.
	306
b5b6b019	307	menu "System tables"
8744bef5	308	depends on !EFI && !SYS_COREBOOT
b5b6b019 BM	309
	310	config GENERATE_PIRQ_TABLE
	311	bool "Generate a PIRQ table"
	312	default n
	313	help
	314	Generate a PIRQ routing table for this board. The PIRQ routing table
	315	is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
	316	at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
	317	It specifies the interrupt router information as well how all the PCI
	318	devices' interrupt pins are wired to PIRQs.
	319
6388e357 SG	320	config GENERATE_SFI_TABLE
	321	bool "Generate a SFI (Simple Firmware Interface) table"
	322	help
	323	The Simple Firmware Interface (SFI) provides a lightweight method
	324	for platform firmware to pass information to the operating system
	325	via static tables in memory. Kernel SFI support is required to
	326	boot on SFI-only platforms. If you have ACPI tables then these are
	327	used instead.
	328
	329	U-Boot writes this table in write_sfi_table() just before booting
	330	the OS.
	331
	332	For more information, see http://simplefirmware.org
	333
07545d86 BM	334	config GENERATE_MP_TABLE
	335	bool "Generate an MP (Multi-Processor) table"
	336	default n
	337	help
	338	Generate an MP (Multi-Processor) table for this board. The MP table
	339	provides a way for the operating system to support for symmetric
	340	multiprocessing as well as symmetric I/O interrupt handling with
	341	the local APIC and I/O APIC.
	342
867bcb63 SS	343	config GENERATE_ACPI_TABLE
	344	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
	345	default n
	346	help
	347	The Advanced Configuration and Power Interface (ACPI) specification
	348	provides an open standard for device configuration and management
	349	by the operating system. It defines platform-independent interfaces
	350	for configuration and power management monitoring.
	351
721e992a BM	352	config GENERATE_SMBIOS_TABLE
	353	bool "Generate an SMBIOS (System Management BIOS) table"
	354	default y
	355	help
	356	The System Management BIOS (SMBIOS) specification addresses how
	357	motherboard and system vendors present management information about
	358	their products in a standard format by extending the BIOS interface
	359	on Intel architecture systems.
	360
	361	Check http://www.dmtf.org/standards/smbios for details.
	362
b5b6b019 BM	363	endmenu
	364
	365	config MAX_PIRQ_LINKS
	366	int
	367	default 8
	368	help
	369	This variable specifies the number of PIRQ interrupt links which are
	370	routable. On most older chipsets, this is 4, PIRQA through PIRQD.
	371	Some newer chipsets offer more than four links, commonly up to PIRQH.
	372
	373	config IRQ_SLOT_COUNT
	374	int
	375	default 128
	376	help
	377	U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
	378	which in turns forms a table of exact 4KiB. The default value 128
	379	should be enough for most boards. If this does not fit your board,
	380	change it according to your needs.
	381
2d934e57 SG	382	config PCIE_ECAM_BASE
2d934e57 SG	383	hex
ba877efb	384	default 0xe0000000
2d934e57 SG	385	help
	386	This is the memory-mapped address of PCI configuration space, which
	387	is only available through the Enhanced Configuration Access
	388	Mechanism (ECAM) with PCI Express. It can be set up almost
	389	anywhere. Before it is set up, it is possible to access PCI
	390	configuration space through I/O access, but memory access is more
	391	convenient. Using this, PCI can be scanned and configured. This
	392	should be set to a region that does not conflict with memory
	393	assigned to PCI devices - i.e. the memory and prefetch regions, as
	394	passed to pci_set_region().
	395
1ed6648b BM	396	config PCIE_ECAM_SIZE
	397	hex
	398	default 0x10000000
	399	help
	400	This is the size of memory-mapped address of PCI configuration space,
	401	which is only available through the Enhanced Configuration Access
	402	Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
	403	so a default 0x10000000 size covers all of the 256 buses which is the
	404	maximum number of PCI buses as defined by the PCI specification.
	405
1eb39a50 BM	406	config I8259_PIC
	407	bool
	408	default y
	409	help
	410	Intel 8259 ISA compatible chipset incorporates two 8259 (master and
	411	slave) interrupt controllers. Include this to have U-Boot set up
	412	the interrupt correctly.
	413
	414	config I8254_TIMER
	415	bool
	416	default y
	417	help
	418	Intel 8254 timer contains three counters which have fixed uses.
	419	Include this to have U-Boot set up the timer correctly.
	420
6b44ae6b SG	421	config I8042_KEYB
	422	default y
	423
	424	config DM_KEYBOARD
	425	default y
	426
e49cceac SG	427	source "arch/x86/lib/efi/Kconfig"
e49cceac SG	428
dd84058d	429	endmenu