[people/ms/u-boot.git] / arch / x86 / include / asm / cache.h

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __X86_CACHE_H__
#define __X86_CACHE_H__

/*
 * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
 * use 64-bytes, a safe default for x86.
 */
#ifndef CONFIG_SYS_CACHELINE_SIZE
#define CONFIG_SYS_CACHELINE_SIZE	64
#endif

#define ARCH_DMA_MINALIGN		CONFIG_SYS_CACHELINE_SIZE

static inline void wbinvd(void)
{
	asm volatile ("wbinvd" : : : "memory");
}

static inline void invd(void)
{
	asm volatile("invd" : : : "memory");
}

/* Enable caches and write buffer */
void enable_caches(void);

/* Disable caches and write buffer */
void disable_caches(void);

#endif /* __X86_CACHE_H__ */
Commit	Line	Data
3620f860 AS	1	/*
3620f860 AS	2	* Copyright (c) 2011 The Chromium OS Authors.
3620f860	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
3620f860 AS	5	*/
	6
	7	#ifndef __X86_CACHE_H__
	8	#define __X86_CACHE_H__
	9
	10	/*
	11	* If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise
	12	* use 64-bytes, a safe default for x86.
	13	*/
bf4ea7ed SR	14	#ifndef CONFIG_SYS_CACHELINE_SIZE
bf4ea7ed SR	15	#define CONFIG_SYS_CACHELINE_SIZE 64
3620f860 AS	16	#endif
3620f860 AS	17
bf4ea7ed SR	18	#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
bf4ea7ed SR	19
095593c0 SR	20	static inline void wbinvd(void)
	21	{
	22	asm volatile ("wbinvd" : : : "memory");
	23	}
	24
	25	static inline void invd(void)
	26	{
	27	asm volatile("invd" : : : "memory");
	28	}
	29
	30	/* Enable caches and write buffer */
	31	void enable_caches(void);
	32
	33	/* Disable caches and write buffer */
	34	void disable_caches(void);
	35
3620f860	36	#endif /* __X86_CACHE_H__ */