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3620f860 AS |
1 | /* |
2 | * Copyright (c) 2011 The Chromium OS Authors. | |
3620f860 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
3620f860 AS |
5 | */ |
6 | ||
7 | #ifndef __X86_CACHE_H__ | |
8 | #define __X86_CACHE_H__ | |
9 | ||
10 | /* | |
11 | * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise | |
12 | * use 64-bytes, a safe default for x86. | |
13 | */ | |
14 | #ifdef CONFIG_SYS_CACHELINE_SIZE | |
15 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE | |
16 | #else | |
17 | #define ARCH_DMA_MINALIGN 64 | |
18 | #endif | |
19 | ||
095593c0 SR |
20 | static inline void wbinvd(void) |
21 | { | |
22 | asm volatile ("wbinvd" : : : "memory"); | |
23 | } | |
24 | ||
25 | static inline void invd(void) | |
26 | { | |
27 | asm volatile("invd" : : : "memory"); | |
28 | } | |
29 | ||
30 | /* Enable caches and write buffer */ | |
31 | void enable_caches(void); | |
32 | ||
33 | /* Disable caches and write buffer */ | |
34 | void disable_caches(void); | |
35 | ||
3620f860 | 36 | #endif /* __X86_CACHE_H__ */ |