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887e2ec9 | 1 | /* |
83a49c8d MF |
2 | * (C) Copyright 2008 |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
887e2ec9 SR |
4 | * |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
25ddd1fb | 24 | #include <asm-offsets.h> |
887e2ec9 | 25 | #include <ppc_asm.tmpl> |
61f2b38a | 26 | #include <asm/mmu.h> |
887e2ec9 SR |
27 | #include <config.h> |
28 | ||
83a49c8d | 29 | /* |
887e2ec9 SR |
30 | * TLB TABLE |
31 | * | |
32 | * This table is used by the cpu boot code to setup the initial tlb | |
33 | * entries. Rather than make broad assumptions in the cpu source tree, | |
34 | * this table lets each board set things up however they like. | |
35 | * | |
36 | * Pointer to the table is returned in r1 | |
83a49c8d | 37 | */ |
887e2ec9 SR |
38 | .section .bootpg,"ax" |
39 | .globl tlbtab | |
40 | ||
41 | tlbtab: | |
42 | tlbtab_start | |
43 | ||
4d332dbe | 44 | /* vxWorks needs this as first entry for the Machine Check interrupt */ |
cf6eb6da | 45 | tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG ) |
887e2ec9 | 46 | |
d873133f SR |
47 | /* |
48 | * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This | |
49 | * entry is already configured for SDRAM via the JTAG debugger and mustn't | |
50 | * be re-initialized by this RAM-booting U-Boot version. | |
51 | */ | |
52 | #ifndef CONFIG_SYS_RAMBOOT | |
887e2ec9 | 53 | /* TLB-entry for DDR SDRAM (Up to 2GB) */ |
ea2e1428 | 54 | #ifdef CONFIG_4xx_DCACHE |
cf6eb6da | 55 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G) |
ea2e1428 | 56 | #else |
cf6eb6da | 57 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG ) |
ea2e1428 | 58 | #endif |
d873133f | 59 | #endif /* CONFIG_SYS_RAMBOOT */ |
887e2ec9 | 60 | |
4d332dbe | 61 | /* TLB-entry for EBC */ |
cf6eb6da | 62 | tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG ) |
4d332dbe NG |
63 | |
64 | /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the | |
65 | * speed up boot process. It is patched after relocation to enable SA_I | |
66 | */ | |
67 | #ifndef CONFIG_NAND_SPL | |
cf6eb6da | 68 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) |
4d332dbe | 69 | #else |
cf6eb6da | 70 | tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G ) |
4d332dbe NG |
71 | #endif |
72 | ||
6d0f6bcf | 73 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
887e2ec9 | 74 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
cf6eb6da | 75 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
887e2ec9 SR |
76 | #endif |
77 | ||
78 | /* TLB-entry for PCI Memory */ | |
cf6eb6da SR |
79 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) |
80 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) | |
81 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) | |
82 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) | |
887e2ec9 | 83 | |
887e2ec9 | 84 | /* TLB-entry for NAND */ |
cf6eb6da | 85 | tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) |
887e2ec9 SR |
86 | |
87 | /* TLB-entry for Internal Registers & OCM */ | |
cf6eb6da | 88 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) |
887e2ec9 SR |
89 | |
90 | /*TLB-entry PCI registers*/ | |
cf6eb6da | 91 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) |
887e2ec9 SR |
92 | |
93 | /* TLB-entry for peripherals */ | |
cf6eb6da | 94 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) |
887e2ec9 | 95 | |
81b73dec | 96 | /* TLB-entry PCI IO Space - from sr@denx.de */ |
cf6eb6da | 97 | tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) |
81b73dec | 98 | |
887e2ec9 SR |
99 | tlbtab_end |
100 | ||
101 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
102 | /* | |
103 | * For NAND booting the first TLB has to be reconfigured to full size | |
104 | * and with caching disabled after running from RAM! | |
105 | */ | |
6d0f6bcf JCPV |
106 | #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) |
107 | #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) | |
cf6eb6da | 108 | #define TLB02 TLB2(AC_RWX | SA_IG) |
887e2ec9 SR |
109 | |
110 | .globl reconfig_tlb0 | |
111 | reconfig_tlb0: | |
112 | sync | |
113 | isync | |
3edf68c4 | 114 | addi r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */ |
887e2ec9 SR |
115 | lis r5,TLB00@h |
116 | ori r5,r5,TLB00@l | |
117 | tlbwe r5,r4,0x0000 /* Save it out */ | |
118 | lis r5,TLB01@h | |
119 | ori r5,r5,TLB01@l | |
120 | tlbwe r5,r4,0x0001 /* Save it out */ | |
121 | lis r5,TLB02@h | |
122 | ori r5,r5,TLB02@l | |
123 | tlbwe r5,r4,0x0002 /* Save it out */ | |
124 | sync | |
125 | isync | |
126 | blr | |
127 | #endif |