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Commit | Line | Data |
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887e2ec9 SR |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <asm/processor.h> | |
27 | #include <ppc440.h> | |
28 | #include "sequoia.h" | |
29 | ||
30 | DECLARE_GLOBAL_DATA_PTR; | |
31 | ||
32 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
33 | ||
34 | int board_early_init_f(void) | |
35 | { | |
36 | unsigned long sdr0_cust0; | |
37 | unsigned long sdr0_pfc1, sdr0_pfc2; | |
38 | register uint reg; | |
39 | ||
40 | mtdcr(ebccfga, xbcfg); | |
41 | mtdcr(ebccfgd, 0xb8400000); | |
42 | ||
43 | /*-------------------------------------------------------------------- | |
44 | * Setup the GPIO pins | |
45 | *-------------------------------------------------------------------*/ | |
46 | /* test-only: take GPIO init from pcs440ep ???? in config file */ | |
47 | out32(GPIO0_OR, 0x00000000); | |
48 | out32(GPIO0_TCR, 0x0000000f); | |
49 | out32(GPIO0_OSRL, 0x50015400); | |
50 | out32(GPIO0_OSRH, 0x550050aa); | |
51 | out32(GPIO0_TSRL, 0x50015400); | |
52 | out32(GPIO0_TSRH, 0x55005000); | |
53 | out32(GPIO0_ISR1L, 0x50000000); | |
54 | out32(GPIO0_ISR1H, 0x00000000); | |
55 | out32(GPIO0_ISR2L, 0x00000000); | |
56 | out32(GPIO0_ISR2H, 0x00000100); | |
57 | out32(GPIO0_ISR3L, 0x00000000); | |
58 | out32(GPIO0_ISR3H, 0x00000000); | |
59 | ||
60 | out32(GPIO1_OR, 0x00000000); | |
61 | out32(GPIO1_TCR, 0xc2000000); | |
62 | out32(GPIO1_OSRL, 0x5c280000); | |
63 | out32(GPIO1_OSRH, 0x00000000); | |
64 | out32(GPIO1_TSRL, 0x0c000000); | |
65 | out32(GPIO1_TSRH, 0x00000000); | |
66 | out32(GPIO1_ISR1L, 0x00005550); | |
67 | out32(GPIO1_ISR1H, 0x00000000); | |
68 | out32(GPIO1_ISR2L, 0x00050000); | |
69 | out32(GPIO1_ISR2H, 0x00000000); | |
70 | out32(GPIO1_ISR3L, 0x01400000); | |
71 | out32(GPIO1_ISR3H, 0x00000000); | |
72 | ||
73 | /*-------------------------------------------------------------------- | |
74 | * Setup the interrupt controller polarities, triggers, etc. | |
75 | *-------------------------------------------------------------------*/ | |
76 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
77 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
78 | mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ | |
79 | mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ | |
80 | mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ | |
81 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ | |
82 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
83 | ||
84 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
85 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
86 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
87 | mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ | |
88 | mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ | |
89 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ | |
90 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
91 | ||
92 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
93 | mtdcr(uic2er, 0x00000000); /* disable all */ | |
94 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ | |
95 | mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ | |
96 | mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ | |
97 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ | |
98 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
99 | ||
100 | /* 50MHz tmrclk */ | |
101 | *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; | |
102 | ||
103 | /* clear write protects */ | |
104 | *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; | |
105 | ||
106 | /* enable Ethernet */ | |
107 | *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00; | |
108 | ||
109 | /* enable USB device */ | |
110 | *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20; | |
111 | ||
112 | /* select Ethernet pins */ | |
113 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
114 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; | |
115 | mfsdr(SDR0_PFC2, sdr0_pfc2); | |
116 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; | |
117 | mtsdr(SDR0_PFC2, sdr0_pfc2); | |
118 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
119 | ||
120 | /* PCI arbiter enabled */ | |
121 | mfsdr(sdr_pci0, reg); | |
122 | mtsdr(sdr_pci0, 0x80000000 | reg); | |
123 | ||
124 | /* setup NAND FLASH */ | |
125 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
126 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | | |
127 | SDR0_CUST0_NDFC_ENABLE | | |
128 | SDR0_CUST0_NDFC_BW_8_BIT | | |
129 | SDR0_CUST0_NDFC_ARE_MASK | | |
130 | (0x80000000 >> (28 + CFG_NAND_CS)); | |
131 | mtsdr(SDR0_CUST0, sdr0_cust0); | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | /*---------------------------------------------------------------------------+ | |
137 | | misc_init_r. | |
138 | +---------------------------------------------------------------------------*/ | |
139 | int misc_init_r(void) | |
140 | { | |
141 | uint pbcr; | |
142 | int size_val = 0; | |
854bc8da | 143 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
144 | unsigned long usb2d0cr = 0; |
145 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
146 | unsigned long sdr0_pfc1; | |
147 | char *act = getenv("usbact"); | |
854bc8da | 148 | #endif |
887e2ec9 SR |
149 | |
150 | /* | |
151 | * FLASH stuff... | |
152 | */ | |
153 | ||
154 | /* Re-do sizing to get full correct info */ | |
155 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) | |
156 | mtdcr(ebccfga, pb3cr); | |
157 | #else | |
158 | mtdcr(ebccfga, pb0cr); | |
159 | #endif | |
160 | pbcr = mfdcr(ebccfgd); | |
161 | switch (gd->bd->bi_flashsize) { | |
162 | case 1 << 20: | |
163 | size_val = 0; | |
164 | break; | |
165 | case 2 << 20: | |
166 | size_val = 1; | |
167 | break; | |
168 | case 4 << 20: | |
169 | size_val = 2; | |
170 | break; | |
171 | case 8 << 20: | |
172 | size_val = 3; | |
173 | break; | |
174 | case 16 << 20: | |
175 | size_val = 4; | |
176 | break; | |
177 | case 32 << 20: | |
178 | size_val = 5; | |
179 | break; | |
180 | case 64 << 20: | |
181 | size_val = 6; | |
182 | break; | |
183 | case 128 << 20: | |
184 | size_val = 7; | |
185 | break; | |
186 | } | |
187 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); | |
188 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) | |
189 | mtdcr(ebccfga, pb3cr); | |
190 | #else | |
191 | mtdcr(ebccfga, pb0cr); | |
192 | #endif | |
193 | mtdcr(ebccfgd, pbcr); | |
194 | ||
195 | /* adjust flash start and offset */ | |
196 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
197 | gd->bd->bi_flashoffset = 0; | |
198 | ||
199 | #ifdef CFG_ENV_IS_IN_FLASH | |
200 | /* Monitor protection ON by default */ | |
201 | (void)flash_protect(FLAG_PROTECT_SET, | |
202 | -CFG_MONITOR_LEN, | |
203 | 0xffffffff, | |
204 | &flash_info[0]); | |
205 | ||
206 | /* Env protection ON by default */ | |
207 | (void)flash_protect(FLAG_PROTECT_SET, | |
208 | CFG_ENV_ADDR_REDUND, | |
209 | CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, | |
210 | &flash_info[0]); | |
211 | #endif | |
212 | ||
213 | /* | |
214 | * USB suff... | |
215 | */ | |
854bc8da | 216 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
217 | if (act == NULL || strcmp(act, "hostdev") == 0) { |
218 | /* SDR Setting */ | |
219 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
220 | mfsdr(SDR0_USB0, usb2d0cr); | |
221 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
222 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
223 | ||
224 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
225 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
226 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; | |
227 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ | |
228 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
229 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ | |
230 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
231 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ | |
232 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
233 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ | |
234 | ||
235 | /* An 8-bit/60MHz interface is the only possible alternative | |
236 | when connecting the Device to the PHY */ | |
237 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
238 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ | |
239 | ||
240 | /* To enable the USB 2.0 Device function through the UTMI interface */ | |
241 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
242 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ | |
243 | ||
244 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
245 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ | |
246 | ||
247 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
248 | mtsdr(SDR0_USB0, usb2d0cr); | |
249 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
250 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
251 | ||
252 | /*clear resets*/ | |
253 | udelay (1000); | |
254 | mtsdr(SDR0_SRST1, 0x00000000); | |
255 | udelay (1000); | |
256 | mtsdr(SDR0_SRST0, 0x00000000); | |
257 | ||
258 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
259 | ||
260 | } else if (strcmp(act, "dev") == 0) { | |
261 | /*-------------------PATCH-------------------------------*/ | |
262 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
263 | ||
264 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
265 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
266 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
267 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ | |
268 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
269 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ | |
270 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
271 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ | |
272 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
273 | ||
274 | udelay (1000); | |
275 | mtsdr(SDR0_SRST1, 0x672c6000); | |
276 | ||
277 | udelay (1000); | |
278 | mtsdr(SDR0_SRST0, 0x00000080); | |
279 | ||
280 | udelay (1000); | |
281 | mtsdr(SDR0_SRST1, 0x60206000); | |
282 | ||
283 | *(unsigned int *)(0xe0000350) = 0x00000001; | |
284 | ||
285 | udelay (1000); | |
286 | mtsdr(SDR0_SRST1, 0x60306000); | |
287 | /*-------------------PATCH-------------------------------*/ | |
288 | ||
289 | /* SDR Setting */ | |
290 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
291 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
292 | mfsdr(SDR0_USB0, usb2d0cr); | |
293 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
294 | ||
295 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
296 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
297 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; | |
298 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ | |
299 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
300 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ | |
301 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; | |
302 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ | |
303 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; | |
304 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ | |
305 | ||
306 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
307 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ | |
308 | ||
309 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
310 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ | |
311 | ||
312 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
313 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ | |
314 | ||
315 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
316 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
317 | mtsdr(SDR0_USB0, usb2d0cr); | |
318 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
319 | ||
320 | /*clear resets*/ | |
321 | udelay (1000); | |
322 | mtsdr(SDR0_SRST1, 0x00000000); | |
323 | udelay (1000); | |
324 | mtsdr(SDR0_SRST0, 0x00000000); | |
325 | ||
326 | printf("USB: Device(int phy)\n"); | |
327 | } | |
854bc8da | 328 | #endif /* CONFIG_440EPX */ |
887e2ec9 SR |
329 | |
330 | return 0; | |
331 | } | |
332 | ||
333 | int checkboard(void) | |
334 | { | |
335 | char *s = getenv("serial#"); | |
336 | ||
854bc8da | 337 | #ifdef CONFIG_440EPX |
887e2ec9 | 338 | printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); |
854bc8da SR |
339 | #else |
340 | printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); | |
341 | #endif | |
887e2ec9 SR |
342 | if (s != NULL) { |
343 | puts(", serial# "); | |
344 | puts(s); | |
345 | } | |
346 | putc('\n'); | |
347 | ||
348 | return (0); | |
349 | } | |
350 | ||
351 | #if defined(CFG_DRAM_TEST) | |
352 | int testdram(void) | |
353 | { | |
354 | unsigned long *mem = (unsigned long *)0; | |
355 | const unsigned long kend = (1024 / sizeof(unsigned long)); | |
356 | unsigned long k, n; | |
357 | ||
358 | mtmsr(0); | |
359 | ||
360 | for (k = 0; k < CFG_MBYTES_SDRAM; | |
361 | ++k, mem += (1024 / sizeof(unsigned long))) { | |
362 | if ((k & 1023) == 0) { | |
363 | printf("%3d MB\r", k / 1024); | |
364 | } | |
365 | ||
366 | memset(mem, 0xaaaaaaaa, 1024); | |
367 | for (n = 0; n < kend; ++n) { | |
368 | if (mem[n] != 0xaaaaaaaa) { | |
369 | printf("SDRAM test fails at: %08x\n", | |
370 | (uint) & mem[n]); | |
371 | return 1; | |
372 | } | |
373 | } | |
374 | ||
375 | memset(mem, 0x55555555, 1024); | |
376 | for (n = 0; n < kend; ++n) { | |
377 | if (mem[n] != 0x55555555) { | |
378 | printf("SDRAM test fails at: %08x\n", | |
379 | (uint) & mem[n]); | |
380 | return 1; | |
381 | } | |
382 | } | |
383 | } | |
384 | printf("SDRAM test passes\n"); | |
385 | return 0; | |
386 | } | |
387 | #endif | |
388 | ||
389 | /************************************************************************* | |
390 | * pci_pre_init | |
391 | * | |
392 | * This routine is called just prior to registering the hose and gives | |
393 | * the board the opportunity to check things. Returning a value of zero | |
394 | * indicates that things are bad & PCI initialization should be aborted. | |
395 | * | |
396 | * Different boards may wish to customize the pci controller structure | |
397 | * (add regions, override default access routines, etc) or perform | |
398 | * certain pre-initialization actions. | |
399 | * | |
400 | ************************************************************************/ | |
401 | #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) | |
402 | int pci_pre_init(struct pci_controller *hose) | |
403 | { | |
404 | unsigned long addr; | |
405 | #if 0 | |
406 | /*--------------------------------------------------------------------------+ | |
407 | * Cactus is always configured as the host & requires the | |
408 | * PCI arbiter to be enabled ??? | |
409 | *--------------------------------------------------------------------------*/ | |
410 | unsigned long strap; | |
411 | mfsdr(sdr_sdstp1, strap); | |
412 | if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { | |
413 | printf("PCI: SDR0_STRP1[PAE] not set.\n"); | |
414 | printf("PCI: Configuration aborted.\n"); | |
415 | return 0; | |
416 | } | |
417 | #endif | |
418 | ||
419 | /*-------------------------------------------------------------------------+ | |
420 | | Set priority for all PLB3 devices to 0. | |
421 | | Set PLB3 arbiter to fair mode. | |
422 | +-------------------------------------------------------------------------*/ | |
423 | mfsdr(sdr_amp1, addr); | |
424 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
425 | addr = mfdcr(plb3_acr); | |
426 | mtdcr(plb3_acr, addr | 0x80000000); | |
427 | ||
428 | /*-------------------------------------------------------------------------+ | |
429 | | Set priority for all PLB4 devices to 0. | |
430 | +-------------------------------------------------------------------------*/ | |
431 | mfsdr(sdr_amp0, addr); | |
432 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
433 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
434 | mtdcr(plb4_acr, addr); | |
435 | ||
436 | /*-------------------------------------------------------------------------+ | |
437 | | Set Nebula PLB4 arbiter to fair mode. | |
438 | +-------------------------------------------------------------------------*/ | |
439 | /* Segment0 */ | |
440 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
441 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
442 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
443 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
444 | mtdcr(plb0_acr, addr); | |
445 | ||
446 | /* Segment1 */ | |
447 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
448 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
449 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
450 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
451 | mtdcr(plb1_acr, addr); | |
452 | ||
453 | return 1; | |
454 | } | |
455 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ | |
456 | ||
457 | /************************************************************************* | |
458 | * pci_target_init | |
459 | * | |
460 | * The bootstrap configuration provides default settings for the pci | |
461 | * inbound map (PIM). But the bootstrap config choices are limited and | |
462 | * may not be sufficient for a given board. | |
463 | * | |
464 | ************************************************************************/ | |
465 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) | |
466 | void pci_target_init(struct pci_controller *hose) | |
467 | { | |
468 | /*--------------------------------------------------------------------------+ | |
469 | * Set up Direct MMIO registers | |
470 | *--------------------------------------------------------------------------*/ | |
471 | /*--------------------------------------------------------------------------+ | |
472 | | PowerPC440EPX PCI Master configuration. | |
473 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
474 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF | |
475 | | Use byte reversed out routines to handle endianess. | |
476 | | Make this region non-prefetchable. | |
477 | +--------------------------------------------------------------------------*/ | |
478 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
479 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ | |
480 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ | |
481 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
482 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
483 | ||
484 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
485 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ | |
486 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ | |
487 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
488 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
489 | ||
490 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
491 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ | |
492 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
493 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
494 | ||
495 | /*--------------------------------------------------------------------------+ | |
496 | * Set up Configuration registers | |
497 | *--------------------------------------------------------------------------*/ | |
498 | ||
499 | /* Program the board's subsystem id/vendor id */ | |
500 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
501 | CFG_PCI_SUBSYS_VENDORID); | |
502 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); | |
503 | ||
504 | /* Configure command register as bus master */ | |
505 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
506 | ||
507 | /* 240nS PCI clock */ | |
508 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
509 | ||
510 | /* No error reporting */ | |
511 | pci_write_config_word(0, PCI_ERREN, 0); | |
512 | ||
513 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
514 | ||
515 | } | |
516 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ | |
517 | ||
518 | /************************************************************************* | |
519 | * pci_master_init | |
520 | * | |
521 | ************************************************************************/ | |
522 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) | |
523 | void pci_master_init(struct pci_controller *hose) | |
524 | { | |
525 | unsigned short temp_short; | |
526 | ||
527 | /*--------------------------------------------------------------------------+ | |
528 | | Write the PowerPC440 EP PCI Configuration regs. | |
529 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
530 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
531 | +--------------------------------------------------------------------------*/ | |
532 | pci_read_config_word(0, PCI_COMMAND, &temp_short); | |
533 | pci_write_config_word(0, PCI_COMMAND, | |
534 | temp_short | PCI_COMMAND_MASTER | | |
535 | PCI_COMMAND_MEMORY); | |
536 | } | |
537 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ | |
538 | ||
539 | /************************************************************************* | |
540 | * is_pci_host | |
541 | * | |
542 | * This routine is called to determine if a pci scan should be | |
543 | * performed. With various hardware environments (especially cPCI and | |
544 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
545 | * bit in the strap register, or generic host/adapter assumptions. | |
546 | * | |
547 | * Rather than hard-code a bad assumption in the general 440 code, the | |
548 | * 440 pci code requires the board to decide at runtime. | |
549 | * | |
550 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
551 | * | |
552 | * | |
553 | ************************************************************************/ | |
554 | #if defined(CONFIG_PCI) | |
555 | int is_pci_host(struct pci_controller *hose) | |
556 | { | |
557 | /* Cactus is always configured as host. */ | |
558 | return (1); | |
559 | } | |
560 | #endif /* defined(CONFIG_PCI) */ |