[people/ms/u-boot.git] / board / amcc / yosemite / yosemite.c

/*
 * (C) Copyright 2006-2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/

int board_early_init_f(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr(ebccfga, xbcfg);
	reg = mfdcr(ebccfgd);
	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */

	/*--------------------------------------------------------------------
	 * Setup the GPIO pins
	 *-------------------------------------------------------------------*/
	/*CPLD cs */
	/*setup Address lines for flash size 64Meg. */
	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);

	/*setup emac */
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);

	/*UART1 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);

	/* external interrupts IRQ0...3 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);

#ifdef CONFIG_440EP
	/*setup USB 2.0 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
#endif

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	/*--------------------------------------------------------------------
	 * Setup other serial configuration
	 *-------------------------------------------------------------------*/
	mfsdr(sdr_pci0, reg);
	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */

	/*clear tmrclk divisor */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;

	/*enable ethernet */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;

#ifdef CONFIG_440EP
	/*enable usb 1.1 fs device and remove usb 2.0 reset */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
#endif

	/*get rid of flash write protect */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;

	return 0;
}

int misc_init_r (void)
{
	uint pbcr;
	int size_val = 0;

	/* Re-do sizing to get full correct info */
	mtdcr(ebccfga, pb0cr);
	pbcr = mfdcr(ebccfgd);
	switch (gd->bd->bi_flashsize) {
	case 1 << 20:
		size_val = 0;
		break;
	case 2 << 20:
		size_val = 1;
		break;
	case 4 << 20:
		size_val = 2;
		break;
	case 8 << 20:
		size_val = 3;
		break;
	case 16 << 20:
		size_val = 4;
		break;
	case 32 << 20:
		size_val = 5;
		break;
	case 64 << 20:
		size_val = 6;
		break;
	case 128 << 20:
		size_val = 7;
		break;
	}
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
	mtdcr(ebccfga, pb0cr);
	mtdcr(ebccfgd, pbcr);

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CONFIG_SYS_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[0]);

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");
	u8 rev;
	u8 val;

#ifdef CONFIG_440EP
	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
#else
	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
#endif

	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
	val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

/*************************************************************************
 *  initdram -- doesn't use serial presence detect.
 *
 *  Assumes:    256 MB, ECC, non-registered
 *              PLB @ 133 MHz
 *
 ************************************************************************/
#define NUM_TRIES 64
#define NUM_READS 10

void sdram_tr1_set(int ram_address, int* tr1_value)
{
	int i;
	int j, k;
	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
	int first_good = -1, last_bad = 0x1ff;

	unsigned long test[NUM_TRIES] = {
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };

	/* go through all possible SDRAM0_TR1[RDCT] values */
	for (i=0; i<=0x1ff; i++) {
		/* set the current value for TR1 */
		mtsdram(mem_tr1, (0x80800800 | i));

		/* write values */
		for (j=0; j<NUM_TRIES; j++) {
			ram_pointer[j] = test[j];

			/* clear any cache at ram location */
			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
		}

		/* read values back */
		for (j=0; j<NUM_TRIES; j++) {
			for (k=0; k<NUM_READS; k++) {
				/* clear any cache at ram location */
				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));

				if (ram_pointer[j] != test[j])
					break;
			}

			/* read error */
			if (k != NUM_READS) {
				break;
			}
		}

		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
		if (j == NUM_TRIES) {
			if (first_good == -1)
				first_good = i;		/* found beginning of window */
		} else { /* bad read */
			/* if we have not had a good read then don't care */
			if(first_good != -1) {
				/* first failure after a good read */
				last_bad = i-1;
				break;
			}
		}
	}

	/* return the current value for TR1 */
	*tr1_value = (first_good + last_bad) / 2;
}

phys_size_t initdram(int board)
{
	register uint reg;
	int tr1_bank1, tr1_bank2;

	/*--------------------------------------------------------------------
	 * Setup some default
	 *------------------------------------------------------------------*/
	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
	mtsdram(mem_clktr, 0x40000000);	/* ?? */
	mtsdram(mem_wddctr, 0x40000000);	/* ?? */

	/*clear this first, if the DDR is enabled by a debugger
	  then you can not make changes. */
	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */

	/*--------------------------------------------------------------------
	 * Setup for board-specific specific mem
	 *------------------------------------------------------------------*/
	/*
	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
	 */
	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */

	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
	mtsdram(mem_rtr, 0x04080000);	/* ?? */
	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
	mtsdram(mem_cfg0, 0x30000000);	/* Disable EEC */
	udelay(400);		/* Delay 200 usecs (min)            */

	/*--------------------------------------------------------------------
	 * Enable the controller, then wait for DCEN to complete
	 *------------------------------------------------------------------*/
	mtsdram(mem_cfg0, 0x80000000);	/* Enable */

	for (;;) {
		mfsdram(mem_mcsts, reg);
		if (reg & 0x80000000)
			break;
	}

	sdram_tr1_set(0x00000000, &tr1_bank1);
	sdram_tr1_set(0x08000000, &tr1_bank2);
	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));

	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);	/* return bytes */
}

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
	unsigned long addr;

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB3 devices to 0.
	  | Set PLB3 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp1, addr);
	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb3_acr);
	mtdcr(plb3_acr, addr | 0x80000000);

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB4 devices to 0.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp0, addr);
	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
	mtdcr(plb4_acr, addr);

	/*-------------------------------------------------------------------------+
	  | Set Nebula PLB4 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	/* Segment0 */
	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
	mtdcr(plb0_acr, addr);

	/* Segment1 */
	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
	mtdcr(plb1_acr, addr);

	return 1;
}
#endif	/* defined(CONFIG_PCI) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
	/*--------------------------------------------------------------------------+
	 * Set up Direct MMIO registers
	 *--------------------------------------------------------------------------*/
	/*--------------------------------------------------------------------------+
	  | PowerPC440 EP PCI Master configuration.
	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	  |   Use byte reversed out routines to handle endianess.
	  | Make this region non-prefetchable.
	  +--------------------------------------------------------------------------*/
	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */

	/*--------------------------------------------------------------------------+
	 * Set up Configuration registers
	 *--------------------------------------------------------------------------*/

	/* Program the board's subsystem id/vendor id */
	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);

	/* Configure command register as bus master */
	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);

	/* 240nS PCI clock */
	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);

	/* No error reporting */
	pci_write_config_word(0, PCI_ERREN, 0);

	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);

}
#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */

/*************************************************************************
 *  pci_master_init
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
	unsigned short temp_short;

	/*--------------------------------------------------------------------------+
	  | Write the PowerPC440 EP PCI Configuration regs.
	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
	  +--------------------------------------------------------------------------*/
	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	pci_write_config_word(0, PCI_COMMAND,
			      temp_short | PCI_COMMAND_MASTER |
			      PCI_COMMAND_MEMORY);
}
#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* Bamboo is always configured as host. */
	return (1);
}
#endif				/* defined(CONFIG_PCI) */

/*************************************************************************
 *  hw_watchdog_reset
 *
 *	This routine is called to reset (keep alive) the watchdog timer
 *
 ************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{

}
#endif

void board_reset(void)
{
	/* give reset to BCSR */
	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
}
Commit	Line	Data
c157d8e2	1	/*
5a5958b7 SR	2	* (C) Copyright 2006-2007
5a5958b7 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
c157d8e2 SR	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
84286386	25	#include <ppc4xx.h>
c157d8e2	26	#include <asm/processor.h>
5a5958b7	27	#include <asm/io.h>
c157d8e2	28	#include <spd_sdram.h>
4adb3023 IS	29	#include <libfdt.h>
4adb3023 IS	30	#include <fdt_support.h>
c157d8e2	31
d87080b7 WD	32	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	33
6d0f6bcf	34	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
84286386	35
c157d8e2 SR	36	int board_early_init_f(void)
	37	{
	38	register uint reg;
	39
	40	/*--------------------------------------------------------------------
	41	* Setup the external bus controller/chip selects
	42	-------------------------------------------------------------------/
	43	mtdcr(ebccfga, xbcfg);
	44	reg = mfdcr(ebccfgd);
	45	mtdcr(ebccfgd, reg \| 0x04000000); /* Set ATC */
	46
c157d8e2 SR	47	/*--------------------------------------------------------------------
	48	* Setup the GPIO pins
	49	-------------------------------------------------------------------/
	50	/CPLD cs /
81a3170b SR	51	/setup Address lines for flash size 64Meg. /
	52	out32(GPIO0_OSRL, in32(GPIO0_OSRL) \| 0x50010000);
	53	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x50010000);
	54	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x50000000);
c157d8e2 SR	55
	56	/setup emac /
	57	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xC080);
	58	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x40);
	59	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x55);
	60	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0x50004000);
	61	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) \| 0x00440000);
	62
	63	/UART1 /
	64	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0x02000000);
	65	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x00080000);
	66	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) \| 0x00010000);
	67
e190290b	68	/* external interrupts IRQ0...3 */
b9b2480f WD	69	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
b9b2480f WD	70	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
e190290b SR	71	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) \| 0x00005500);
e190290b SR	72
700200c6	73	#ifdef CONFIG_440EP
c157d8e2 SR	74	/setup USB 2.0 /
	75	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0xc0000000);
	76	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x50000000);
	77	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xf);
	78	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0xaa);
	79	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) \| 0x00000500);
700200c6	80	#endif
c157d8e2	81
ef04a0aa SR	82	/*--------------------------------------------------------------------
	83	* Setup the interrupt controller polarities, triggers, etc.
	84	-------------------------------------------------------------------/
	85	mtdcr(uic0sr, 0xffffffff); /* clear all */
	86	mtdcr(uic0er, 0x00000000); /* disable all */
	87	mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
	88	mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
	89	mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
	90	mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
	91	mtdcr(uic0sr, 0xffffffff); /* clear all */
	92
	93	mtdcr(uic1sr, 0xffffffff); /* clear all */
	94	mtdcr(uic1er, 0x00000000); /* disable all */
	95	mtdcr(uic1cr, 0x00000000); /* all non-critical */
	96	mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
	97	mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
	98	mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
	99	mtdcr(uic1sr, 0xffffffff); /* clear all */
	100
c157d8e2 SR	101	/*--------------------------------------------------------------------
	102	* Setup other serial configuration
	103	-------------------------------------------------------------------/
	104	mfsdr(sdr_pci0, reg);
	105	mtsdr(sdr_pci0, 0x80000000 \| reg); /* PCI arbiter enabled */
	106	mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
	107	mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
	108
	109	/clear tmrclk divisor /
6d0f6bcf	110	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x04) = 0x00;
c157d8e2 SR	111
c157d8e2 SR	112	/enable ethernet /
6d0f6bcf	113	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x08) = 0xf0;
c157d8e2	114
700200c6	115	#ifdef CONFIG_440EP
c157d8e2	116	/enable usb 1.1 fs device and remove usb 2.0 reset /
6d0f6bcf	117	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x09) = 0x00;
700200c6	118	#endif
c157d8e2 SR	119
c157d8e2 SR	120	/get rid of flash write protect /
6d0f6bcf	121	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x07) = 0x00;
c157d8e2 SR	122
	123	return 0;
	124	}
	125
84286386 SR	126	int misc_init_r (void)
84286386 SR	127	{
84286386 SR	128	uint pbcr;
	129	int size_val = 0;
	130
	131	/* Re-do sizing to get full correct info */
	132	mtdcr(ebccfga, pb0cr);
	133	pbcr = mfdcr(ebccfgd);
	134	switch (gd->bd->bi_flashsize) {
	135	case 1 << 20:
	136	size_val = 0;
	137	break;
	138	case 2 << 20:
	139	size_val = 1;
	140	break;
	141	case 4 << 20:
	142	size_val = 2;
	143	break;
	144	case 8 << 20:
	145	size_val = 3;
	146	break;
	147	case 16 << 20:
	148	size_val = 4;
	149	break;
	150	case 32 << 20:
	151	size_val = 5;
	152	break;
	153	case 64 << 20:
	154	size_val = 6;
	155	break;
	156	case 128 << 20:
	157	size_val = 7;
	158	break;
	159	}
	160	pbcr = (pbcr & 0x0001ffff) \| gd->bd->bi_flashstart \| (size_val << 17);
	161	mtdcr(ebccfga, pb0cr);
	162	mtdcr(ebccfgd, pbcr);
	163
f190c11b SR	164	/* adjust flash start and offset */
	165	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	166	gd->bd->bi_flashoffset = 0;
	167
84286386 SR	168	/* Monitor protection ON by default */
84286386 SR	169	(void)flash_protect(FLAG_PROTECT_SET,
6d0f6bcf	170	-CONFIG_SYS_MONITOR_LEN,
84286386 SR	171	0xffffffff,
	172	&flash_info[0]);
	173
	174	return 0;
	175	}
	176
c157d8e2 SR	177	int checkboard(void)
c157d8e2 SR	178	{
3d9569b2	179	char *s = getenv("serial#");
36adff36 SR	180	u8 rev;
36adff36 SR	181	u8 val;
c157d8e2	182
700200c6	183	#ifdef CONFIG_440EP
93b17ec3	184	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
700200c6 SR	185	#else
	186	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
	187	#endif
36adff36	188
6d0f6bcf JCPV	189	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
6d0f6bcf JCPV	190	val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
36adff36 SR	191	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
36adff36 SR	192
93b17ec3 SR	193	if (s != NULL) {
	194	puts(", serial# ");
	195	puts(s);
	196	}
	197	putc('\n');
	198
c157d8e2 SR	199	return (0);
	200	}
	201
	202	/*************************************************************************
bbeff30c	203	* initdram -- doesn't use serial presence detect.
c157d8e2 SR	204	*
	205	* Assumes: 256 MB, ECC, non-registered
	206	* PLB @ 133 MHz
	207	*
	208	************************************************************************/
81a3170b SR	209	#define NUM_TRIES 64
	210	#define NUM_READS 10
	211
	212	void sdram_tr1_set(int ram_address, int* tr1_value)
	213	{
	214	int i;
	215	int j, k;
	216	volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
	217	int first_good = -1, last_bad = 0x1ff;
	218
	219	unsigned long test[NUM_TRIES] = {
	220	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
	221	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
	222	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
	223	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
	224	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
	225	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
	226	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
	227	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
	228	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
	229	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
	230	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
	231	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
	232	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
	233	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
	234	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
	235	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
	236
	237	/* go through all possible SDRAM0_TR1[RDCT] values */
	238	for (i=0; i<=0x1ff; i++) {
	239	/* set the current value for TR1 */
	240	mtsdram(mem_tr1, (0x80800800 \| i));
	241
	242	/* write values */
	243	for (j=0; j<NUM_TRIES; j++) {
	244	ram_pointer[j] = test[j];
	245
	246	/* clear any cache at ram location */
	247	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
	248	}
	249
	250	/* read values back */
	251	for (j=0; j<NUM_TRIES; j++) {
	252	for (k=0; k<NUM_READS; k++) {
	253	/* clear any cache at ram location */
	254	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
	255
	256	if (ram_pointer[j] != test[j])
	257	break;
	258	}
	259
	260	/* read error */
	261	if (k != NUM_READS) {
	262	break;
	263	}
	264	}
	265
	266	/* we have a SDRAM0_TR1[RDCT] that is part of the window */
	267	if (j == NUM_TRIES) {
	268	if (first_good == -1)
	269	first_good = i; /* found beginning of window */
	270	} else { /* bad read */
	271	/* if we have not had a good read then don't care */
	272	if(first_good != -1) {
273	/* first failure after a good read */
274	last_bad = i-1;
275	break;
276	}
277	}
278	}
279
280	/* return the current value for TR1 */
281	*tr1_value = (first_good + last_bad) / 2;
282	}
283
9973e3c6	284	phys_size_t initdram(int board)
c157d8e2 SR	285	{
c157d8e2 SR	286	register uint reg;
81a3170b	287	int tr1_bank1, tr1_bank2;
c157d8e2 SR	288
	289	/*--------------------------------------------------------------------
	290	* Setup some default
	291	------------------------------------------------------------------/
	292	mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
	293	mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	294	mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
	295	mtsdram(mem_clktr, 0x40000000); /* ?? */
	296	mtsdram(mem_wddctr, 0x40000000); /* ?? */
	297
	298	/*clear this first, if the DDR is enabled by a debugger
81a3170b	299	then you can not make changes. */
c157d8e2 SR	300	mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
	301
	302	/*--------------------------------------------------------------------
	303	* Setup for board-specific specific mem
	304	------------------------------------------------------------------/
	305	/*
	306	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	307	*/
	308	mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
	309	mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
	310
	311	mtsdram(mem_tr0, 0x410a4012); /* ?? */
c157d8e2 SR	312	mtsdram(mem_rtr, 0x04080000); /* ?? */
c157d8e2 SR	313	mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
a2c95a72	314	mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
c157d8e2 SR	315	udelay(400); /* Delay 200 usecs (min) */
	316
	317	/*--------------------------------------------------------------------
	318	* Enable the controller, then wait for DCEN to complete
	319	------------------------------------------------------------------/
a2c95a72	320	mtsdram(mem_cfg0, 0x80000000); /* Enable */
c157d8e2 SR	321
	322	for (;;) {
	323	mfsdram(mem_mcsts, reg);
	324	if (reg & 0x80000000)
	325	break;
	326	}
81a3170b SR	327
	328	sdram_tr1_set(0x00000000, &tr1_bank1);
	329	sdram_tr1_set(0x08000000, &tr1_bank2);
bbeff30c	330	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) \| 0x80800800));
c157d8e2	331
6d0f6bcf	332	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
c157d8e2 SR	333	}
c157d8e2 SR	334
c157d8e2 SR	335	/*************************************************************************
	336	* pci_pre_init
	337	*
	338	* This routine is called just prior to registering the hose and gives
	339	* the board the opportunity to check things. Returning a value of zero
	340	* indicates that things are bad & PCI initialization should be aborted.
	341	*
	342	* Different boards may wish to customize the pci controller structure
	343	* (add regions, override default access routines, etc) or perform
	344	* certain pre-initialization actions.
	345	*
	346	************************************************************************/
466fff1a	347	#if defined(CONFIG_PCI)
c157d8e2 SR	348	int pci_pre_init(struct pci_controller *hose)
c157d8e2 SR	349	{
c157d8e2 SR	350	unsigned long addr;
c157d8e2 SR	351
c157d8e2 SR	352	/*-------------------------------------------------------------------------+
	353	\| Set priority for all PLB3 devices to 0.
	354	\| Set PLB3 arbiter to fair mode.
	355	+-------------------------------------------------------------------------*/
	356	mfsdr(sdr_amp1, addr);
	357	mtsdr(sdr_amp1, (addr & 0x000000FF) \| 0x0000FF00);
	358	addr = mfdcr(plb3_acr);
	359	mtdcr(plb3_acr, addr \| 0x80000000);
	360
	361	/*-------------------------------------------------------------------------+
	362	\| Set priority for all PLB4 devices to 0.
	363	+-------------------------------------------------------------------------*/
	364	mfsdr(sdr_amp0, addr);
	365	mtsdr(sdr_amp0, (addr & 0x000000FF) \| 0x0000FF00);
	366	addr = mfdcr(plb4_acr) \| 0xa0000000; /* Was 0x8---- */
	367	mtdcr(plb4_acr, addr);
	368
	369	/*-------------------------------------------------------------------------+
	370	\| Set Nebula PLB4 arbiter to fair mode.
	371	+-------------------------------------------------------------------------*/
	372	/* Segment0 */
	373	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) \| plb0_acr_ppm_fair;
	374	addr = (addr & ~plb0_acr_hbu_mask) \| plb0_acr_hbu_enabled;
	375	addr = (addr & ~plb0_acr_rdp_mask) \| plb0_acr_rdp_4deep;
	376	addr = (addr & ~plb0_acr_wrp_mask) \| plb0_acr_wrp_2deep;
	377	mtdcr(plb0_acr, addr);
	378
	379	/* Segment1 */
	380	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) \| plb1_acr_ppm_fair;
	381	addr = (addr & ~plb1_acr_hbu_mask) \| plb1_acr_hbu_enabled;
	382	addr = (addr & ~plb1_acr_rdp_mask) \| plb1_acr_rdp_4deep;
	383	addr = (addr & ~plb1_acr_wrp_mask) \| plb1_acr_wrp_2deep;
	384	mtdcr(plb1_acr, addr);
	385
	386	return 1;
	387	}
466fff1a	388	#endif /* defined(CONFIG_PCI) */
c157d8e2 SR	389
	390	/*************************************************************************
	391	* pci_target_init
	392	*
	393	* The bootstrap configuration provides default settings for the pci
	394	* inbound map (PIM). But the bootstrap config choices are limited and
	395	* may not be sufficient for a given board.
	396	*
	397	************************************************************************/
6d0f6bcf	398	#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
c157d8e2 SR	399	void pci_target_init(struct pci_controller *hose)
	400	{
	401	/*--------------------------------------------------------------------------+
	402	* Set up Direct MMIO registers
	403	--------------------------------------------------------------------------/
	404	/*--------------------------------------------------------------------------+
	405	\| PowerPC440 EP PCI Master configuration.
	406	\| Map one 1Gig range of PLB/processor addresses to PCI memory space.
	407	\| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	408	\| Use byte reversed out routines to handle endianess.
	409	\| Make this region non-prefetchable.
	410	+--------------------------------------------------------------------------*/
	411	out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
6d0f6bcf JCPV	412	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
6d0f6bcf JCPV	413	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
c157d8e2 SR	414	out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
	415	out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
	416
	417	out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
6d0f6bcf JCPV	418	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
6d0f6bcf JCPV	419	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
c157d8e2 SR	420	out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
	421	out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
	422
	423	out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
	424	out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
	425	out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
	426	out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
	427
	428	/*--------------------------------------------------------------------------+
	429	* Set up Configuration registers
	430	--------------------------------------------------------------------------/
	431
	432	/* Program the board's subsystem id/vendor id */
	433	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
6d0f6bcf JCPV	434	CONFIG_SYS_PCI_SUBSYS_VENDORID);
6d0f6bcf JCPV	435	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
c157d8e2 SR	436
	437	/* Configure command register as bus master */
	438	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
	439
	440	/* 240nS PCI clock */
	441	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
	442
	443	/* No error reporting */
	444	pci_write_config_word(0, PCI_ERREN, 0);
	445
	446	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
	447
	448	}
6d0f6bcf	449	#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
c157d8e2 SR	450
	451	/*************************************************************************
	452	* pci_master_init
	453	*
	454	************************************************************************/
6d0f6bcf	455	#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
c157d8e2 SR	456	void pci_master_init(struct pci_controller *hose)
	457	{
	458	unsigned short temp_short;
	459
	460	/*--------------------------------------------------------------------------+
	461	\| Write the PowerPC440 EP PCI Configuration regs.
	462	\| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	463	\| Enable PowerPC440 EP to act as a PCI memory target (PTM).
	464	+--------------------------------------------------------------------------*/
	465	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	466	pci_write_config_word(0, PCI_COMMAND,
	467	temp_short \| PCI_COMMAND_MASTER \|
	468	PCI_COMMAND_MEMORY);
	469	}
6d0f6bcf	470	#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
c157d8e2 SR	471
	472	/*************************************************************************
	473	* is_pci_host
	474	*
	475	* This routine is called to determine if a pci scan should be
	476	* performed. With various hardware environments (especially cPCI and
	477	* PPMC) it's insufficient to depend on the state of the arbiter enable
	478	* bit in the strap register, or generic host/adapter assumptions.
	479	*
	480	* Rather than hard-code a bad assumption in the general 440 code, the
	481	* 440 pci code requires the board to decide at runtime.
	482	*
	483	* Return 0 for adapter mode, non-zero for host (monarch) mode.
	484	*
	485	*
	486	************************************************************************/
	487	#if defined(CONFIG_PCI)
	488	int is_pci_host(struct pci_controller *hose)
	489	{
	490	/* Bamboo is always configured as host. */
	491	return (1);
	492	}
	493	#endif /* defined(CONFIG_PCI) */
	494
	495	/*************************************************************************
	496	* hw_watchdog_reset
	497	*
	498	* This routine is called to reset (keep alive) the watchdog timer
	499	*
	500	************************************************************************/
	501	#if defined(CONFIG_HW_WATCHDOG)
	502	void hw_watchdog_reset(void)
	503	{
	504
	505	}
	506	#endif
f3443867 SR	507
	508	void board_reset(void)
	509	{
	510	/* give reset to BCSR */
6d0f6bcf	511	(unsigned char )(CONFIG_SYS_BCSR_BASE \| 0x06) = 0x09;
f3443867	512	}