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Commit | Line | Data |
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8e429b3e SP |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
8e429b3e SP |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
8e429b3e SP |
7 | */ |
8 | ||
9 | #include <common.h> | |
1ace4022 | 10 | #include <linux/sizes.h> |
8e429b3e | 11 | #include <asm/arch/at91sam9263.h> |
8e429b3e | 12 | #include <asm/arch/at91sam9_smc.h> |
1332a2a0 | 13 | #include <asm/arch/at91_common.h> |
8e429b3e | 14 | #include <asm/arch/at91_pmc.h> |
1b34f00c JS |
15 | #include <asm/arch/at91_matrix.h> |
16 | #include <asm/arch/at91_pio.h> | |
dc39ae95 | 17 | #include <asm/arch/clk.h> |
cd46b0f2 XH |
18 | #include <asm/io.h> |
19 | #include <asm/arch/gpio.h> | |
3ae071e4 | 20 | #include <asm/arch/hardware.h> |
56a2479c SP |
21 | #include <lcd.h> |
22 | #include <atmel_lcdc.h> | |
8e429b3e SP |
23 | #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) |
24 | #include <net.h> | |
25 | #endif | |
3ae071e4 | 26 | #include <netdev.h> |
81724e09 | 27 | #include <atmel_mci.h> |
8e429b3e SP |
28 | |
29 | DECLARE_GLOBAL_DATA_PTR; | |
30 | ||
31 | /* ------------------------------------------------------------------------- */ | |
32 | /* | |
33 | * Miscelaneous platform dependent initialisations | |
34 | */ | |
35 | ||
8e429b3e SP |
36 | #ifdef CONFIG_CMD_NAND |
37 | static void at91sam9263ek_nand_hw_init(void) | |
38 | { | |
39 | unsigned long csa; | |
cd46b0f2 XH |
40 | at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; |
41 | at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; | |
42 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; | |
1b34f00c JS |
43 | |
44 | /* Enable CS3 */ | |
45 | csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; | |
46 | writel(csa, &matrix->csa[0]); | |
8e429b3e SP |
47 | |
48 | /* Enable CS3 */ | |
8e429b3e SP |
49 | |
50 | /* Configure SMC CS3 for NAND/SmartMedia */ | |
1b34f00c JS |
51 | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | |
52 | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), | |
53 | &smc->cs[3].setup); | |
54 | ||
55 | writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | | |
56 | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), | |
57 | &smc->cs[3].pulse); | |
58 | ||
59 | writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), | |
60 | &smc->cs[3].cycle); | |
61 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | | |
62 | AT91_SMC_MODE_EXNW_DISABLE | | |
6d0f6bcf | 63 | #ifdef CONFIG_SYS_NAND_DBW_16 |
1b34f00c | 64 | AT91_SMC_MODE_DBW_16 | |
6d0f6bcf | 65 | #else /* CONFIG_SYS_NAND_DBW_8 */ |
1b34f00c | 66 | AT91_SMC_MODE_DBW_8 | |
8e429b3e | 67 | #endif |
1b34f00c JS |
68 | AT91_SMC_MODE_TDF_CYCLE(2), |
69 | &smc->cs[3].mode); | |
8e429b3e | 70 | |
cd46b0f2 | 71 | writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, |
1b34f00c | 72 | &pmc->pcer); |
8e429b3e SP |
73 | |
74 | /* Configure RDY/BSY */ | |
cd46b0f2 | 75 | at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); |
8e429b3e SP |
76 | |
77 | /* Enable NandFlash */ | |
cd46b0f2 | 78 | at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); |
8e429b3e SP |
79 | } |
80 | #endif | |
81 | ||
8e429b3e SP |
82 | #ifdef CONFIG_MACB |
83 | static void at91sam9263ek_macb_hw_init(void) | |
84 | { | |
cd46b0f2 XH |
85 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
86 | at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; | |
4535a24c | 87 | |
8e429b3e | 88 | /* Enable clock */ |
cd46b0f2 | 89 | writel(1 << ATMEL_ID_EMAC, &pmc->pcer); |
8e429b3e SP |
90 | |
91 | /* | |
92 | * Disable pull-up on: | |
93 | * RXDV (PC25) => PHY normal mode (not Test mode) | |
94 | * ERX0 (PE25) => PHY ADDR0 | |
95 | * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 | |
96 | * | |
97 | * PHY has internal pull-down | |
98 | */ | |
1b34f00c JS |
99 | writel(1 << 25, &pio->pioc.pudr); |
100 | writel((1 << 25) | (1 <<26), &pio->pioe.pudr); | |
0aafde1d | 101 | |
4535a24c | 102 | at91_phy_reset(); |
19bd6884 | 103 | |
8e429b3e | 104 | /* Re-enable pull-up */ |
1b34f00c JS |
105 | writel(1 << 25, &pio->pioc.puer); |
106 | writel((1 << 25) | (1 <<26), &pio->pioe.puer); | |
8e429b3e | 107 | |
e2c0476f | 108 | at91_macb_hw_init(); |
8e429b3e SP |
109 | } |
110 | #endif | |
111 | ||
56a2479c SP |
112 | #ifdef CONFIG_LCD |
113 | vidinfo_t panel_info = { | |
c346e466 JH |
114 | .vl_col = 240, |
115 | .vl_row = 320, | |
116 | .vl_clk = 4965000, | |
117 | .vl_sync = ATMEL_LCDC_INVLINE_INVERTED | | |
118 | ATMEL_LCDC_INVFRAME_INVERTED, | |
119 | .vl_bpix = 3, | |
120 | .vl_tft = 1, | |
121 | .vl_hsync_len = 5, | |
122 | .vl_left_margin = 1, | |
123 | .vl_right_margin = 33, | |
124 | .vl_vsync_len = 1, | |
125 | .vl_upper_margin = 1, | |
126 | .vl_lower_margin = 0, | |
127 | .mmio = ATMEL_BASE_LCDC, | |
56a2479c SP |
128 | }; |
129 | ||
130 | void lcd_enable(void) | |
131 | { | |
1b34f00c | 132 | at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */ |
56a2479c SP |
133 | } |
134 | ||
135 | void lcd_disable(void) | |
136 | { | |
1b34f00c | 137 | at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */ |
56a2479c SP |
138 | } |
139 | ||
140 | static void at91sam9263ek_lcd_hw_init(void) | |
141 | { | |
cd46b0f2 | 142 | at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; |
1b34f00c JS |
143 | |
144 | at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ | |
145 | at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ | |
146 | at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ | |
147 | at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ | |
148 | at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ | |
149 | at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ | |
150 | at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ | |
151 | at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ | |
152 | at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ | |
153 | at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ | |
154 | at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ | |
155 | at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ | |
156 | at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ | |
157 | at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ | |
158 | at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ | |
159 | at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ | |
160 | at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ | |
161 | at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ | |
162 | at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ | |
163 | at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ | |
164 | at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ | |
165 | at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ | |
166 | ||
cd46b0f2 XH |
167 | writel(1 << ATMEL_ID_LCDC, &pmc->pcer); |
168 | gd->fb_base = ATMEL_BASE_SRAM0; | |
56a2479c | 169 | } |
6b59e03e HS |
170 | |
171 | #ifdef CONFIG_LCD_INFO | |
172 | #include <nand.h> | |
173 | #include <version.h> | |
174 | ||
1b3b7c64 JCPV |
175 | #ifndef CONFIG_SYS_NO_FLASH |
176 | extern flash_info_t flash_info[]; | |
177 | #endif | |
178 | ||
6b59e03e HS |
179 | void lcd_show_board_info(void) |
180 | { | |
181 | ulong dram_size, nand_size; | |
1b3b7c64 JCPV |
182 | #ifndef CONFIG_SYS_NO_FLASH |
183 | ulong flash_size; | |
184 | #endif | |
6b59e03e HS |
185 | int i; |
186 | char temp[32]; | |
187 | ||
188 | lcd_printf ("%s\n", U_BOOT_VERSION); | |
189 | lcd_printf ("(C) 2008 ATMEL Corp\n"); | |
190 | lcd_printf ("at91support@atmel.com\n"); | |
191 | lcd_printf ("%s CPU at %s MHz\n", | |
cd46b0f2 | 192 | ATMEL_CPU_NAME, |
dc39ae95 | 193 | strmhz(temp, get_cpu_clk_rate())); |
6b59e03e HS |
194 | |
195 | dram_size = 0; | |
196 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) | |
197 | dram_size += gd->bd->bi_dram[i].size; | |
198 | nand_size = 0; | |
199 | for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) | |
200 | nand_size += nand_info[i].size; | |
1b3b7c64 JCPV |
201 | #ifndef CONFIG_SYS_NO_FLASH |
202 | flash_size = 0; | |
203 | for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) | |
204 | flash_size += flash_info[i].size; | |
205 | #endif | |
206 | lcd_printf (" %ld MB SDRAM, %ld MB NAND", | |
6b59e03e HS |
207 | dram_size >> 20, |
208 | nand_size >> 20 ); | |
1b3b7c64 JCPV |
209 | #ifndef CONFIG_SYS_NO_FLASH |
210 | lcd_printf (",\n %ld MB NOR", | |
211 | flash_size >> 20); | |
212 | #endif | |
213 | lcd_puts ("\n"); | |
6b59e03e HS |
214 | } |
215 | #endif /* CONFIG_LCD_INFO */ | |
56a2479c SP |
216 | #endif |
217 | ||
81724e09 AH |
218 | #ifdef CONFIG_GENERIC_ATMEL_MCI |
219 | int board_mmc_init(bd_t *bd) | |
220 | { | |
221 | at91_mci_hw_init(); | |
222 | ||
223 | return atmel_mci_init((void *)ATMEL_BASE_MCI1); | |
224 | } | |
225 | #endif | |
226 | ||
cd46b0f2 XH |
227 | int board_early_init_f(void) |
228 | { | |
229 | struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; | |
230 | ||
231 | /* Enable clocks for all PIOs */ | |
232 | writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | | |
233 | (1 << ATMEL_ID_PIOCDE), | |
234 | &pmc->pcer); | |
235 | ||
2feb7366 | 236 | at91_seriald_hw_init(); |
cd46b0f2 XH |
237 | return 0; |
238 | } | |
239 | ||
8e429b3e SP |
240 | int board_init(void) |
241 | { | |
8e429b3e SP |
242 | /* arch number of AT91SAM9263EK-Board */ |
243 | gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; | |
244 | /* adress of boot parameters */ | |
cd46b0f2 | 245 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
8e429b3e | 246 | |
8e429b3e SP |
247 | #ifdef CONFIG_CMD_NAND |
248 | at91sam9263ek_nand_hw_init(); | |
249 | #endif | |
250 | #ifdef CONFIG_HAS_DATAFLASH | |
1b34f00c | 251 | at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */ |
7ebafb7e | 252 | at91_spi0_hw_init(1 << 0); |
8e429b3e SP |
253 | #endif |
254 | #ifdef CONFIG_MACB | |
255 | at91sam9263ek_macb_hw_init(); | |
256 | #endif | |
257 | #ifdef CONFIG_USB_OHCI_NEW | |
f3f91f88 | 258 | at91_uhp_hw_init(); |
56a2479c SP |
259 | #endif |
260 | #ifdef CONFIG_LCD | |
261 | at91sam9263ek_lcd_hw_init(); | |
8e429b3e SP |
262 | #endif |
263 | return 0; | |
264 | } | |
265 | ||
266 | int dram_init(void) | |
267 | { | |
cd46b0f2 XH |
268 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, |
269 | CONFIG_SYS_SDRAM_SIZE); | |
270 | ||
8e429b3e SP |
271 | return 0; |
272 | } | |
273 | ||
274 | #ifdef CONFIG_RESET_PHY_R | |
275 | void reset_phy(void) | |
276 | { | |
8e429b3e SP |
277 | } |
278 | #endif | |
3ae071e4 BW |
279 | |
280 | int board_eth_init(bd_t *bis) | |
281 | { | |
282 | int rc = 0; | |
283 | #ifdef CONFIG_MACB | |
cd46b0f2 | 284 | rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00); |
3ae071e4 BW |
285 | #endif |
286 | return rc; | |
287 | } |