[people/ms/u-boot.git] / board / atmel / at91sam9x5ek / at91sam9x5ek.c

/*
 * Copyright (C) 2012 Atmel Corporation
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91sam9x5_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <debug_uart.h>
#include <asm/mach-types.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */
#ifdef CONFIG_CMD_NAND
static void at91sam9x5ek_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Enable CS3 */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
	/* NAND flash on D16 */
	csa |= AT91_MATRIX_NFD0_ON_D16;

	/* Configure IO drive */
	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;

	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
		&smc->cs[3].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		AT91_SMC_MODE_DBW_8 |
#endif
		AT91_SMC_MODE_TDF_CYCLE(1),
		&smc->cs[3].mode);

	at91_periph_clk_enable(ATMEL_ID_PIOCD);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);

	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);	/* NAND OE */
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);	/* NAND WE */
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);	/* NAND ALE */
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);	/* NAND CLE */
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
}
#endif

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_DM_VIDEO
	at91_video_show_board_info();
#endif
	return 0;
}
#endif

#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
	at91_seriald_hw_init();
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
#ifdef CONFIG_DEBUG_UART
	debug_uart_init();
#endif
	return 0;
}
#endif

int board_init(void)
{
	/* arch number of AT91SAM9X5EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_CMD_NAND
	at91sam9x5ek_nand_hw_init();
#endif

#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
	at91_uhp_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
					CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

#if defined(CONFIG_SPL_BUILD)
#include <spl.h>
#include <nand.h>

void at91_spl_board_init(void)
{
#ifdef CONFIG_SD_BOOT
	at91_mci_hw_init();
#elif CONFIG_NAND_BOOT
	at91sam9x5ek_nand_hw_init();
#endif
}

#include <asm/arch/atmel_mpddrc.h>
static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);

	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
		    ATMEL_MPDDRC_CR_NR_ROW_13 |
		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
		    ATMEL_MPDDRC_CR_NB_8BANKS |
		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);

	ddr2->rtr = 0x411;

	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);

	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);

	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
}

void mem_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct atmel_mpddrc_config ddr2;
	unsigned long csa;

	ddr2_conf(&ddr2);

	/* enable DDR2 clock */
	writel(AT91_PMC_DDR, &pmc->scer);

	/* Chip select 1 is for DDR2/SDRAM */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
	csa |= AT91_MATRIX_EBI_DBPD_OFF;
	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
	writel(csa, &matrix->ebicsa);

	/* DDRAM2 Controller initialize */
	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
}
#endif
Commit	Line	Data
f7fa2f37 BS	1	/*
	2	* Copyright (C) 2012 Atmel Corporation
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
f7fa2f37 BS	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/at91sam9x5_matrix.h>
	10	#include <asm/arch/at91sam9_smc.h>
	11	#include <asm/arch/at91_common.h>
f7fa2f37	12	#include <asm/arch/at91_rstc.h>
f7fa2f37	13	#include <asm/arch/clk.h>
70341e2e	14	#include <asm/arch/gpio.h>
9daf89cb	15	#include <debug_uart.h>
c62db35d	16	#include <asm/mach-types.h>
f7fa2f37 BS	17
	18	DECLARE_GLOBAL_DATA_PTR;
	19
	20	/* ------------------------------------------------------------------------- */
	21	/*
	22	* Miscelaneous platform dependent initialisations
	23	*/
	24	#ifdef CONFIG_CMD_NAND
	25	static void at91sam9x5ek_nand_hw_init(void)
	26	{
	27	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	28	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
f7fa2f37 BS	29	unsigned long csa;
	30
	31	/* Enable CS3 */
	32	csa = readl(&matrix->ebicsa);
	33	csa \|= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
4ed9c886 BS	34	/* NAND flash on D16 */
4ed9c886 BS	35	csa \|= AT91_MATRIX_NFD0_ON_D16;
1c5794a1 WJ	36
	37	/* Configure IO drive */
	38	csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
	39
f7fa2f37 BS	40	writel(csa, &matrix->ebicsa);
	41
	42	/* Configure SMC CS3 for NAND/SmartMedia */
2ab4c746 WJ	43	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
2ab4c746 WJ	44	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
f7fa2f37	45	&smc->cs[3].setup);
2ab4c746 WJ	46	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(5) \|
2ab4c746 WJ	47	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(6),
f7fa2f37	48	&smc->cs[3].pulse);
2ab4c746	49	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(6),
f7fa2f37 BS	50	&smc->cs[3].cycle);
	51	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	52	AT91_SMC_MODE_EXNW_DISABLE \|
	53	#ifdef CONFIG_SYS_NAND_DBW_16
	54	AT91_SMC_MODE_DBW_16 \|
	55	#else /* CONFIG_SYS_NAND_DBW_8 */
	56	AT91_SMC_MODE_DBW_8 \|
	57	#endif
2ab4c746	58	AT91_SMC_MODE_TDF_CYCLE(1),
f7fa2f37 BS	59	&smc->cs[3].mode);
f7fa2f37 BS	60
70341e2e	61	at91_periph_clk_enable(ATMEL_ID_PIOCD);
f7fa2f37 BS	62
	63	/* Configure RDY/BSY */
	64	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
	65	/* Enable NandFlash */
	66	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
	67
2dc63f73 WY	68	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
	69	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
	70	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
	71	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
	72	at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
	73	at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
	74	at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
	75	at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
	76	at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
	77	at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
	78	at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
	79	at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
f7fa2f37 BS	80	}
	81	#endif
	82
40f34294 WY	83	#ifdef CONFIG_BOARD_LATE_INIT
40f34294 WY	84	int board_late_init(void)
f7fa2f37	85	{
40f34294 WY	86	#ifdef CONFIG_DM_VIDEO
	87	at91_video_show_board_info();
	88	#endif
	89	return 0;
f7fa2f37	90	}
40f34294	91	#endif
f7fa2f37	92
9daf89cb WY	93	#ifdef CONFIG_DEBUG_UART_BOARD_INIT
9daf89cb WY	94	void board_debug_uart_init(void)
f7fa2f37 BS	95	{
f7fa2f37 BS	96	at91_seriald_hw_init();
9daf89cb WY	97	}
	98	#endif
	99
	100	#ifdef CONFIG_BOARD_EARLY_INIT_F
	101	int board_early_init_f(void)
	102	{
	103	#ifdef CONFIG_DEBUG_UART
	104	debug_uart_init();
	105	#endif
f7fa2f37 BS	106	return 0;
f7fa2f37 BS	107	}
9daf89cb	108	#endif
f7fa2f37 BS	109
	110	int board_init(void)
	111	{
94ba26f2 TR	112	/* arch number of AT91SAM9X5EK-Board */
	113	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
	114
f7fa2f37 BS	115	/* adress of boot parameters */
	116	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
	117
	118	#ifdef CONFIG_CMD_NAND
	119	at91sam9x5ek_nand_hw_init();
	120	#endif
	121
8850c5d5	122	#if defined(CONFIG_USB_OHCI_NEW) \|\| defined(CONFIG_USB_EHCI_HCD)
bcfc8976	123	at91_uhp_hw_init();
f7fa2f37 BS	124	#endif
	125	return 0;
	126	}
	127
	128	int dram_init(void)
	129	{
	130	gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
	131	CONFIG_SYS_SDRAM_SIZE);
	132	return 0;
	133	}
d85e8914 BS	134
	135	#if defined(CONFIG_SPL_BUILD)
	136	#include <spl.h>
	137	#include <nand.h>
	138
	139	void at91_spl_board_init(void)
	140	{
5541543f	141	#ifdef CONFIG_SD_BOOT
d85e8914	142	at91_mci_hw_init();
5541543f	143	#elif CONFIG_NAND_BOOT
d85e8914	144	at91sam9x5ek_nand_hw_init();
d85e8914 BS	145	#endif
	146	}
	147
	148	#include <asm/arch/atmel_mpddrc.h>
7e8702a0	149	static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
d85e8914 BS	150	{
	151	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS \| ATMEL_MPDDRC_MD_DDR2_SDRAM);
	152
	153	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	154	ATMEL_MPDDRC_CR_NR_ROW_13 \|
	155	ATMEL_MPDDRC_CR_CAS_DDR_CAS3 \|
	156	ATMEL_MPDDRC_CR_NB_8BANKS \|
	157	ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
	158
	159	ddr2->rtr = 0x411;
	160
	161	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET \|
	162	2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|
	163	2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET \|
	164	8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET \|
	165	2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET \|
	166	2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET \|
	167	2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET \|
	168	2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
	169
	170	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET \|
	171	200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET \|
	172	19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET \|
	173	18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
	174
	175	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET \|
	176	2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET \|
	177	3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET \|
	178	7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET \|
	179	2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
	180	}
	181
	182	void mem_init(void)
	183	{
	184	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	185	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
7e8702a0	186	struct atmel_mpddrc_config ddr2;
d85e8914 BS	187	unsigned long csa;
	188
	189	ddr2_conf(&ddr2);
	190
	191	/* enable DDR2 clock */
c982f6b9	192	writel(AT91_PMC_DDR, &pmc->scer);
d85e8914 BS	193
	194	/* Chip select 1 is for DDR2/SDRAM */
	195	csa = readl(&matrix->ebicsa);
	196	csa \|= AT91_MATRIX_EBI_CS1A_SDRAMC;
	197	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
	198	csa \|= AT91_MATRIX_EBI_DBPD_OFF;
	199	csa \|= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
	200	writel(csa, &matrix->ebicsa);
	201
	202	/* DDRAM2 Controller initialize */
0c01c3e8	203	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
d85e8914 BS	204	}
d85e8914 BS	205	#endif