[people/ms/u-boot.git] / board / atmel / sama5d3xek / sama5d3xek.c

/*
 * Copyright (C) 2012 - 2013 Atmel Corporation
 * Bo Shen <voice.shen@atmel.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#include <net.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_NAND_ATMEL
void sama5d3xek_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	at91_periph_clk_enable(ATMEL_ID_SMC);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
	       AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
	       AT91_SMC_MODE_DBW_8 |
#endif
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);
}
#endif

#ifdef CONFIG_CMD_USB
static void sama5d3xek_usb_hw_init(void)
{
	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
}
#endif

#ifdef CONFIG_GENERIC_ATMEL_MCI
static void sama5d3xek_mci_hw_init(void)
{
	at91_mci_hw_init();

	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col = 800,
	.vl_row = 480,
	.vl_clk = 24000000,
	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
	.vl_bpix = LCD_BPP,
	.vl_tft = 1,
	.vl_hsync_len = 128,
	.vl_left_margin = 64,
	.vl_right_margin = 64,
	.vl_vsync_len = 2,
	.vl_upper_margin = 22,
	.vl_lower_margin = 21,
	.mmio = ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
}

void lcd_disable(void)
{
}

static void sama5d3xek_lcd_hw_init(void)
{
	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;

	/* The higher 8 bit of LCD is board related */
	at91_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
	at91_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
	at91_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
	at91_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
	at91_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
	at91_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
	at91_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
	at91_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */

	/* Configure lower 16 bit of LCD and enable clock */
	at91_lcd_hw_init();
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size;
	int i;
	char temp[32];

	lcd_printf("%s\n", U_BOOT_VERSION);
	lcd_printf("(C) 2013 ATMEL Corp\n");
	lcd_printf("at91@atmel.com\n");
	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
		   strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i].size;
#endif
	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
		   dram_size >> 20, nand_size >> 20);
}
#endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_LCD */

int board_early_init_f(void)
{
	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_NAND_ATMEL
	sama5d3xek_nand_hw_init();
#endif
#ifdef CONFIG_CMD_USB
	sama5d3xek_usb_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
	sama5d3xek_mci_hw_init();
#endif
#ifdef CONFIG_ATMEL_SPI
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
	if (has_emac())
		at91_macb_hw_init();
#endif
#ifdef CONFIG_LCD
	if (has_lcdc())
		sama5d3xek_lcd_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;

#ifdef CONFIG_MACB
	if (has_emac())
		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
#endif

	return rc;
}

#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bis)
{
	int rc = 0;

	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);

	return rc;
}
#endif

/* SPI chip select control */
#ifdef CONFIG_ATMEL_SPI
#include <spi.h>

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs < 4;
}

void spi_cs_activate(struct spi_slave *slave)
{
	switch (slave->cs) {
	case 0:
		at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
	case 1:
		at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
	case 2:
		at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
	case 3:
		at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
	default:
		break;
	}
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	switch (slave->cs) {
	case 0:
		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
	case 1:
		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
	case 2:
		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
	case 3:
		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
	default:
		break;
	}
}
#endif /* CONFIG_ATMEL_SPI */
Commit	Line	Data
3225f34e BS	1	/*
	2	* Copyright (C) 2012 - 2013 Atmel Corporation
	3	* Bo Shen <voice.shen@atmel.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mmc.h>
	26	#include <asm/io.h>
	27	#include <asm/arch/sama5d3_smc.h>
	28	#include <asm/arch/at91_common.h>
	29	#include <asm/arch/at91_pmc.h>
	30	#include <asm/arch/at91_rstc.h>
	31	#include <asm/arch/gpio.h>
	32	#include <asm/arch/clk.h>
	33	#include <lcd.h>
	34	#include <atmel_lcdc.h>
	35	#include <atmel_mci.h>
	36	#include <net.h>
	37	#include <netdev.h>
	38
	39	DECLARE_GLOBAL_DATA_PTR;
	40
	41	/* ------------------------------------------------------------------------- */
	42	/*
	43	* Miscelaneous platform dependent initialisations
	44	*/
	45
	46	#ifdef CONFIG_NAND_ATMEL
	47	void sama5d3xek_nand_hw_init(void)
	48	{
	49	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	50
	51	at91_periph_clk_enable(ATMEL_ID_SMC);
	52
	53	/* Configure SMC CS3 for NAND/SmartMedia */
	54	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(1) \|
	55	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(1),
	56	&smc->cs[3].setup);
	57	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(5) \|
	58	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(5),
	59	&smc->cs[3].pulse);
	60	writel(AT91_SMC_CYCLE_NWE(8) \| AT91_SMC_CYCLE_NRD(8),
	61	&smc->cs[3].cycle);
	62	writel(AT91_SMC_TIMINGS_TCLR(3) \| AT91_SMC_TIMINGS_TADL(10) \|
	63	AT91_SMC_TIMINGS_TAR(3) \| AT91_SMC_TIMINGS_TRR(4) \|
	64	AT91_SMC_TIMINGS_TWB(5) \| AT91_SMC_TIMINGS_RBNSEL(3)\|
65	AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
66	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
67	AT91_SMC_MODE_EXNW_DISABLE \|
68	#ifdef CONFIG_SYS_NAND_DBW_16
69	AT91_SMC_MODE_DBW_16 \|
70	#else /* CONFIG_SYS_NAND_DBW_8 */
71	AT91_SMC_MODE_DBW_8 \|
72	#endif
73	AT91_SMC_MODE_TDF_CYCLE(3),
74	&smc->cs[3].mode);
75	}
76	#endif
77
78	#ifdef CONFIG_CMD_USB
79	static void sama5d3xek_usb_hw_init(void)
80	{
81	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
82	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
83	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
84	}
85	#endif
86
87	#ifdef CONFIG_GENERIC_ATMEL_MCI
88	static void sama5d3xek_mci_hw_init(void)
89	{
90	at91_mci_hw_init();
91
92	at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
93	}
94	#endif
95
96	#ifdef CONFIG_LCD
97	vidinfo_t panel_info = {
98	.vl_col = 800,
99	.vl_row = 480,
100	.vl_clk = 24000000,
101	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL \| ATMEL_LCDC_INVFRAME_NORMAL,
102	.vl_bpix = LCD_BPP,
103	.vl_tft = 1,
104	.vl_hsync_len = 128,
105	.vl_left_margin = 64,
106	.vl_right_margin = 64,
107	.vl_vsync_len = 2,
108	.vl_upper_margin = 22,
109	.vl_lower_margin = 21,
110	.mmio = ATMEL_BASE_LCDC,
111	};
112
113	void lcd_enable(void)
114	{
115	}
116
117	void lcd_disable(void)
118	{
119	}
120
121	static void sama5d3xek_lcd_hw_init(void)
122	{
123	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
124
125	/* The higher 8 bit of LCD is board related */
126	at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
127	at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
128	at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
129	at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
130	at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
131	at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
132	at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
133	at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
134
135	/* Configure lower 16 bit of LCD and enable clock */
136	at91_lcd_hw_init();
137	}
138
139	#ifdef CONFIG_LCD_INFO
140	#include <nand.h>
141	#include <version.h>
142
143	void lcd_show_board_info(void)
144	{
145	ulong dram_size, nand_size;
146	int i;
147	char temp[32];
148
149	lcd_printf("%s\n", U_BOOT_VERSION);
150	lcd_printf("(C) 2013 ATMEL Corp\n");
151	lcd_printf("at91@atmel.com\n");
152	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
153	strmhz(temp, get_cpu_clk_rate()));
154
155	dram_size = 0;
156	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
157	dram_size += gd->bd->bi_dram[i].size;
158
159	nand_size = 0;
160	#ifdef CONFIG_NAND_ATMEL
161	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
162	nand_size += nand_info[i].size;
163	#endif
164	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
165	dram_size >> 20, nand_size >> 20);
166	}
167	#endif /* CONFIG_LCD_INFO */
168	#endif /* CONFIG_LCD */
169
170	int board_early_init_f(void)
171	{
172	at91_seriald_hw_init();
173
174	return 0;
175	}
176
177	int board_init(void)
178	{
179	/* adress of boot parameters */
180	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
181
182	#ifdef CONFIG_NAND_ATMEL
183	sama5d3xek_nand_hw_init();
184	#endif
185	#ifdef CONFIG_CMD_USB
186	sama5d3xek_usb_hw_init();
187	#endif
188	#ifdef CONFIG_GENERIC_ATMEL_MCI
189	sama5d3xek_mci_hw_init();
190	#endif
191	#ifdef CONFIG_ATMEL_SPI
192	at91_spi0_hw_init(1 << 0);
193	#endif
194	#ifdef CONFIG_MACB
195	if (has_emac())
196	at91_macb_hw_init();
197	#endif
198	#ifdef CONFIG_LCD
199	if (has_lcdc())
200	sama5d3xek_lcd_hw_init();
201	#endif
202	return 0;
203	}
204
205	int dram_init(void)
206	{
207	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
208	CONFIG_SYS_SDRAM_SIZE);
209	return 0;
210	}
211
212	int board_eth_init(bd_t *bis)
213	{
214	int rc = 0;
215
216	#ifdef CONFIG_MACB
217	if (has_emac())
218	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
219	#endif
220
221	return rc;
222	}
223
224	#ifdef CONFIG_GENERIC_ATMEL_MCI
225	int board_mmc_init(bd_t *bis)
226	{
227	int rc = 0;
228
229	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
230
231	return rc;
232	}
233	#endif
234
235	/* SPI chip select control */
236	#ifdef CONFIG_ATMEL_SPI
237	#include <spi.h>
238
239	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
240	{
241	return bus == 0 && cs < 4;
242	}
243
244	void spi_cs_activate(struct spi_slave *slave)
245	{
246	switch (slave->cs) {
247	case 0:
248	at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
249	case 1:
250	at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
251	case 2:
252	at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
253	case 3:
254	at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
255	default:
256	break;
257	}
258	}
259
260	void spi_cs_deactivate(struct spi_slave *slave)
261	{
262	switch (slave->cs) {
263	case 0:
264	at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
265	case 1:
266	at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
267	case 2:
268	at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
269	case 3:
270	at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
271	default:
272	break;
273	}
274	}
275	#endif /* CONFIG_ATMEL_SPI */