[people/ms/u-boot.git] / board / atmel / sama5d3xek / sama5d3xek.c

/*
 * Copyright (C) 2012 - 2013 Atmel Corporation
 * Bo Shen <voice.shen@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <asm/io.h>
#include <asm/arch/sama5d3_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/clk.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#include <atmel_mci.h>
#include <net.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_NAND_ATMEL
void sama5d3xek_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	at91_periph_clk_enable(ATMEL_ID_SMC);

	/* Configure SMC CS3 for NAND/SmartMedia */
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
	       &smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
	       &smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
	       &smc->cs[3].cycle);
	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
	       AT91_SMC_TIMINGS_TAR(3)  | AT91_SMC_TIMINGS_TRR(4)   |
	       AT91_SMC_TIMINGS_TWB(5)  | AT91_SMC_TIMINGS_RBNSEL(3)|
	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
	       AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
	       AT91_SMC_MODE_DBW_8 |
#endif
	       AT91_SMC_MODE_TDF_CYCLE(3),
	       &smc->cs[3].mode);
}
#endif

#ifdef CONFIG_CMD_USB
static void sama5d3xek_usb_hw_init(void)
{
	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
}
#endif

#ifdef CONFIG_GENERIC_ATMEL_MCI
static void sama5d3xek_mci_hw_init(void)
{
	at91_mci_hw_init();

	at91_set_pio_output(AT91_PIO_PORTB, 10, 0);	/* MCI0 Power */
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col = 800,
	.vl_row = 480,
	.vl_clk = 24000000,
	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
	.vl_bpix = LCD_BPP,
	.vl_tft = 1,
	.vl_hsync_len = 128,
	.vl_left_margin = 64,
	.vl_right_margin = 64,
	.vl_vsync_len = 2,
	.vl_upper_margin = 22,
	.vl_lower_margin = 21,
	.mmio = ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
}

void lcd_disable(void)
{
}

static void sama5d3xek_lcd_hw_init(void)
{
	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;

	/* The higher 8 bit of LCD is board related */
	at91_set_c_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD16 */
	at91_set_c_periph(AT91_PIO_PORTC, 13, 0);	/* LCDD17 */
	at91_set_c_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD18 */
	at91_set_c_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD19 */
	at91_set_c_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD20 */
	at91_set_c_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD21 */
	at91_set_c_periph(AT91_PIO_PORTE, 27, 0);	/* LCDD22 */
	at91_set_c_periph(AT91_PIO_PORTE, 28, 0);	/* LCDD23 */

	/* Configure lower 16 bit of LCD and enable clock */
	at91_lcd_hw_init();
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size;
	int i;
	char temp[32];

	lcd_printf("%s\n", U_BOOT_VERSION);
	lcd_printf("(C) 2013 ATMEL Corp\n");
	lcd_printf("at91@atmel.com\n");
	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
		   strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;

	nand_size = 0;
#ifdef CONFIG_NAND_ATMEL
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i].size;
#endif
	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
		   dram_size >> 20, nand_size >> 20);
}
#endif /* CONFIG_LCD_INFO */
#endif /* CONFIG_LCD */

int board_early_init_f(void)
{
	at91_seriald_hw_init();

	return 0;
}

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_NAND_ATMEL
	sama5d3xek_nand_hw_init();
#endif
#ifdef CONFIG_CMD_USB
	sama5d3xek_usb_hw_init();
#endif
#ifdef CONFIG_GENERIC_ATMEL_MCI
	sama5d3xek_mci_hw_init();
#endif
#ifdef CONFIG_ATMEL_SPI
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_MACB
	if (has_emac())
		at91_macb_hw_init();
#endif
#ifdef CONFIG_LCD
	if (has_lcdc())
		sama5d3xek_lcd_hw_init();
#endif
	return 0;
}

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
				    CONFIG_SYS_SDRAM_SIZE);
	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;

#ifdef CONFIG_MACB
	if (has_emac())
		rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
#endif

	return rc;
}

#ifdef CONFIG_GENERIC_ATMEL_MCI
int board_mmc_init(bd_t *bis)
{
	int rc = 0;

	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);

	return rc;
}
#endif

/* SPI chip select control */
#ifdef CONFIG_ATMEL_SPI
#include <spi.h>

int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
	return bus == 0 && cs < 4;
}

void spi_cs_activate(struct spi_slave *slave)
{
	switch (slave->cs) {
	case 0:
		at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
	case 1:
		at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
	case 2:
		at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
	case 3:
		at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
	default:
		break;
	}
}

void spi_cs_deactivate(struct spi_slave *slave)
{
	switch (slave->cs) {
	case 0:
		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
	case 1:
		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
	case 2:
		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
	case 3:
		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
	default:
		break;
	}
}
#endif /* CONFIG_ATMEL_SPI */
Commit	Line	Data
3225f34e BS	1	/*
	2	* Copyright (C) 2012 - 2013 Atmel Corporation
	3	* Bo Shen <voice.shen@atmel.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
3225f34e BS	6	*/
	7
	8	#include <common.h>
	9	#include <mmc.h>
	10	#include <asm/io.h>
	11	#include <asm/arch/sama5d3_smc.h>
	12	#include <asm/arch/at91_common.h>
	13	#include <asm/arch/at91_pmc.h>
	14	#include <asm/arch/at91_rstc.h>
	15	#include <asm/arch/gpio.h>
	16	#include <asm/arch/clk.h>
	17	#include <lcd.h>
	18	#include <atmel_lcdc.h>
	19	#include <atmel_mci.h>
	20	#include <net.h>
	21	#include <netdev.h>
	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	/* ------------------------------------------------------------------------- */
	26	/*
	27	* Miscelaneous platform dependent initialisations
	28	*/
	29
	30	#ifdef CONFIG_NAND_ATMEL
	31	void sama5d3xek_nand_hw_init(void)
	32	{
	33	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	34
	35	at91_periph_clk_enable(ATMEL_ID_SMC);
	36
	37	/* Configure SMC CS3 for NAND/SmartMedia */
	38	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(1) \|
	39	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(1),
	40	&smc->cs[3].setup);
	41	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(5) \|
	42	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(5),
	43	&smc->cs[3].pulse);
	44	writel(AT91_SMC_CYCLE_NWE(8) \| AT91_SMC_CYCLE_NRD(8),
	45	&smc->cs[3].cycle);
	46	writel(AT91_SMC_TIMINGS_TCLR(3) \| AT91_SMC_TIMINGS_TADL(10) \|
	47	AT91_SMC_TIMINGS_TAR(3) \| AT91_SMC_TIMINGS_TRR(4) \|
	48	AT91_SMC_TIMINGS_TWB(5) \| AT91_SMC_TIMINGS_RBNSEL(3)\|
	49	AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
	50	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	51	AT91_SMC_MODE_EXNW_DISABLE \|
	52	#ifdef CONFIG_SYS_NAND_DBW_16
	53	AT91_SMC_MODE_DBW_16 \|
	54	#else /* CONFIG_SYS_NAND_DBW_8 */
	55	AT91_SMC_MODE_DBW_8 \|
	56	#endif
	57	AT91_SMC_MODE_TDF_CYCLE(3),
	58	&smc->cs[3].mode);
	59	}
	60	#endif
	61
	62	#ifdef CONFIG_CMD_USB
	63	static void sama5d3xek_usb_hw_init(void)
	64	{
	65	at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
	66	at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
	67	at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
	68	}
	69	#endif
70
71	#ifdef CONFIG_GENERIC_ATMEL_MCI
72	static void sama5d3xek_mci_hw_init(void)
73	{
74	at91_mci_hw_init();
75
76	at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
77	}
78	#endif
79
80	#ifdef CONFIG_LCD
81	vidinfo_t panel_info = {
82	.vl_col = 800,
83	.vl_row = 480,
84	.vl_clk = 24000000,
85	.vl_sync = ATMEL_LCDC_INVLINE_NORMAL \| ATMEL_LCDC_INVFRAME_NORMAL,
86	.vl_bpix = LCD_BPP,
87	.vl_tft = 1,
88	.vl_hsync_len = 128,
89	.vl_left_margin = 64,
90	.vl_right_margin = 64,
91	.vl_vsync_len = 2,
92	.vl_upper_margin = 22,
93	.vl_lower_margin = 21,
94	.mmio = ATMEL_BASE_LCDC,
95	};
96
97	void lcd_enable(void)
98	{
99	}
100
101	void lcd_disable(void)
102	{
103	}
104
105	static void sama5d3xek_lcd_hw_init(void)
106	{
107	gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
108
109	/* The higher 8 bit of LCD is board related */
110	at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
111	at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
112	at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
113	at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
114	at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
115	at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
116	at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
117	at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
118
119	/* Configure lower 16 bit of LCD and enable clock */
120	at91_lcd_hw_init();
121	}
122
123	#ifdef CONFIG_LCD_INFO
124	#include <nand.h>
125	#include <version.h>
126
127	void lcd_show_board_info(void)
128	{
129	ulong dram_size, nand_size;
130	int i;
131	char temp[32];
132
133	lcd_printf("%s\n", U_BOOT_VERSION);
134	lcd_printf("(C) 2013 ATMEL Corp\n");
135	lcd_printf("at91@atmel.com\n");
136	lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
137	strmhz(temp, get_cpu_clk_rate()));
138
139	dram_size = 0;
140	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
141	dram_size += gd->bd->bi_dram[i].size;
142
143	nand_size = 0;
144	#ifdef CONFIG_NAND_ATMEL
145	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
146	nand_size += nand_info[i].size;
147	#endif
148	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
149	dram_size >> 20, nand_size >> 20);
150	}
151	#endif /* CONFIG_LCD_INFO */
152	#endif /* CONFIG_LCD */
153
154	int board_early_init_f(void)
155	{
156	at91_seriald_hw_init();
157
158	return 0;
159	}
160
161	int board_init(void)
162	{
163	/* adress of boot parameters */
164	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
165
166	#ifdef CONFIG_NAND_ATMEL
167	sama5d3xek_nand_hw_init();
168	#endif
169	#ifdef CONFIG_CMD_USB
170	sama5d3xek_usb_hw_init();
171	#endif
172	#ifdef CONFIG_GENERIC_ATMEL_MCI
173	sama5d3xek_mci_hw_init();
174	#endif
175	#ifdef CONFIG_ATMEL_SPI
176	at91_spi0_hw_init(1 << 0);
177	#endif
178	#ifdef CONFIG_MACB
179	if (has_emac())
180	at91_macb_hw_init();
181	#endif
182	#ifdef CONFIG_LCD
183	if (has_lcdc())
184	sama5d3xek_lcd_hw_init();
185	#endif
186	return 0;
187	}
188
189	int dram_init(void)
190	{
191	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
192	CONFIG_SYS_SDRAM_SIZE);
193	return 0;
194	}
195
196	int board_eth_init(bd_t *bis)
197	{
198	int rc = 0;
199
200	#ifdef CONFIG_MACB
201	if (has_emac())
202	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
203	#endif
204
205	return rc;
206	}
207
208	#ifdef CONFIG_GENERIC_ATMEL_MCI
209	int board_mmc_init(bd_t *bis)
210	{
211	int rc = 0;
212
213	rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
214
215	return rc;
216	}
217	#endif
218
219	/* SPI chip select control */
220	#ifdef CONFIG_ATMEL_SPI
221	#include <spi.h>
222
223	int spi_cs_is_valid(unsigned int bus, unsigned int cs)
224	{
225	return bus == 0 && cs < 4;
226	}
227
228	void spi_cs_activate(struct spi_slave *slave)
229	{
230	switch (slave->cs) {
231	case 0:
232	at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
233	case 1:
234	at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
235	case 2:
236	at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
237	case 3:
238	at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
239	default:
240	break;
241	}
242	}
243
244	void spi_cs_deactivate(struct spi_slave *slave)
245	{
246	switch (slave->cs) {
247	case 0:
248	at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
249	case 1:
250	at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
251	case 2:
252	at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
253	case 3:
254	at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
255	default:
256	break;
257	}
258	}
259	#endif /* CONFIG_ATMEL_SPI */