]>
Commit | Line | Data |
---|---|---|
871ec6da JT |
1 | /* |
2 | * Copyright (C) 2016 Amarula Solutions B.V. | |
3 | * Copyright (C) 2016 Engicam S.r.l. | |
4 | * Author: Jagan Teki <jagan@amarulasolutions.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
d98fd132 | 10 | #include <mmc.h> |
871ec6da JT |
11 | |
12 | #include <asm/io.h> | |
13 | #include <asm/gpio.h> | |
14 | #include <linux/sizes.h> | |
15 | ||
16 | #include <asm/arch/clock.h> | |
17 | #include <asm/arch/crm_regs.h> | |
18 | #include <asm/arch/iomux.h> | |
19 | #include <asm/arch/mx6-pins.h> | |
20 | #include <asm/arch/sys_proto.h> | |
21 | #include <asm/imx-common/iomux-v3.h> | |
22 | ||
23 | DECLARE_GLOBAL_DATA_PTR; | |
24 | ||
871ec6da JT |
25 | int board_init(void) |
26 | { | |
27 | /* Address of boot parameters */ | |
28 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
29 | ||
30 | return 0; | |
31 | } | |
32 | ||
d98fd132 | 33 | #ifdef CONFIG_ENV_IS_IN_MMC |
2ea79a98 JT |
34 | int board_mmc_get_env_dev(int devno) |
35 | { | |
36 | /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */ | |
37 | return (devno == 3) ? 1 : 0; | |
38 | } | |
39 | ||
d98fd132 JT |
40 | static void mmc_late_init(void) |
41 | { | |
42 | char cmd[32]; | |
43 | char mmcblk[32]; | |
44 | u32 dev_no = mmc_get_env_dev(); | |
45 | ||
46 | setenv_ulong("mmcdev", dev_no); | |
47 | ||
48 | /* Set mmcblk env */ | |
49 | sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); | |
50 | setenv("mmcroot", mmcblk); | |
51 | ||
52 | sprintf(cmd, "mmc dev %d", dev_no); | |
53 | run_command(cmd, 0); | |
54 | } | |
55 | #endif | |
56 | ||
8c998a85 JT |
57 | int board_late_init(void) |
58 | { | |
59 | switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> | |
60 | IMX6_BMODE_SHIFT) { | |
61 | case IMX6_BMODE_SD: | |
62 | case IMX6_BMODE_ESD: | |
63 | case IMX6_BMODE_MMC: | |
64 | case IMX6_BMODE_EMMC: | |
d98fd132 JT |
65 | #ifdef CONFIG_ENV_IS_IN_MMC |
66 | mmc_late_init(); | |
67 | #endif | |
8c998a85 JT |
68 | setenv("modeboot", "mmcboot"); |
69 | break; | |
70 | default: | |
71 | setenv("modeboot", ""); | |
72 | break; | |
73 | } | |
74 | ||
6f1f3f59 JT |
75 | if (is_mx6dq()) |
76 | setenv("fdt_file", "imx6q-icore-rqs.dtb"); | |
77 | else if(is_mx6dl() || is_mx6solo()) | |
78 | setenv("fdt_file", "imx6dl-icore-rqs.dtb"); | |
79 | ||
8c998a85 JT |
80 | return 0; |
81 | } | |
82 | ||
871ec6da JT |
83 | int dram_init(void) |
84 | { | |
85 | gd->ram_size = imx_ddr_size(); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | #ifdef CONFIG_SPL_BUILD | |
91 | #include <libfdt.h> | |
92 | #include <spl.h> | |
93 | ||
94 | #include <asm/arch/crm_regs.h> | |
95 | #include <asm/arch/mx6-ddr.h> | |
96 | ||
b805b174 JT |
97 | #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
98 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
99 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
100 | ||
101 | static iomux_v3_cfg_t const uart4_pads[] = { | |
102 | IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
103 | IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
104 | }; | |
105 | ||
871ec6da JT |
106 | /* MMC board initialization is needed till adding DM support in SPL */ |
107 | #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) | |
108 | #include <mmc.h> | |
109 | #include <fsl_esdhc.h> | |
110 | ||
111 | #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
112 | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ | |
113 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
114 | ||
115 | static iomux_v3_cfg_t const usdhc3_pads[] = { | |
116 | IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
117 | IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
118 | IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
119 | IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
120 | IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
121 | IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
122 | }; | |
123 | ||
ffa11c33 JT |
124 | static iomux_v3_cfg_t const usdhc4_pads[] = { |
125 | IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
126 | IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
127 | IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
128 | IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
129 | IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
130 | IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
131 | IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
132 | IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
133 | IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
134 | IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
135 | }; | |
136 | ||
137 | struct fsl_esdhc_cfg usdhc_cfg[2] = { | |
871ec6da | 138 | {USDHC3_BASE_ADDR, 1, 4}, |
ffa11c33 | 139 | {USDHC4_BASE_ADDR, 1, 8}, |
871ec6da JT |
140 | }; |
141 | ||
142 | int board_mmc_getcd(struct mmc *mmc) | |
143 | { | |
144 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
145 | int ret = 0; | |
146 | ||
147 | switch (cfg->esdhc_base) { | |
148 | case USDHC3_BASE_ADDR: | |
ffa11c33 | 149 | case USDHC4_BASE_ADDR: |
871ec6da JT |
150 | ret = 1; |
151 | break; | |
152 | } | |
153 | ||
154 | return ret; | |
155 | } | |
156 | ||
157 | int board_mmc_init(bd_t *bis) | |
158 | { | |
159 | int i, ret; | |
160 | ||
161 | /* | |
162 | * According to the board_mmc_init() the following map is done: | |
163 | * (U-boot device node) (Physical Port) | |
ffa11c33 JT |
164 | * mmc0 USDHC3 |
165 | * mmc1 USDHC4 | |
871ec6da JT |
166 | */ |
167 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | |
168 | switch (i) { | |
169 | case 0: | |
170 | SETUP_IOMUX_PADS(usdhc3_pads); | |
171 | usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
172 | break; | |
ffa11c33 JT |
173 | case 1: |
174 | SETUP_IOMUX_PADS(usdhc4_pads); | |
175 | usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); | |
176 | break; | |
871ec6da JT |
177 | default: |
178 | printf("Warning - USDHC%d controller not supporting\n", | |
179 | i + 1); | |
180 | return 0; | |
181 | } | |
182 | ||
183 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | |
184 | if (ret) { | |
185 | printf("Warning: failed to initialize mmc dev %d\n", i); | |
186 | return ret; | |
187 | } | |
188 | } | |
189 | ||
190 | return 0; | |
191 | } | |
10fa3ee0 JT |
192 | |
193 | #ifdef CONFIG_ENV_IS_IN_MMC | |
194 | void board_boot_order(u32 *spl_boot_list) | |
195 | { | |
196 | u32 bmode = imx6_src_get_boot_mode(); | |
197 | u8 boot_dev = BOOT_DEVICE_MMC1; | |
198 | ||
199 | switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) { | |
200 | case IMX6_BMODE_SD: | |
201 | case IMX6_BMODE_ESD: | |
202 | /* SD/eSD - BOOT_DEVICE_MMC1 */ | |
203 | break; | |
204 | case IMX6_BMODE_MMC: | |
205 | case IMX6_BMODE_EMMC: | |
206 | /* MMC/eMMC */ | |
207 | boot_dev = BOOT_DEVICE_MMC2; | |
208 | break; | |
209 | default: | |
210 | /* Default - BOOT_DEVICE_MMC1 */ | |
211 | printf("Wrong board boot order\n"); | |
212 | break; | |
213 | } | |
214 | ||
215 | spl_boot_list[0] = boot_dev; | |
216 | } | |
217 | #endif | |
871ec6da JT |
218 | #endif |
219 | ||
bc1fe900 JT |
220 | #ifdef CONFIG_SPL_LOAD_FIT |
221 | int board_fit_config_name_match(const char *name) | |
222 | { | |
223 | if (is_mx6dq() && !strcmp(name, "imx6q-icore-rqs")) | |
224 | return 0; | |
225 | else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore-rqs")) | |
226 | return 0; | |
227 | else | |
228 | return -1; | |
229 | } | |
230 | #endif | |
231 | ||
871ec6da JT |
232 | /* |
233 | * Driving strength: | |
234 | * 0x30 == 40 Ohm | |
235 | * 0x28 == 48 Ohm | |
236 | */ | |
237 | ||
238 | #define IMX6DQ_DRIVE_STRENGTH 0x30 | |
239 | #define IMX6SDL_DRIVE_STRENGTH 0x28 | |
240 | ||
241 | /* configure MX6Q/DUAL mmdc DDR io registers */ | |
242 | static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { | |
243 | .dram_sdqs0 = 0x28, | |
244 | .dram_sdqs1 = 0x28, | |
245 | .dram_sdqs2 = 0x28, | |
246 | .dram_sdqs3 = 0x28, | |
247 | .dram_sdqs4 = 0x28, | |
248 | .dram_sdqs5 = 0x28, | |
249 | .dram_sdqs6 = 0x28, | |
250 | .dram_sdqs7 = 0x28, | |
251 | .dram_dqm0 = 0x28, | |
252 | .dram_dqm1 = 0x28, | |
253 | .dram_dqm2 = 0x28, | |
254 | .dram_dqm3 = 0x28, | |
255 | .dram_dqm4 = 0x28, | |
256 | .dram_dqm5 = 0x28, | |
257 | .dram_dqm6 = 0x28, | |
258 | .dram_dqm7 = 0x28, | |
259 | .dram_cas = 0x30, | |
260 | .dram_ras = 0x30, | |
261 | .dram_sdclk_0 = 0x30, | |
262 | .dram_sdclk_1 = 0x30, | |
263 | .dram_reset = 0x30, | |
264 | .dram_sdcke0 = 0x3000, | |
265 | .dram_sdcke1 = 0x3000, | |
266 | .dram_sdba2 = 0x00000000, | |
267 | .dram_sdodt0 = 0x30, | |
268 | .dram_sdodt1 = 0x30, | |
269 | }; | |
270 | ||
271 | /* configure MX6Q/DUAL mmdc GRP io registers */ | |
272 | static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { | |
273 | .grp_b0ds = 0x30, | |
274 | .grp_b1ds = 0x30, | |
275 | .grp_b2ds = 0x30, | |
276 | .grp_b3ds = 0x30, | |
277 | .grp_b4ds = 0x30, | |
278 | .grp_b5ds = 0x30, | |
279 | .grp_b6ds = 0x30, | |
280 | .grp_b7ds = 0x30, | |
281 | .grp_addds = 0x30, | |
282 | .grp_ddrmode_ctl = 0x00020000, | |
283 | .grp_ddrpke = 0x00000000, | |
284 | .grp_ddrmode = 0x00020000, | |
285 | .grp_ctlds = 0x30, | |
286 | .grp_ddr_type = 0x000c0000, | |
287 | }; | |
288 | ||
289 | /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ | |
290 | struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { | |
291 | .dram_sdclk_0 = 0x30, | |
292 | .dram_sdclk_1 = 0x30, | |
293 | .dram_cas = 0x30, | |
294 | .dram_ras = 0x30, | |
295 | .dram_reset = 0x30, | |
296 | .dram_sdcke0 = 0x30, | |
297 | .dram_sdcke1 = 0x30, | |
298 | .dram_sdba2 = 0x00000000, | |
299 | .dram_sdodt0 = 0x30, | |
300 | .dram_sdodt1 = 0x30, | |
301 | .dram_sdqs0 = 0x28, | |
302 | .dram_sdqs1 = 0x28, | |
303 | .dram_sdqs2 = 0x28, | |
304 | .dram_sdqs3 = 0x28, | |
305 | .dram_sdqs4 = 0x28, | |
306 | .dram_sdqs5 = 0x28, | |
307 | .dram_sdqs6 = 0x28, | |
308 | .dram_sdqs7 = 0x28, | |
309 | .dram_dqm0 = 0x28, | |
310 | .dram_dqm1 = 0x28, | |
311 | .dram_dqm2 = 0x28, | |
312 | .dram_dqm3 = 0x28, | |
313 | .dram_dqm4 = 0x28, | |
314 | .dram_dqm5 = 0x28, | |
315 | .dram_dqm6 = 0x28, | |
316 | .dram_dqm7 = 0x28, | |
317 | }; | |
318 | ||
319 | /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ | |
320 | struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { | |
321 | .grp_ddr_type = 0x000c0000, | |
322 | .grp_ddrmode_ctl = 0x00020000, | |
323 | .grp_ddrpke = 0x00000000, | |
324 | .grp_addds = 0x30, | |
325 | .grp_ctlds = 0x30, | |
326 | .grp_ddrmode = 0x00020000, | |
327 | .grp_b0ds = 0x28, | |
328 | .grp_b1ds = 0x28, | |
329 | .grp_b2ds = 0x28, | |
330 | .grp_b3ds = 0x28, | |
331 | .grp_b4ds = 0x28, | |
332 | .grp_b5ds = 0x28, | |
333 | .grp_b6ds = 0x28, | |
334 | .grp_b7ds = 0x28, | |
335 | }; | |
336 | ||
337 | /* mt41j256 */ | |
338 | static struct mx6_ddr3_cfg mt41j256 = { | |
339 | .mem_speed = 1066, | |
340 | .density = 2, | |
341 | .width = 16, | |
342 | .banks = 8, | |
343 | .rowaddr = 13, | |
344 | .coladdr = 10, | |
345 | .pagesz = 2, | |
346 | .trcd = 1375, | |
347 | .trcmin = 4875, | |
348 | .trasmin = 3500, | |
349 | .SRT = 0, | |
350 | }; | |
351 | ||
352 | static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { | |
353 | .p0_mpwldectrl0 = 0x000E0009, | |
354 | .p0_mpwldectrl1 = 0x0018000E, | |
355 | .p1_mpwldectrl0 = 0x00000007, | |
356 | .p1_mpwldectrl1 = 0x00000000, | |
357 | .p0_mpdgctrl0 = 0x43280334, | |
358 | .p0_mpdgctrl1 = 0x031C0314, | |
359 | .p1_mpdgctrl0 = 0x4318031C, | |
360 | .p1_mpdgctrl1 = 0x030C0258, | |
361 | .p0_mprddlctl = 0x3E343A40, | |
362 | .p1_mprddlctl = 0x383C3844, | |
363 | .p0_mpwrdlctl = 0x40404440, | |
364 | .p1_mpwrdlctl = 0x4C3E4446, | |
365 | }; | |
366 | ||
367 | /* DDR 64bit */ | |
368 | static struct mx6_ddr_sysinfo mem_q = { | |
369 | .ddr_type = DDR_TYPE_DDR3, | |
370 | .dsize = 2, | |
371 | .cs1_mirror = 0, | |
372 | /* config for full 4GB range so that get_mem_size() works */ | |
373 | .cs_density = 32, | |
374 | .ncs = 1, | |
375 | .bi_on = 1, | |
376 | .rtt_nom = 2, | |
377 | .rtt_wr = 2, | |
378 | .ralat = 5, | |
379 | .walat = 0, | |
380 | .mif3_mode = 3, | |
381 | .rst_to_cke = 0x23, | |
382 | .sde_to_rst = 0x10, | |
383 | }; | |
384 | ||
385 | static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { | |
386 | .p0_mpwldectrl0 = 0x001F0024, | |
387 | .p0_mpwldectrl1 = 0x00110018, | |
388 | .p1_mpwldectrl0 = 0x001F0024, | |
389 | .p1_mpwldectrl1 = 0x00110018, | |
390 | .p0_mpdgctrl0 = 0x4230022C, | |
391 | .p0_mpdgctrl1 = 0x02180220, | |
392 | .p1_mpdgctrl0 = 0x42440248, | |
393 | .p1_mpdgctrl1 = 0x02300238, | |
394 | .p0_mprddlctl = 0x44444A48, | |
395 | .p1_mprddlctl = 0x46484A42, | |
396 | .p0_mpwrdlctl = 0x38383234, | |
397 | .p1_mpwrdlctl = 0x3C34362E, | |
398 | }; | |
399 | ||
400 | /* DDR 64bit 1GB */ | |
401 | static struct mx6_ddr_sysinfo mem_dl = { | |
402 | .dsize = 2, | |
403 | .cs1_mirror = 0, | |
404 | /* config for full 4GB range so that get_mem_size() works */ | |
405 | .cs_density = 32, | |
406 | .ncs = 1, | |
407 | .bi_on = 1, | |
408 | .rtt_nom = 1, | |
409 | .rtt_wr = 1, | |
410 | .ralat = 5, | |
411 | .walat = 0, | |
412 | .mif3_mode = 3, | |
413 | .rst_to_cke = 0x23, | |
414 | .sde_to_rst = 0x10, | |
415 | }; | |
416 | ||
417 | /* DDR 32bit 512MB */ | |
418 | static struct mx6_ddr_sysinfo mem_s = { | |
419 | .dsize = 1, | |
420 | .cs1_mirror = 0, | |
421 | /* config for full 4GB range so that get_mem_size() works */ | |
422 | .cs_density = 32, | |
423 | .ncs = 1, | |
424 | .bi_on = 1, | |
425 | .rtt_nom = 1, | |
426 | .rtt_wr = 1, | |
427 | .ralat = 5, | |
428 | .walat = 0, | |
429 | .mif3_mode = 3, | |
430 | .rst_to_cke = 0x23, | |
431 | .sde_to_rst = 0x10, | |
432 | }; | |
433 | ||
434 | static void ccgr_init(void) | |
435 | { | |
436 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
437 | ||
438 | writel(0x00003F3F, &ccm->CCGR0); | |
439 | writel(0x0030FC00, &ccm->CCGR1); | |
440 | writel(0x000FC000, &ccm->CCGR2); | |
441 | writel(0x3F300000, &ccm->CCGR3); | |
442 | writel(0xFF00F300, &ccm->CCGR4); | |
443 | writel(0x0F0000C3, &ccm->CCGR5); | |
444 | writel(0x000003CC, &ccm->CCGR6); | |
445 | } | |
446 | ||
447 | static void gpr_init(void) | |
448 | { | |
449 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
450 | ||
451 | /* enable AXI cache for VDOA/VPU/IPU */ | |
452 | writel(0xF00000CF, &iomux->gpr[4]); | |
453 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ | |
454 | writel(0x007F007F, &iomux->gpr[6]); | |
455 | writel(0x007F007F, &iomux->gpr[7]); | |
456 | } | |
457 | ||
458 | static void spl_dram_init(void) | |
459 | { | |
460 | if (is_mx6solo()) { | |
461 | mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); | |
462 | mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); | |
463 | } else if (is_mx6dl()) { | |
464 | mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); | |
465 | mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); | |
466 | } else if (is_mx6dq()) { | |
467 | mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); | |
468 | mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); | |
469 | } | |
470 | ||
471 | udelay(100); | |
472 | } | |
473 | ||
474 | void board_init_f(ulong dummy) | |
475 | { | |
476 | ccgr_init(); | |
477 | ||
478 | /* setup AIPS and disable watchdog */ | |
479 | arch_cpu_init(); | |
480 | ||
481 | gpr_init(); | |
482 | ||
483 | /* iomux */ | |
b805b174 | 484 | SETUP_IOMUX_PADS(uart4_pads); |
871ec6da JT |
485 | |
486 | /* setup GP timer */ | |
487 | timer_init(); | |
488 | ||
489 | /* UART clocks enabled and gd valid - init serial console */ | |
490 | preloader_console_init(); | |
491 | ||
492 | /* DDR initialization */ | |
493 | spl_dram_init(); | |
494 | ||
495 | /* Clear the BSS. */ | |
496 | memset(__bss_start, 0, __bss_end - __bss_start); | |
497 | ||
498 | /* load/boot image from boot device */ | |
499 | board_init_r(NULL, 0); | |
500 | } | |
501 | #endif |