[people/ms/u-boot.git] / board / engicam / isiotmx6ul / isiotmx6ul.c

/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 * Author: Jagan Teki <jagan@amarulasolutions.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>

#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>

#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_NAND_MXS

#define GPMI_PAD_CTRL0		(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1		(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
				PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2		(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)

static iomux_v3_cfg_t const nand_pads[] = {
	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
};

static void setup_gpmi_nand(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* config gpmi nand iomux */
	SETUP_IOMUX_PADS(nand_pads);

	clrbits_le32(&mxc_ccm->CCGR4,
		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);

	/*
	 * config gpmi and bch clock to 100 MHz
	 * bch/gpmi select PLL2 PFD2 400M
	 * 100M = 400M / 4
	 */
	clrbits_le32(&mxc_ccm->cscmr1,
		     MXC_CCM_CSCMR1_BCH_CLK_SEL |
		     MXC_CCM_CSCMR1_GPMI_CLK_SEL);
	clrsetbits_le32(&mxc_ccm->cscdr1,
			MXC_CCM_CSCDR1_BCH_PODF_MASK |
			MXC_CCM_CSCDR1_GPMI_PODF_MASK,
			(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
			(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));

	/* enable gpmi and bch clock gating */
	setbits_le32(&mxc_ccm->CCGR4,
		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);

	/* enable apbh clock gating */
	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif /* CONFIG_NAND_MXS */

#ifdef CONFIG_ENV_IS_IN_MMC
int board_mmc_get_env_dev(int devno)
{
	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
	return (devno == 0) ? 0 : 1;
}

static void mmc_late_init(void)
{
	char cmd[32];
	char mmcblk[32];
	u32 dev_no = mmc_get_env_dev();

	setenv_ulong("mmcdev", dev_no);

	/* Set mmcblk env */
	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
	setenv("mmcroot", mmcblk);

	sprintf(cmd, "mmc dev %d", dev_no);
	run_command(cmd, 0);
}
#endif

int board_late_init(void)
{
	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
			IMX6_BMODE_SHIFT) {
	case IMX6_BMODE_SD:
	case IMX6_BMODE_ESD:
	case IMX6_BMODE_MMC:
	case IMX6_BMODE_EMMC:
#ifdef CONFIG_ENV_IS_IN_MMC
		mmc_late_init();
#endif
		setenv("modeboot", "mmcboot");
		break;
	case IMX6_BMODE_NAND:
		setenv("modeboot", "nandboot");
		break;
	default:
		setenv("modeboot", "");
		break;
	}

	if (is_mx6ul()) {
#ifdef CONFIG_ENV_IS_IN_MMC
		setenv("fdt_file", "imx6ul-isiot-emmc.dtb");
#else
		setenv("fdt_file", "imx6ul-isiot-nand.dtb");
#endif
	}

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_NAND_MXS
	setup_gpmi_nand();
#endif
	return 0;
}

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

#ifdef CONFIG_SPL_BUILD
#include <spl.h>

/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const usdhc1_pads[] = {
	IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),

	/* VSELECT */
	IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	/* CD */
	IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* RST_B */
	IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static iomux_v3_cfg_t const usdhc2_pads[] = {
	IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};

#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 19)
#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 5)

struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC1_BASE_ADDR, 0, 4},
	{USDHC2_BASE_ADDR, 0, 8},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = !gpio_get_value(USDHC1_CD_GPIO);
		break;
	case USDHC2_BASE_ADDR:
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int i, ret;

	/*
	* According to the board_mmc_init() the following map is done:
	* (U-boot device node)    (Physical Port)
	* mmc0				USDHC1
	* mmc1				USDHC2
	*/
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			SETUP_IOMUX_PADS(usdhc1_pads);
			gpio_direction_input(USDHC1_CD_GPIO);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
			break;
		case 1:
			SETUP_IOMUX_PADS(usdhc2_pads);
			gpio_direction_input(USDHC2_CD_GPIO);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
			break;
		default:
			printf("Warning - USDHC%d controller not supporting\n",
			       i + 1);
			return 0;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret) {
			printf("Warning: failed to initialize mmc dev %d\n", i);
			return ret;
		}
	}

	return 0;
}

#ifdef CONFIG_ENV_IS_IN_MMC
void board_boot_order(u32 *spl_boot_list)
{
	u32 bmode = imx6_src_get_boot_mode();
	u8 boot_dev = BOOT_DEVICE_MMC1;

	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
	case IMX6_BMODE_SD:
	case IMX6_BMODE_ESD:
		/* SD/eSD - BOOT_DEVICE_MMC1 */
		break;
	case IMX6_BMODE_MMC:
	case IMX6_BMODE_EMMC:
		/* MMC/eMMC */
		boot_dev = BOOT_DEVICE_MMC2;
		break;
	default:
		/* Default - BOOT_DEVICE_MMC1 */
		printf("Wrong board boot order\n");
		break;
	}

	spl_boot_list[0] = boot_dev;
}
#endif
#endif /* CONFIG_FSL_ESDHC */
#endif /* CONFIG_SPL_BUILD */
Commit	Line	Data
e9dfa1e1 JT	1	/*
	2	* Copyright (C) 2016 Amarula Solutions B.V.
	3	* Copyright (C) 2016 Engicam S.r.l.
	4	* Author: Jagan Teki <jagan@amarulasolutions.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
0dd259a1	10	#include <mmc.h>
e9dfa1e1 JT	11
	12	#include <asm/io.h>
	13	#include <asm/gpio.h>
	14	#include <linux/sizes.h>
	15
	16	#include <asm/arch/clock.h>
	17	#include <asm/arch/crm_regs.h>
	18	#include <asm/arch/iomux.h>
	19	#include <asm/arch/mx6-pins.h>
	20	#include <asm/arch/sys_proto.h>
	21	#include <asm/imx-common/iomux-v3.h>
	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
6788a7e4 JT	25	#ifdef CONFIG_NAND_MXS
	26
	27	#define GPMI_PAD_CTRL0 (PAD_CTL_PKE \| PAD_CTL_PUE \| PAD_CTL_PUS_100K_UP)
	28	#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm \| PAD_CTL_SPEED_MED \| \
	29	PAD_CTL_SRE_FAST)
	30	#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 \| GPMI_PAD_CTRL1)
	31
	32	static iomux_v3_cfg_t const nand_pads[] = {
534bf2cc JT	33	IOMUX_PADS(PAD_NAND_DATA00__RAWNAND_DATA00 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	34	IOMUX_PADS(PAD_NAND_DATA01__RAWNAND_DATA01 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	35	IOMUX_PADS(PAD_NAND_DATA02__RAWNAND_DATA02 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	36	IOMUX_PADS(PAD_NAND_DATA03__RAWNAND_DATA03 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	37	IOMUX_PADS(PAD_NAND_DATA04__RAWNAND_DATA04 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	38	IOMUX_PADS(PAD_NAND_DATA05__RAWNAND_DATA05 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	39	IOMUX_PADS(PAD_NAND_DATA06__RAWNAND_DATA06 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	40	IOMUX_PADS(PAD_NAND_DATA07__RAWNAND_DATA07 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	41	IOMUX_PADS(PAD_NAND_CLE__RAWNAND_CLE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	42	IOMUX_PADS(PAD_NAND_ALE__RAWNAND_ALE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	43	IOMUX_PADS(PAD_NAND_CE0_B__RAWNAND_CE0_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	44	IOMUX_PADS(PAD_NAND_RE_B__RAWNAND_RE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	45	IOMUX_PADS(PAD_NAND_WE_B__RAWNAND_WE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	46	IOMUX_PADS(PAD_NAND_WP_B__RAWNAND_WP_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	47	IOMUX_PADS(PAD_NAND_READY_B__RAWNAND_READY_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
6788a7e4 JT	48	};
	49
	50	static void setup_gpmi_nand(void)
	51	{
	52	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	53
	54	/* config gpmi nand iomux */
534bf2cc	55	SETUP_IOMUX_PADS(nand_pads);
6788a7e4 JT	56
	57	clrbits_le32(&mxc_ccm->CCGR4,
	58	MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK \|
	59	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK \|
	60	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK \|
	61	MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK \|
	62	MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
	63
	64	/*
	65	* config gpmi and bch clock to 100 MHz
	66	* bch/gpmi select PLL2 PFD2 400M
	67	* 100M = 400M / 4
	68	*/
	69	clrbits_le32(&mxc_ccm->cscmr1,
	70	MXC_CCM_CSCMR1_BCH_CLK_SEL \|
	71	MXC_CCM_CSCMR1_GPMI_CLK_SEL);
	72	clrsetbits_le32(&mxc_ccm->cscdr1,
	73	MXC_CCM_CSCDR1_BCH_PODF_MASK \|
	74	MXC_CCM_CSCDR1_GPMI_PODF_MASK,
	75	(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) \|
	76	(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
	77
	78	/* enable gpmi and bch clock gating */
	79	setbits_le32(&mxc_ccm->CCGR4,
	80	MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK \|
	81	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK \|
	82	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK \|
	83	MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK \|
	84	MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
	85
	86	/* enable apbh clock gating */
	87	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
	88	}
	89	#endif /* CONFIG_NAND_MXS */
	90
0dd259a1	91	#ifdef CONFIG_ENV_IS_IN_MMC
e9685967 JT	92	int board_mmc_get_env_dev(int devno)
	93	{
	94	/* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
	95	return (devno == 0) ? 0 : 1;
	96	}
	97
0dd259a1 JT	98	static void mmc_late_init(void)
	99	{
	100	char cmd[32];
	101	char mmcblk[32];
	102	u32 dev_no = mmc_get_env_dev();
	103
	104	setenv_ulong("mmcdev", dev_no);
	105
	106	/* Set mmcblk env */
	107	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
	108	setenv("mmcroot", mmcblk);
	109
	110	sprintf(cmd, "mmc dev %d", dev_no);
	111	run_command(cmd, 0);
	112	}
	113	#endif
	114
2e2a8dc6 JT	115	int board_late_init(void)
	116	{
	117	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
	118	IMX6_BMODE_SHIFT) {
	119	case IMX6_BMODE_SD:
	120	case IMX6_BMODE_ESD:
	121	case IMX6_BMODE_MMC:
	122	case IMX6_BMODE_EMMC:
0dd259a1 JT	123	#ifdef CONFIG_ENV_IS_IN_MMC
	124	mmc_late_init();
	125	#endif
2e2a8dc6 JT	126	setenv("modeboot", "mmcboot");
	127	break;
	128	case IMX6_BMODE_NAND:
	129	setenv("modeboot", "nandboot");
	130	break;
	131	default:
	132	setenv("modeboot", "");
	133	break;
	134	}
	135
6f1f3f59 JT	136	if (is_mx6ul()) {
	137	#ifdef CONFIG_ENV_IS_IN_MMC
	138	setenv("fdt_file", "imx6ul-isiot-emmc.dtb");
	139	#else
	140	setenv("fdt_file", "imx6ul-isiot-nand.dtb");
	141	#endif
	142	}
	143
2e2a8dc6 JT	144	return 0;
	145	}
	146
e9dfa1e1 JT	147	int board_init(void)
	148	{
	149	/* Address of boot parameters */
	150	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	151
6788a7e4 JT	152	#ifdef CONFIG_NAND_MXS
	153	setup_gpmi_nand();
	154	#endif
e9dfa1e1 JT	155	return 0;
	156	}
	157
	158	int dram_init(void)
	159	{
	160	gd->ram_size = imx_ddr_size();
	161
	162	return 0;
	163	}
	164
	165	#ifdef CONFIG_SPL_BUILD
e9dfa1e1 JT	166	#include <spl.h>
e9dfa1e1 JT	167
e9dfa1e1 JT	168	/* MMC board initialization is needed till adding DM support in SPL */
	169	#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
	170	#include <mmc.h>
	171	#include <fsl_esdhc.h>
	172
	173	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	174	PAD_CTL_PUS_22K_UP \| PAD_CTL_SPEED_LOW \| \
	175	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	176
	177	static iomux_v3_cfg_t const usdhc1_pads[] = {
534bf2cc JT	178	IOMUX_PADS(PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	179	IOMUX_PADS(PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	180	IOMUX_PADS(PAD_SD1_DATA0__USDHC1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	181	IOMUX_PADS(PAD_SD1_DATA1__USDHC1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	182	IOMUX_PADS(PAD_SD1_DATA2__USDHC1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	183	IOMUX_PADS(PAD_SD1_DATA3__USDHC1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
e9dfa1e1 JT	184
e9dfa1e1 JT	185	/* VSELECT */
534bf2cc	186	IOMUX_PADS(PAD_GPIO1_IO05__USDHC1_VSELECT \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
e9dfa1e1	187	/* CD */
534bf2cc	188	IOMUX_PADS(PAD_UART1_RTS_B__GPIO1_IO19 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
e9dfa1e1	189	/* RST_B */
534bf2cc	190	IOMUX_PADS(PAD_GPIO1_IO09__GPIO1_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
e9dfa1e1 JT	191	};
e9dfa1e1 JT	192
7cf22dc8	193	static iomux_v3_cfg_t const usdhc2_pads[] = {
534bf2cc JT	194	IOMUX_PADS(PAD_NAND_ALE__USDHC2_RESET_B \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	195	IOMUX_PADS(PAD_NAND_RE_B__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	196	IOMUX_PADS(PAD_NAND_WE_B__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	197	IOMUX_PADS(PAD_NAND_DATA00__USDHC2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	198	IOMUX_PADS(PAD_NAND_DATA01__USDHC2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	199	IOMUX_PADS(PAD_NAND_DATA02__USDHC2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	200	IOMUX_PADS(PAD_NAND_DATA03__USDHC2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	201	IOMUX_PADS(PAD_NAND_DATA04__USDHC2_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	202	IOMUX_PADS(PAD_NAND_DATA05__USDHC2_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
7cf22dc8 JT	203	};
7cf22dc8 JT	204
e9dfa1e1	205	#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
7cf22dc8	206	#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
e9dfa1e1	207
7cf22dc8	208	struct fsl_esdhc_cfg usdhc_cfg[2] = {
e9dfa1e1	209	{USDHC1_BASE_ADDR, 0, 4},
7cf22dc8	210	{USDHC2_BASE_ADDR, 0, 8},
e9dfa1e1 JT	211	};
	212
	213	int board_mmc_getcd(struct mmc *mmc)
	214	{
	215	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	216	int ret = 0;
	217
	218	switch (cfg->esdhc_base) {
	219	case USDHC1_BASE_ADDR:
	220	ret = !gpio_get_value(USDHC1_CD_GPIO);
	221	break;
7cf22dc8 JT	222	case USDHC2_BASE_ADDR:
	223	ret = !gpio_get_value(USDHC2_CD_GPIO);
	224	break;
e9dfa1e1 JT	225	}
	226
	227	return ret;
	228	}
	229
	230	int board_mmc_init(bd_t *bis)
	231	{
	232	int i, ret;
	233
	234	/*
	235	* According to the board_mmc_init() the following map is done:
	236	* (U-boot device node) (Physical Port)
	237	* mmc0 USDHC1
7cf22dc8	238	* mmc1 USDHC2
e9dfa1e1 JT	239	*/
	240	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	241	switch (i) {
	242	case 0:
534bf2cc	243	SETUP_IOMUX_PADS(usdhc1_pads);
e9dfa1e1 JT	244	gpio_direction_input(USDHC1_CD_GPIO);
	245	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	246	break;
7cf22dc8	247	case 1:
534bf2cc	248	SETUP_IOMUX_PADS(usdhc2_pads);
7cf22dc8 JT	249	gpio_direction_input(USDHC2_CD_GPIO);
	250	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	251	break;
e9dfa1e1 JT	252	default:
	253	printf("Warning - USDHC%d controller not supporting\n",
	254	i + 1);
	255	return 0;
	256	}
	257
	258	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	259	if (ret) {
	260	printf("Warning: failed to initialize mmc dev %d\n", i);
	261	return ret;
	262	}
	263	}
	264
	265	return 0;
	266	}
cde5aa37 JT	267
	268	#ifdef CONFIG_ENV_IS_IN_MMC
	269	void board_boot_order(u32 *spl_boot_list)
	270	{
	271	u32 bmode = imx6_src_get_boot_mode();
	272	u8 boot_dev = BOOT_DEVICE_MMC1;
	273
	274	switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
	275	case IMX6_BMODE_SD:
	276	case IMX6_BMODE_ESD:
	277	/* SD/eSD - BOOT_DEVICE_MMC1 */
	278	break;
	279	case IMX6_BMODE_MMC:
	280	case IMX6_BMODE_EMMC:
	281	/* MMC/eMMC */
	282	boot_dev = BOOT_DEVICE_MMC2;
	283	break;
	284	default:
	285	/* Default - BOOT_DEVICE_MMC1 */
	286	printf("Wrong board boot order\n");
	287	break;
	288	}
	289
	290	spl_boot_list[0] = boot_dev;
	291	}
	292	#endif
e9dfa1e1	293	#endif /* CONFIG_FSL_ESDHC */
e9dfa1e1	294	#endif /* CONFIG_SPL_BUILD */