[people/ms/u-boot.git] / board / esd / cpci2dp / cpci2dp.c

/*
 * (C) Copyright 2005
 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f (void)
{
	unsigned long cntrl0Reg;

	/*
	 * Setup GPIO pins
	 */
	cntrl0Reg = mfdcr(cntrl0);
	mtdcr(cntrl0, cntrl0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));

	/* set output pins to high */
	out32(GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
	/* setup for output (LED=off) */
	out32(GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);

	/*
	 * IRQ 0-15  405GP internally generated; active high; level sensitive
	 * IRQ 16    405GP internally generated; active low; level sensitive
	 * IRQ 17-24 RESERVED
	 * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
	 * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	 * IRQ 31 (EXT IRQ 6) unused
	 */
	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
	mtdcr(uicer, 0x00000000);	/* disable all ints */
	mtdcr(uiccr, 0x00000000);	/* set all to be non-critical*/
	mtdcr(uicpr, 0xFFFFFF81);	/* set int polarities */

	mtdcr(uictr, 0x10000000);	/* set int trigger levels */
	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority*/
	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */

	return 0;
}

int misc_init_r (void)
{
	unsigned long cntrl0Reg;

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/*
	 * Select cts (and not dsr) on uart1
	 */
	cntrl0Reg = mfdcr(cntrl0);
	mtdcr(cntrl0, cntrl0Reg | 0x00001000);

	return (0);
}


/*
 * Check Board Identity:
 */
int checkboard (void)
{
	char str[64];
	int i = getenv_r ("serial#", str, sizeof(str));

	puts ("Board: ");

	if (i == -1) {
		puts ("### No HW ID - assuming CPCI2DP");
	} else {
		puts(str);
	}

	printf(" (Ver 1.0)");

	putc ('\n');

	return 0;
}

#if defined(CONFIG_SYS_EEPROM_WREN)
/* Input: <dev_addr>  I2C address of EEPROM device to enable.
 *	   <state>     -1: deliver current state
 *		       0: disable write
 *		       1: enable write
 *  Returns:	       -1: wrong device address
 *			0: dis-/en- able done
 *		     0/1: current state if <state> was -1.
 */
int eeprom_write_enable (unsigned dev_addr, int state) {
	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
		return -1;
	} else {
		switch (state) {
		case 1:
			/* Enable write access, clear bit GPIO_SINT2. */
			out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
			state = 0;
			break;
		case 0:
			/* Disable write access, set bit GPIO_SINT2. */
			out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
			state = 0;
			break;
		default:
			/* Read current status back. */
			state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
			break;
		}
	}
	return state;
}
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int query = argc == 1;
	int state = 0;

	if (query) {
		/* Query write access state. */
		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
		if (state < 0) {
			puts ("Query of write access state failed.\n");
		} else {
			printf ("Write access for device 0x%0x is %sabled.\n",
				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
			state = 0;
		}
	} else {
		if ('0' == argv[1][0]) {
			/* Disable write access. */
			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
		} else {
			/* Enable write access. */
			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
		}
		if (state < 0) {
			puts ("Setup of write access state failed.\n");
		}
	}

	return state;
}

U_BOOT_CMD(
	eepwren,	2,	0,	do_eep_wren,
	"Enable / disable / query EEPROM write access",
	NULL
	);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
Commit	Line	Data
7644f16f SR	1	/*
	2	* (C) Copyright 2005
	3	* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
f013dacf	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7644f16f SR	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <asm/processor.h>
	26	#include <command.h>
	27	#include <malloc.h>
	28
d87080b7 WD	29	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	30
7644f16f SR	31	int board_early_init_f (void)
	32	{
	33	unsigned long cntrl0Reg;
	34
	35	/*
2076d0a1	36	* Setup GPIO pins
7644f16f SR	37	*/
7644f16f SR	38	cntrl0Reg = mfdcr(cntrl0);
6d0f6bcf	39	mtdcr(cntrl0, cntrl0Reg \| ((CONFIG_SYS_EEPROM_WP \| CONFIG_SYS_PB_LED \| CONFIG_SYS_SELF_RST \| CONFIG_SYS_INTA_FAKE) << 5));
7644f16f	40
bfc81252	41	/* set output pins to high */
6d0f6bcf	42	out32(GPIO0_OR, CONFIG_SYS_EEPROM_WP);
bfc81252	43	/* setup for output (LED=off) */
6d0f6bcf	44	out32(GPIO0_TCR, CONFIG_SYS_EEPROM_WP \| CONFIG_SYS_PB_LED);
7644f16f SR	45
	46	/*
	47	* IRQ 0-15 405GP internally generated; active high; level sensitive
	48	* IRQ 16 405GP internally generated; active low; level sensitive
	49	* IRQ 17-24 RESERVED
	50	* IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
	51	* IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
	52	* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
	53	* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
	54	* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
	55	* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
	56	* IRQ 31 (EXT IRQ 6) unused
	57	*/
f013dacf WD	58	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	59	mtdcr(uicer, 0x00000000); /* disable all ints */
	60	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
	61	mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
7644f16f	62
f013dacf WD	63	mtdcr(uictr, 0x10000000); /* set int trigger levels */
	64	mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	65	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
7644f16f SR	66
	67	return 0;
	68	}
	69
7644f16f SR	70	int misc_init_r (void)
7644f16f SR	71	{
7644f16f SR	72	unsigned long cntrl0Reg;
	73
	74	/* adjust flash start and offset */
	75	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	76	gd->bd->bi_flashoffset = 0;
	77
	78	/*
	79	* Select cts (and not dsr) on uart1
	80	*/
	81	cntrl0Reg = mfdcr(cntrl0);
	82	mtdcr(cntrl0, cntrl0Reg \| 0x00001000);
	83
	84	return (0);
	85	}
	86
	87
	88	/*
	89	* Check Board Identity:
	90	*/
	91	int checkboard (void)
	92	{
77ddac94	93	char str[64];
7644f16f SR	94	int i = getenv_r ("serial#", str, sizeof(str));
	95
	96	puts ("Board: ");
	97
	98	if (i == -1) {
	99	puts ("### No HW ID - assuming CPCI2DP");
	100	} else {
	101	puts(str);
	102	}
	103
	104	printf(" (Ver 1.0)");
	105
	106	putc ('\n');
	107
	108	return 0;
	109	}
	110
6d0f6bcf	111	#if defined(CONFIG_SYS_EEPROM_WREN)
7644f16f	112	/* Input: <dev_addr> I2C address of EEPROM device to enable.
f013dacf WD	113	* <state> -1: deliver current state
f013dacf WD	114	* 0: disable write
7644f16f	115	* 1: enable write
f013dacf WD	116	* Returns: -1: wrong device address
f013dacf WD	117	* 0: dis-/en- able done
7644f16f SR	118	* 0/1: current state if <state> was -1.
	119	*/
	120	int eeprom_write_enable (unsigned dev_addr, int state) {
6d0f6bcf	121	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
7644f16f	122	return -1;
f013dacf	123	} else {
7644f16f SR	124	switch (state) {
	125	case 1:
	126	/* Enable write access, clear bit GPIO_SINT2. */
6d0f6bcf	127	out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
7644f16f SR	128	state = 0;
	129	break;
	130	case 0:
	131	/* Disable write access, set bit GPIO_SINT2. */
6d0f6bcf	132	out32(GPIO0_OR, in32(GPIO0_OR) \| CONFIG_SYS_EEPROM_WP);
7644f16f SR	133	state = 0;
	134	break;
	135	default:
	136	/* Read current status back. */
6d0f6bcf	137	state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
7644f16f SR	138	break;
	139	}
	140	}
	141	return state;
	142	}
	143	#endif
	144
6d0f6bcf	145	#if defined(CONFIG_SYS_EEPROM_WREN)
7644f16f SR	146	int do_eep_wren (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	147	{
	148	int query = argc == 1;
	149	int state = 0;
	150
	151	if (query) {
	152	/* Query write access state. */
6d0f6bcf	153	state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
7644f16f SR	154	if (state < 0) {
7644f16f SR	155	puts ("Query of write access state failed.\n");
f013dacf	156	} else {
7644f16f	157	printf ("Write access for device 0x%0x is %sabled.\n",
6d0f6bcf	158	CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
7644f16f SR	159	state = 0;
7644f16f SR	160	}
f013dacf	161	} else {
7644f16f SR	162	if ('0' == argv[1][0]) {
7644f16f SR	163	/* Disable write access. */
6d0f6bcf	164	state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
f013dacf	165	} else {
7644f16f	166	/* Enable write access. */
6d0f6bcf	167	state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
7644f16f SR	168	}
	169	if (state < 0) {
	170	puts ("Setup of write access state failed.\n");
	171	}
	172	}
	173
	174	return state;
	175	}
	176
	177	U_BOOT_CMD(
2076d0a1	178	eepwren, 2, 0, do_eep_wren,
2fb2604d	179	"Enable / disable / query EEPROM write access",
2076d0a1 SR	180	NULL
2076d0a1 SR	181	);
6d0f6bcf	182	#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */