[people/ms/u-boot.git] / board / esd / dasa_sim / dasa_sim.c

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <netdev.h>
#include "dasa_sim.h"

/* ------------------------------------------------------------------------- */

#undef FPGA_DEBUG

#define	_NOT_USED_	0xFFFFFFFF

/* ------------------------------------------------------------------------- */

/* fpga configuration data - generated by bit2inc */
static unsigned char fpgadata[] = {
#include "fpgadata.c"
};

#define FPGA_PRG_SLEEP         32	/* fpga program sleep-time */
#define LOAD_LONG(a)           a


/******************************************************************************
 *
 * sysFpgaBoot - Load fpga-image into fpga
 *
 */
static int fpgaBoot (void)
{
	int i, j, index, len;
	unsigned char b;
	int imageSize;

	imageSize = sizeof (fpgadata);

	/* display infos on fpgaimage */
	index = 15;
	for (i = 0; i < 4; i++) {
		len = fpgadata[index];
		index += len + 3;
	}

	/* search for preamble 0xFF2X */
	for (index = 0; index < imageSize - 1; index++) {
		if ((fpgadata[index] == 0xff)
			&& ((fpgadata[index + 1] & 0xf0) == 0x20))
			break;
	}

	/* enable cs1 instead of user0... */
	*(unsigned long *) 0x50000084 &= ~0x00000002;

#ifdef FPGA_DEBUG
	printf ("%s\n",
		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
		"NOT DONE" : "DONE");
#endif

	/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
	*(unsigned long *) 0x50000084 &= ~0x00000400;
	udelay (FPGA_PRG_SLEEP * 1000);

	*(unsigned long *) 0x50000084 |= 0x00000400;
	udelay (FPGA_PRG_SLEEP * 1000);

#ifdef FPGA_DEBUG
	printf ("%s\n",
		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
		"NOT DONE" : "DONE");
#endif

	/* cs1: disable burst, disable ready */
	*(unsigned long *) 0x50000114 &= ~0x00000300;

	/* cs1: set write timing */
	*(unsigned long *) 0x50000118 |= 0x00010900;

	/* write configuration-data into fpga... */
	for (i = index; i < imageSize; i++) {
		b = fpgadata[i];
		for (j = 0; j < 8; j++) {
			*(unsigned long *) 0x30000000 =
				((b & 0x80) == 0x80)
				? LOAD_LONG (0x03030101)
				: LOAD_LONG (0x02020000);
			b <<= 1;
		}
	}

#ifdef FPGA_DEBUG
	printf ("%s\n",
		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
		"NOT DONE" : "DONE");
#endif

	/* set cs1 to 32 bit data-width, disable burst, enable ready */
	*(unsigned long *) 0x50000114 |= 0x00000202;
	*(unsigned long *) 0x50000114 &= ~0x00000100;

	/* cs1: set iop access to little endian */
	*(unsigned long *) 0x50000114 &= ~0x00000010;

	/* cs1: set read and write timing */
	*(unsigned long *) 0x50000118 = 0x00010000;
	*(unsigned long *) 0x5000011c = 0x00010001;

#ifdef FPGA_DEBUG
	printf ("%s\n",
		((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
		"NOT DONE" : "DONE");
#endif

	/* wait for 30 ms... */
	udelay (30 * 1000);
	/* check if fpga's DONE signal - correctly booted ? */
	if ((*(unsigned long *) 0x50000084 & 0x00010000) == 0)
		return -1;

	return 0;
}


int board_early_init_f (void)
{
	/*
	 * Init pci regs
	 */
	*(unsigned long *) 0x50000304 = 0x02900007;	/* enable mem/io/master bits */
	*(unsigned long *) 0x500001b4 = 0x00000000;	/* disable pci interrupt output enable */
	*(unsigned long *) 0x50000354 = 0x00c05800;	/* disable emun interrupt output enable */
	*(unsigned long *) 0x50000344 = 0x00000000;	/* disable pme interrupt output enable */
	*(unsigned long *) 0x50000310 = 0x00000000;	/* pcibar0 */
	*(unsigned long *) 0x50000314 = 0x00000000;	/* pcibar1 */
	*(unsigned long *) 0x50000318 = 0x00000000;	/* pcibar2 */

	return 0;
}


/*
 * Check Board Identity:
 */

int checkboard (void)
{
	int index;
	int len;
	char str[64];
	int i = getenv_f("serial#", str, sizeof (str));
	int fpga;
	unsigned short val;

	puts ("Board: ");

	/*
	 * Boot onboard FPGA
	 */
	fpga = fpgaBoot ();

	if (!i || strncmp (str, "DASA_SIM", 8)) {
		puts ("### No HW ID - assuming DASA_SIM");
	}

	puts (str);

	if (fpga == 0) {
		val = *(unsigned short *) 0x30000202;
		printf (" (Id=%d Version=%d Revision=%d)",
			(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);

		puts ("\nFPGA:  ");

		/* display infos on fpgaimage */
		index = 15;
		for (i = 0; i < 4; i++) {
			len = fpgadata[index];
			printf ("%s ", &(fpgadata[index + 1]));
			index += len + 3;
		}
	} else {
		puts ("\nFPGA:  Booting failed!");
	}

	putc ('\n');

	return 0;
}

phys_size_t initdram (int board_type)
{
	return (16 * 1024 * 1024);
}
Commit	Line	Data
16f21704 WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
16f21704 WD	6	*/
	7
	8	#include <common.h>
8ca0b3f9	9	#include <netdev.h>
16f21704 WD	10	#include "dasa_sim.h"
	11
	12	/* ------------------------------------------------------------------------- */
	13
	14	#undef FPGA_DEBUG
	15
	16	#define _NOT_USED_ 0xFFFFFFFF
	17
	18	/* ------------------------------------------------------------------------- */
	19
	20	/* fpga configuration data - generated by bit2inc */
	21	static unsigned char fpgadata[] = {
	22	#include "fpgadata.c"
	23	};
	24
	25	#define FPGA_PRG_SLEEP 32 /* fpga program sleep-time */
	26	#define LOAD_LONG(a) a
	27
	28
	29	/******************************************************************************
	30	*
	31	* sysFpgaBoot - Load fpga-image into fpga
	32	*
	33	*/
	34	static int fpgaBoot (void)
	35	{
	36	int i, j, index, len;
	37	unsigned char b;
	38	int imageSize;
	39
	40	imageSize = sizeof (fpgadata);
	41
	42	/* display infos on fpgaimage */
	43	index = 15;
	44	for (i = 0; i < 4; i++) {
	45	len = fpgadata[index];
	46	index += len + 3;
	47	}
	48
	49	/* search for preamble 0xFF2X */
	50	for (index = 0; index < imageSize - 1; index++) {
	51	if ((fpgadata[index] == 0xff)
	52	&& ((fpgadata[index + 1] & 0xf0) == 0x20))
	53	break;
	54	}
	55
	56	/* enable cs1 instead of user0... */
	57	(unsigned long ) 0x50000084 &= ~0x00000002;
	58
	59	#ifdef FPGA_DEBUG
	60	printf ("%s\n",
049216f0 MF	61	((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
049216f0 MF	62	"NOT DONE" : "DONE");
16f21704 WD	63	#endif
	64
	65	/* init fpga by asserting and deasserting PROGRAM* (USER2)... */
	66	(unsigned long ) 0x50000084 &= ~0x00000400;
	67	udelay (FPGA_PRG_SLEEP * 1000);
	68
	69	(unsigned long ) 0x50000084 \|= 0x00000400;
	70	udelay (FPGA_PRG_SLEEP * 1000);
	71
	72	#ifdef FPGA_DEBUG
	73	printf ("%s\n",
049216f0 MF	74	((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
049216f0 MF	75	"NOT DONE" : "DONE");
16f21704 WD	76	#endif
	77
	78	/* cs1: disable burst, disable ready */
	79	(unsigned long ) 0x50000114 &= ~0x00000300;
	80
	81	/* cs1: set write timing */
	82	(unsigned long ) 0x50000118 \|= 0x00010900;
	83
	84	/* write configuration-data into fpga... */
	85	for (i = index; i < imageSize; i++) {
	86	b = fpgadata[i];
	87	for (j = 0; j < 8; j++) {
	88	(unsigned long ) 0x30000000 =
	89	((b & 0x80) == 0x80)
	90	? LOAD_LONG (0x03030101)
	91	: LOAD_LONG (0x02020000);
	92	b <<= 1;
	93	}
	94	}
	95
	96	#ifdef FPGA_DEBUG
	97	printf ("%s\n",
049216f0 MF	98	((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
049216f0 MF	99	"NOT DONE" : "DONE");
16f21704 WD	100	#endif
	101
	102	/* set cs1 to 32 bit data-width, disable burst, enable ready */
	103	(unsigned long ) 0x50000114 \|= 0x00000202;
	104	(unsigned long ) 0x50000114 &= ~0x00000100;
	105
	106	/* cs1: set iop access to little endian */
	107	(unsigned long ) 0x50000114 &= ~0x00000010;
	108
	109	/* cs1: set read and write timing */
	110	(unsigned long ) 0x50000118 = 0x00010000;
	111	(unsigned long ) 0x5000011c = 0x00010001;
	112
	113	#ifdef FPGA_DEBUG
	114	printf ("%s\n",
049216f0 MF	115	((in_be32 ((void *)0x50000084) & 0x00010000) == 0) ?
049216f0 MF	116	"NOT DONE" : "DONE");
16f21704 WD	117	#endif
	118
	119	/* wait for 30 ms... */
	120	udelay (30 * 1000);
	121	/* check if fpga's DONE signal - correctly booted ? */
	122	if (((unsigned long ) 0x50000084 & 0x00010000) == 0)
	123	return -1;
	124
	125	return 0;
	126	}
	127
	128
c837dcb1	129	int board_early_init_f (void)
16f21704 WD	130	{
	131	/*
	132	* Init pci regs
	133	*/
	134	(unsigned long ) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
	135	(unsigned long ) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
	136	(unsigned long ) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
	137	(unsigned long ) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
	138	(unsigned long ) 0x50000310 = 0x00000000; /* pcibar0 */
	139	(unsigned long ) 0x50000314 = 0x00000000; /* pcibar1 */
	140	(unsigned long ) 0x50000318 = 0x00000000; /* pcibar2 */
	141
	142	return 0;
	143	}
	144
	145
	146	/*
	147	* Check Board Identity:
	148	*/
	149
	150	int checkboard (void)
	151	{
	152	int index;
	153	int len;
77ddac94	154	char str[64];
cdb74977	155	int i = getenv_f("serial#", str, sizeof (str));
16f21704 WD	156	int fpga;
	157	unsigned short val;
	158
	159	puts ("Board: ");
	160
	161	/*
	162	* Boot onboard FPGA
	163	*/
	164	fpga = fpgaBoot ();
	165
	166	if (!i \|\| strncmp (str, "DASA_SIM", 8)) {
	167	puts ("### No HW ID - assuming DASA_SIM");
	168	}
	169
	170	puts (str);
	171
	172	if (fpga == 0) {
	173	val = (unsigned short ) 0x30000202;
	174	printf (" (Id=%d Version=%d Revision=%d)",
	175	(val & 0x07f8) >> 3, val & 0x0001, (val & 0x0006) >> 1);
	176
	177	puts ("\nFPGA: ");
	178
	179	/* display infos on fpgaimage */
	180	index = 15;
	181	for (i = 0; i < 4; i++) {
	182	len = fpgadata[index];
	183	printf ("%s ", &(fpgadata[index + 1]));
	184	index += len + 3;
	185	}
	186	} else {
	187	puts ("\nFPGA: Booting failed!");
	188	}
	189
	190	putc ('\n');
	191
	192	return 0;
	193	}
	194
9973e3c6	195	phys_size_t initdram (int board_type)
16f21704 WD	196	{
	197	return (16 * 1024 * 1024);
	198	}