projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 72c5d52a | 1 | /* |
| 1a459660 | 2 | * SPDX-License-Identifier: GPL-2.0+ |
| 72c5d52a MF |
3 | */ |
| 4 | ||
| 25ddd1fb | 5 | #include <asm-offsets.h> |
| 72c5d52a | 6 | #include <ppc_asm.tmpl> |
| 61f2b38a | 7 | #include <asm/mmu.h> |
| 72c5d52a MF |
8 | #include <config.h> |
| 9 | ||
| 3b4bd2d7 | 10 | /* |
| 72c5d52a MF |
11 | * TLB TABLE |
| 12 | * | |
| 13 | * This table is used by the cpu boot code to setup the initial tlb | |
| 14 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 15 | * this table lets each board set things up however they like. | |
| 16 | * | |
| 17 | * Pointer to the table is returned in r1 | |
| 18 | * | |
| 3b4bd2d7 | 19 | */ |
| 72c5d52a MF |
20 | .section .bootpg,"ax" |
| 21 | .globl tlbtab | |
| 22 | ||
| 23 | tlbtab: | |
| 24 | tlbtab_start | |
| 25 | ||
| 26 | /* | |
| 27 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
| 28 | * speed up boot process. It is patched after relocation to enable SA_I | |
| 29 | */ | |
| cf6eb6da | 30 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) |
| 72c5d52a | 31 | |
| 3b4bd2d7 | 32 | /* TLB entries for DDR2 SDRAM are generated dynamically */ |
| 72c5d52a | 33 | |
| 6d0f6bcf | 34 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
| 72c5d52a | 35 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| cf6eb6da | 36 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
| 72c5d52a MF |
37 | #endif |
| 38 | ||
| 39 | /* TLB-entry for PCI Memory */ | |
| cf6eb6da SR |
40 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) |
| 41 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) | |
| 42 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) | |
| 43 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) | |
| 72c5d52a MF |
44 | |
| 45 | /* TLB-entries for EBC */ | |
| 46 | /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral | |
| 47 | * tlb entry. | |
| 48 | * This dummy entry is only for convinience in order not to modify the | |
| 49 | * amount of entries. Currently OS/9 relies on this :-) | |
| 50 | */ | |
| cf6eb6da | 51 | tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG ) |
| 72c5d52a MF |
52 | |
| 53 | /* TLB-entry for NAND */ | |
| cf6eb6da | 54 | tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG ) |
| 72c5d52a MF |
55 | |
| 56 | /* TLB-entry for Internal Registers & OCM */ | |
| cf6eb6da | 57 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) |
| 72c5d52a MF |
58 | |
| 59 | /*TLB-entry PCI registers*/ | |
| cf6eb6da | 60 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) |
| 72c5d52a MF |
61 | |
| 62 | /* TLB-entry for peripherals */ | |
| cf6eb6da | 63 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) |
| 72c5d52a MF |
64 | |
| 65 | /* TLB-entry PCI IO space */ | |
| cf6eb6da | 66 | tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG) |
| 72c5d52a MF |
67 | |
| 68 | /* TODO: what about high IO space */ | |
| 69 | tlbtab_end |