[people/ms/u-boot.git] / board / freescale / b4860qds / ddr.c

/*
 * Copyright 2011-2012 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <fsl_ddr.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>

DECLARE_GLOBAL_DATA_PTR;

dimm_params_t ddr_raw_timing = {
	.n_ranks = 2,
	.rank_density = 2147483648u,
	.capacity = 4294967296u,
	.primary_sdram_width = 64,
	.ec_sdram_width = 8,
	.registered_dimm = 0,
	.mirrored_dimm = 1,
	.n_row_addr = 15,
	.n_col_addr = 10,
	.n_banks_per_sdram_device = 8,
	.edc_config = 2,	/* ECC */
	.burst_lengths_bitmask = 0x0c,

	.tckmin_x_ps = 1071,
	.caslat_x = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
	.taa_ps = 13910,
	.twr_ps = 15000,
	.trcd_ps = 13910,
	.trrd_ps = 6000,
	.trp_ps = 13910,
	.tras_ps = 34000,
	.trc_ps = 48910,
	.trfc_ps = 260000,
	.twtr_ps = 7500,
	.trtp_ps = 7500,
	.refresh_rate_ps = 7800000,
	.tfaw_ps = 35000,
};

int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
		unsigned int controller_number,
		unsigned int dimm_number)
{
	const char dimm_model[] = "RAW timing DDR";

	if ((controller_number == 0) && (dimm_number == 0)) {
		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
	}

	return 0;
}

struct board_specific_parameters {
	u32 n_ranks;
	u32 datarate_mhz_high;
	u32 clk_adjust;
	u32 wrlvl_start;
	u32 wrlvl_ctl_2;
	u32 wrlvl_ctl_3;
	u32 cpo;
	u32 write_data_delay;
	u32 force_2t;
};

/*
 * This table contains all valid speeds we want to override with board
 * specific parameters. datarate_mhz_high values need to be in ascending order
 * for each n_ranks group.
 */
static const struct board_specific_parameters udimm0[] = {
	/*
	 * memory controller 0
	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
	 */
	{2,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
	{2,  1666,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
	{2,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
	{1,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
	{1,  1700,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
	{1,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
	{}
};

static const struct board_specific_parameters *udimms[] = {
	udimm0,
};

void fsl_ddr_board_options(memctl_options_t *popts,
				dimm_params_t *pdimm,
				unsigned int ctrl_num)
{
	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
	ulong ddr_freq;

	if (ctrl_num > 2) {
		printf("Not supported controller number %d\n", ctrl_num);
		return;
	}
	if (!pdimm->n_ranks)
		return;

	pbsp = udimms[0];


	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
	 * freqency and n_banks specified in board_specific_parameters table.
	 */
	ddr_freq = get_ddr_freq(0) / 1000000;
	while (pbsp->datarate_mhz_high) {
		if (pbsp->n_ranks == pdimm->n_ranks) {
			if (ddr_freq <= pbsp->datarate_mhz_high) {
				popts->cpo_override = pbsp->cpo;
				popts->write_data_delay =
					pbsp->write_data_delay;
				popts->clk_adjust = pbsp->clk_adjust;
				popts->wrlvl_start = pbsp->wrlvl_start;
				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
				popts->twot_en = pbsp->force_2t;
				goto found;
			}
			pbsp_highest = pbsp;
		}
		pbsp++;
	}

	if (pbsp_highest) {
		printf("Error: board specific timing not found "
			"for data rate %lu MT/s\n"
			"Trying to use the highest speed (%u) parameters\n",
			ddr_freq, pbsp_highest->datarate_mhz_high);
		popts->cpo_override = pbsp_highest->cpo;
		popts->write_data_delay = pbsp_highest->write_data_delay;
		popts->clk_adjust = pbsp_highest->clk_adjust;
		popts->wrlvl_start = pbsp_highest->wrlvl_start;
		popts->twot_en = pbsp_highest->force_2t;
	} else {
		panic("DIMM is not supported by this board");
	}
found:
	/*
	 * Factors to consider for half-strength driver enable:
	 *	- number of DIMMs installed
	 */
	popts->half_strength_driver_enable = 0;
	/*
	 * Write leveling override
	 */
	popts->wrlvl_override = 1;
	popts->wrlvl_sample = 0xf;

	/*
	 * Rtt and Rtt_WR override
	 */
	popts->rtt_override = 0;

	/* Enable ZQ calibration */
	popts->zq_en = 1;

	/* DHC_EN =1, ODT = 75 Ohm */
	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);

	/* optimize cpo for erratum A-009942 */
	popts->cpo_sample = 0x3e;
}

phys_size_t initdram(void)
{
	phys_size_t dram_size;

#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
	puts("Initializing....using SPD\n");
	dram_size = fsl_ddr_sdram();
#else
	dram_size =  fsl_ddr_sdram_size();
#endif
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

	return dram_size;
}

unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
			  unsigned int dbw_cap_adj[])
{
	int i, j;
	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
	unsigned long long rank_density, ctlr_density = 0;

	current_mem_base = 0ull;
	total_mem = 0;
	/*
	 * This board has soldered DDR chips. DDRC1 has two rank.
	 * DDRC2 has only one rank.
	 * Assigning DDRC2 to lower address and DDRC1 to higher address.
	 */
	if (pinfo->memctl_opts[0].memctl_interleaving) {
		rank_density = pinfo->dimm_params[0][0].rank_density >>
					dbw_cap_adj[0];
		ctlr_density = rank_density;

		debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
		      rank_density, ctlr_density);
		for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
			switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
			case FSL_DDR_CACHE_LINE_INTERLEAVING:
			case FSL_DDR_PAGE_INTERLEAVING:
			case FSL_DDR_BANK_INTERLEAVING:
			case FSL_DDR_SUPERBANK_INTERLEAVING:
				total_ctlr_mem = 2 * ctlr_density;
				break;
			default:
				panic("Unknown interleaving mode");
			}
			pinfo->common_timing_params[i].base_address =
						current_mem_base;
			pinfo->common_timing_params[i].total_mem =
						total_ctlr_mem;
			total_mem = current_mem_base + total_ctlr_mem;
			debug("ctrl %d base 0x%llx\n", i, current_mem_base);
			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
		}
	} else {
		/*
		 * Simple linear assignment if memory
		 * controllers are not interleaved.
		 */
		for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
			total_ctlr_mem = 0;
			pinfo->common_timing_params[i].base_address =
						current_mem_base;
			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
				/* Compute DIMM base addresses. */
				unsigned long long cap =
					pinfo->dimm_params[i][j].capacity;
				pinfo->dimm_params[i][j].base_address =
					current_mem_base;
				debug("ctrl %d dimm %d base 0x%llx\n",
				      i, j, current_mem_base);
				current_mem_base += cap;
				total_ctlr_mem += cap;
			}
			debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
			pinfo->common_timing_params[i].total_mem =
							total_ctlr_mem;
			total_mem += total_ctlr_mem;
		}
	}
	debug("Total mem by %s is 0x%llx\n", __func__, total_mem);

	return total_mem;
}
Commit	Line	Data
b5b06fb7 YS	1	/*
	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
	3	*
5b8031cc	4	* SPDX-License-Identifier: GPL-2.0
b5b06fb7 YS	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <hwconfig.h>
5614e71b	10	#include <fsl_ddr.h>
b5b06fb7	11	#include <asm/mmu.h>
5614e71b YS	12	#include <fsl_ddr_sdram.h>
5614e71b YS	13	#include <fsl_ddr_dimm_params.h>
b5b06fb7 YS	14	#include <asm/fsl_law.h>
	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	dimm_params_t ddr_raw_timing = {
	19	.n_ranks = 2,
	20	.rank_density = 2147483648u,
	21	.capacity = 4294967296u,
	22	.primary_sdram_width = 64,
	23	.ec_sdram_width = 8,
	24	.registered_dimm = 0,
	25	.mirrored_dimm = 1,
	26	.n_row_addr = 15,
	27	.n_col_addr = 10,
	28	.n_banks_per_sdram_device = 8,
	29	.edc_config = 2, /* ECC */
	30	.burst_lengths_bitmask = 0x0c,
	31
0dd38a35 PJ	32	.tckmin_x_ps = 1071,
	33	.caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
	34	.taa_ps = 13910,
	35	.twr_ps = 15000,
	36	.trcd_ps = 13910,
	37	.trrd_ps = 6000,
	38	.trp_ps = 13910,
	39	.tras_ps = 34000,
	40	.trc_ps = 48910,
	41	.trfc_ps = 260000,
	42	.twtr_ps = 7500,
	43	.trtp_ps = 7500,
b5b06fb7	44	.refresh_rate_ps = 7800000,
0dd38a35	45	.tfaw_ps = 35000,
b5b06fb7 YS	46	};
	47
	48	int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
	49	unsigned int controller_number,
	50	unsigned int dimm_number)
	51	{
	52	const char dimm_model[] = "RAW timing DDR";
	53
	54	if ((controller_number == 0) && (dimm_number == 0)) {
	55	memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
	56	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	57	memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
	58	}
	59
	60	return 0;
	61	}
	62
	63	struct board_specific_parameters {
	64	u32 n_ranks;
	65	u32 datarate_mhz_high;
	66	u32 clk_adjust;
	67	u32 wrlvl_start;
	68	u32 wrlvl_ctl_2;
	69	u32 wrlvl_ctl_3;
	70	u32 cpo;
	71	u32 write_data_delay;
0dd38a35	72	u32 force_2t;
b5b06fb7 YS	73	};
	74
	75	/*
	76	* This table contains all valid speeds we want to override with board
	77	* specific parameters. datarate_mhz_high values need to be in ascending order
	78	* for each n_ranks group.
	79	*/
	80	static const struct board_specific_parameters udimm0[] = {
	81	/*
	82	* memory controller 0
	83	* num\| hi\| clk\| wrlvl \| wrlvl \| wrlvl \| cpo \|wrdata\|2T
	84	* ranks\| mhz\|adjst\| start \| ctl2 \| ctl3 \| \|delay \|
	85	*/
	86	{2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
	87	{2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
	88	{2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
	89	{1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
	90	{1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
	91	{1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
	92	{}
	93	};
	94
	95	static const struct board_specific_parameters *udimms[] = {
	96	udimm0,
	97	};
	98
	99	void fsl_ddr_board_options(memctl_options_t *popts,
	100	dimm_params_t *pdimm,
	101	unsigned int ctrl_num)
	102	{
	103	const struct board_specific_parameters pbsp, pbsp_highest = NULL;
	104	ulong ddr_freq;
	105
	106	if (ctrl_num > 2) {
	107	printf("Not supported controller number %d\n", ctrl_num);
	108	return;
	109	}
	110	if (!pdimm->n_ranks)
	111	return;
	112
	113	pbsp = udimms[0];
	114
	115
	116	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
	117	* freqency and n_banks specified in board_specific_parameters table.
	118	*/
	119	ddr_freq = get_ddr_freq(0) / 1000000;
	120	while (pbsp->datarate_mhz_high) {
	121	if (pbsp->n_ranks == pdimm->n_ranks) {
	122	if (ddr_freq <= pbsp->datarate_mhz_high) {
	123	popts->cpo_override = pbsp->cpo;
	124	popts->write_data_delay =
	125	pbsp->write_data_delay;
	126	popts->clk_adjust = pbsp->clk_adjust;
	127	popts->wrlvl_start = pbsp->wrlvl_start;
	128	popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
	129	popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
0dd38a35	130	popts->twot_en = pbsp->force_2t;
b5b06fb7 YS	131	goto found;
	132	}
	133	pbsp_highest = pbsp;
	134	}
	135	pbsp++;
	136	}
	137
	138	if (pbsp_highest) {
	139	printf("Error: board specific timing not found "
	140	"for data rate %lu MT/s\n"
	141	"Trying to use the highest speed (%u) parameters\n",
	142	ddr_freq, pbsp_highest->datarate_mhz_high);
	143	popts->cpo_override = pbsp_highest->cpo;
	144	popts->write_data_delay = pbsp_highest->write_data_delay;
	145	popts->clk_adjust = pbsp_highest->clk_adjust;
	146	popts->wrlvl_start = pbsp_highest->wrlvl_start;
0dd38a35	147	popts->twot_en = pbsp_highest->force_2t;
b5b06fb7 YS	148	} else {
	149	panic("DIMM is not supported by this board");
	150	}
	151	found:
	152	/*
	153	* Factors to consider for half-strength driver enable:
	154	* - number of DIMMs installed
	155	*/
	156	popts->half_strength_driver_enable = 0;
	157	/*
	158	* Write leveling override
	159	*/
	160	popts->wrlvl_override = 1;
	161	popts->wrlvl_sample = 0xf;
	162
	163	/*
	164	* Rtt and Rtt_WR override
	165	*/
	166	popts->rtt_override = 0;
	167
	168	/* Enable ZQ calibration */
	169	popts->zq_en = 1;
	170
	171	/* DHC_EN =1, ODT = 75 Ohm */
	172	popts->ddr_cdr1 = DDR_CDR1_DHC_EN \| DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
	173	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
90101386 SL	174
	175	/* optimize cpo for erratum A-009942 */
	176	popts->cpo_sample = 0x3e;
b5b06fb7 YS	177	}
b5b06fb7 YS	178
52c41180	179	phys_size_t initdram(void)
b5b06fb7 YS	180	{
	181	phys_size_t dram_size;
	182
c5dfe6ec	183	#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_RAMBOOT_PBL)
b5b06fb7	184	puts("Initializing....using SPD\n");
b5b06fb7	185	dram_size = fsl_ddr_sdram();
c5dfe6ec PK	186	#else
	187	dram_size = fsl_ddr_sdram_size();
	188	#endif
53499282 SL	189	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	190	dram_size *= 0x100000;
	191
b5b06fb7 YS	192	return dram_size;
b5b06fb7 YS	193	}
43104795 YS	194
	195	unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
	196	unsigned int dbw_cap_adj[])
	197	{
	198	int i, j;
	199	unsigned long long total_mem, current_mem_base, total_ctlr_mem;
	200	unsigned long long rank_density, ctlr_density = 0;
	201
	202	current_mem_base = 0ull;
	203	total_mem = 0;
	204	/*
	205	* This board has soldered DDR chips. DDRC1 has two rank.
	206	* DDRC2 has only one rank.
	207	* Assigning DDRC2 to lower address and DDRC1 to higher address.
	208	*/
	209	if (pinfo->memctl_opts[0].memctl_interleaving) {
	210	rank_density = pinfo->dimm_params[0][0].rank_density >>
	211	dbw_cap_adj[0];
	212	ctlr_density = rank_density;
	213
	214	debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
	215	rank_density, ctlr_density);
51370d56	216	for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
43104795 YS	217	switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
	218	case FSL_DDR_CACHE_LINE_INTERLEAVING:
	219	case FSL_DDR_PAGE_INTERLEAVING:
	220	case FSL_DDR_BANK_INTERLEAVING:
	221	case FSL_DDR_SUPERBANK_INTERLEAVING:
	222	total_ctlr_mem = 2 * ctlr_density;
	223	break;
	224	default:
	225	panic("Unknown interleaving mode");
	226	}
	227	pinfo->common_timing_params[i].base_address =
	228	current_mem_base;
	229	pinfo->common_timing_params[i].total_mem =
	230	total_ctlr_mem;
	231	total_mem = current_mem_base + total_ctlr_mem;
	232	debug("ctrl %d base 0x%llx\n", i, current_mem_base);
	233	debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
	234	}
	235	} else {
	236	/*
	237	* Simple linear assignment if memory
	238	* controllers are not interleaved.
	239	*/
51370d56	240	for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
43104795 YS	241	total_ctlr_mem = 0;
	242	pinfo->common_timing_params[i].base_address =
	243	current_mem_base;
	244	for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
	245	/* Compute DIMM base addresses. */
	246	unsigned long long cap =
	247	pinfo->dimm_params[i][j].capacity;
	248	pinfo->dimm_params[i][j].base_address =
	249	current_mem_base;
	250	debug("ctrl %d dimm %d base 0x%llx\n",
	251	i, j, current_mem_base);
	252	current_mem_base += cap;
	253	total_ctlr_mem += cap;
	254	}
	255	debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
	256	pinfo->common_timing_params[i].total_mem =
	257	total_ctlr_mem;
	258	total_mem += total_ctlr_mem;
	259	}
	260	}
	261	debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
	262
	263	return total_mem;
	264	}