]> git.ipfire.org Git - people/ms/u-boot.git/commitdiff
board_f: Drop board_type parameter from initdram()
authorSimon Glass <sjg@chromium.org>
Fri, 31 Mar 2017 14:40:24 +0000 (08:40 -0600)
committerTom Rini <trini@konsulko.com>
Wed, 5 Apr 2017 17:58:44 +0000 (13:58 -0400)
It looks like only cm5200 and tqm8xx use this feature, so we don't really
need it in generic code. Drop it and have the users access gd->board_type
directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
140 files changed:
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
arch/mips/mach-ath79/dram.c
arch/mips/mach-pic32/cpu.c
arch/powerpc/cpu/mpc5xxx/spl_boot.c
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
arch/powerpc/cpu/ppc4xx/sdram.c
arch/powerpc/cpu/ppc4xx/spl_boot.c
board/Arcturus/ucp1020/spl.c
board/BuS/eb_cpu5282/eb_cpu5282.c
board/a3m071/a3m071.c
board/a4m072/a4m072.c
board/amcc/acadia/memory.c
board/amcc/bamboo/bamboo.c
board/amcc/bubinga/bubinga.c
board/amcc/sequoia/sdram.c
board/amcc/walnut/walnut.c
board/amcc/yosemite/yosemite.c
board/astro/mcf5373l/mcf5373l.c
board/canmb/canmb.c
board/cm5200/cm5200.c
board/cobra5272/cobra5272.c
board/davedenx/aria/aria.c
board/dbau1x00/dbau1x00.c
board/esd/mecp5123/mecp5123.c
board/esd/pmc440/sdram.c
board/esd/vme8349/vme8349.c
board/freescale/b4860qds/ddr.c
board/freescale/b4860qds/spl.c
board/freescale/c29xpcie/spl.c
board/freescale/corenet_ds/ddr.c
board/freescale/ls1021aqds/ddr.c
board/freescale/ls1021aqds/ls1021aqds.c
board/freescale/ls1043aqds/ddr.c
board/freescale/ls1043aqds/ls1043aqds.c
board/freescale/ls1043ardb/ddr.c
board/freescale/ls1046aqds/ddr.c
board/freescale/ls1046aqds/ls1046aqds.c
board/freescale/ls1046ardb/ddr.c
board/freescale/ls2080a/ddr.c
board/freescale/ls2080aqds/ddr.c
board/freescale/ls2080ardb/ddr.c
board/freescale/m5208evbe/m5208evbe.c
board/freescale/m52277evb/m52277evb.c
board/freescale/m5235evb/m5235evb.c
board/freescale/m5249evb/m5249evb.c
board/freescale/m5253demo/m5253demo.c
board/freescale/m5253evbe/m5253evbe.c
board/freescale/m5272c3/m5272c3.c
board/freescale/m5275evb/m5275evb.c
board/freescale/m5282evb/m5282evb.c
board/freescale/m53017evb/m53017evb.c
board/freescale/m5329evb/m5329evb.c
board/freescale/m5373evb/m5373evb.c
board/freescale/m54418twr/m54418twr.c
board/freescale/m54451evb/m54451evb.c
board/freescale/m54455evb/m54455evb.c
board/freescale/m547xevb/m547xevb.c
board/freescale/m548xevb/m548xevb.c
board/freescale/mpc5121ads/mpc5121ads.c
board/freescale/mpc8308rdb/sdram.c
board/freescale/mpc8313erdb/mpc8313erdb.c
board/freescale/mpc8313erdb/sdram.c
board/freescale/mpc8315erdb/mpc8315erdb.c
board/freescale/mpc8315erdb/sdram.c
board/freescale/mpc8323erdb/mpc8323erdb.c
board/freescale/mpc832xemds/mpc832xemds.c
board/freescale/mpc8349emds/mpc8349emds.c
board/freescale/mpc8349itx/mpc8349itx.c
board/freescale/mpc837xemds/mpc837xemds.c
board/freescale/mpc837xerdb/mpc837xerdb.c
board/freescale/mpc8610hpcd/mpc8610hpcd.c
board/freescale/mpc8641hpcn/mpc8641hpcn.c
board/freescale/p1010rdb/spl.c
board/freescale/p1022ds/spl.c
board/freescale/p1_p2_rdb_pc/spl.c
board/freescale/p2041rdb/ddr.c
board/freescale/t102xqds/ddr.c
board/freescale/t102xqds/spl.c
board/freescale/t102xrdb/ddr.c
board/freescale/t102xrdb/spl.c
board/freescale/t1040qds/ddr.c
board/freescale/t104xrdb/ddr.c
board/freescale/t104xrdb/spl.c
board/freescale/t208xqds/ddr.c
board/freescale/t208xqds/spl.c
board/freescale/t208xrdb/ddr.c
board/freescale/t208xrdb/spl.c
board/freescale/t4qds/ddr.c
board/freescale/t4qds/spl.c
board/freescale/t4rdb/ddr.c
board/freescale/t4rdb/spl.c
board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c
board/gaisler/gr_ep2s60/gr_ep2s60.c
board/gaisler/gr_xc3s_1500/gr_xc3s_1500.c
board/gaisler/grsim/grsim.c
board/gaisler/grsim_leon2/grsim_leon2.c
board/gdsys/mpc8308/sdram.c
board/ids/ids8313/ids8313.c
board/ifm/ac14xx/ac14xx.c
board/ifm/o2dnt2/o2dnt2.c
board/imgtec/boston/ddr.c
board/imgtec/malta/malta.c
board/imgtec/xilfpga/xilfpga.c
board/inka4x0/inka4x0.c
board/intercontrol/digsy_mtc/digsy_mtc.c
board/ipek01/ipek01.c
board/jupiter/jupiter.c
board/keymile/km82xx/km82xx.c
board/keymile/km83xx/km83xx.c
board/keymile/kmp204x/ddr.c
board/liebherr/lwmon5/sdram.c
board/micronas/vct/vct.c
board/motionpro/motionpro.c
board/mpc8308_p1m/sdram.c
board/mpl/mip405/mip405.c
board/mpl/pati/pati.c
board/mpl/pip405/pip405.c
board/munices/munices.c
board/pb1x00/pb1x00.c
board/pdm360ng/pdm360ng.c
board/phytec/pcm030/pcm030.c
board/qemu-mips/qemu-mips.c
board/sbc8349/sbc8349.c
board/sbc8641d/sbc8641d.c
board/sysam/amcore/amcore.c
board/tqc/tqm5200/tqm5200.c
board/tqc/tqm834x/tqm834x.c
board/tqc/tqm8xx/tqm8xx.c
board/v38b/v38b.c
board/varisys/cyrus/ddr.c
board/ve8313/ve8313.c
board/xes/xpedite1000/xpedite1000.c
board/xes/xpedite517x/xpedite517x.c
board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
common/board_f.c
include/asm-generic/global_data.h
include/common.h

index cebbb0fec5ee054c31fdabf33759819de86cafac..d260e5d62fb47d8c5d403c9091905bd2d19e5a21 100644 (file)
@@ -874,7 +874,7 @@ void update_early_mmu_table(void)
 
 __weak int dram_init(void)
 {
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
        /* This will break-before-make MMU for DDR */
        update_early_mmu_table();
index c29e98c2f4c2e0009fd843c214490d6d3c1b519e..5ef43a059d18483c175fec7538760a88c663f5ad 100644 (file)
@@ -9,7 +9,7 @@
 #include <asm/addrspace.h>
 #include <mach/ddr.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        ddr_tap_tuning();
        return get_ram_size((void *)KSEG1, SZ_256M);
index ac33391921a70b8208642e3ff80a67f7b26c43b5..f15b58d849128061e15fdd8cc95de744807017a3 100644 (file)
@@ -110,7 +110,7 @@ static void ddr2_pmd_ungate(void)
 }
 
 /* initialize the DDR2 Controller and DDR2 PHY */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        ddr2_pmd_ungate();
        ddr2_phy_init();
index e182dfbd45a34cb51d983f2a376c9d110600ae7b..23d201034392a0971368553be233d45b6135f9b8 100644 (file)
@@ -62,7 +62,7 @@ void board_init_f(ulong bootflag)
         * First we need to initialize the SDRAM, so that the real
         * U-Boot or the OS (Linux) can be loaded
         */
-       initdram(0);
+       initdram();
 
        /* Clear bss */
        memset(__bss_start, '\0', __bss_end - __bss_start);
index cc30fa6e176c89ac75bfe306758bc4437633c3a0..192634d41cd7ceef98700d05025f58d989ee5bcd 100644 (file)
@@ -401,7 +401,7 @@ void mpc85xx_reginfo(void)
 #ifndef CONFIG_FSL_CORENET
 #if (defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)) && \
        !defined(CONFIG_SYS_INIT_L2_ADDR)
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
        defined(CONFIG_ARCH_QEMU_E500)
@@ -411,7 +411,7 @@ phys_size_t initdram(int board_type)
 #endif
 }
 #else /* CONFIG_SYS_RAMBOOT */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size = 0;
 
index 7202c3fc46f96d94d091f0ba586b6a2b8e84ee0a..3b79efb24648420b8645f0fec9f4db2c65f6c6a8 100644 (file)
@@ -414,7 +414,7 @@ static unsigned char spd_read(uchar chip, uint addr)
  *              banks appropriately. If Auto Memory Configuration is
  *              not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
        unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
@@ -2855,7 +2855,7 @@ static void test(void)
  *             time parameters.
  *             Configures the PPC405EX(r) and PPC460EX/GT
  *---------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        unsigned long val;
 
index 455136c68cf012c5f70b0ac62b8f5b0ceaaf5144..3b072b7791f66bd3141db6357d466c25fc0fc379 100644 (file)
@@ -998,7 +998,7 @@ static void program_ddr0_44(unsigned long dimm_ranks[],
  *              banks appropriately. If Auto Memory Configuration is
  *              not used, it is assumed that no DIMM is plugged
  *-----------------------------------------------------------------------------*/
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
        unsigned long dimm_ranks[MAXDIMMS];
index cd63456e700a32e5b532115f719638fba6954089..2d805717a7f8fe3238bca32fd3180d7c195438cd 100644 (file)
@@ -148,7 +148,7 @@ static ulong compute_rtr(ulong speed, ulong rows, ulong refresh)
 /*
  * Autodetect onboard SDRAM on 405 platforms
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        ulong speed;
        ulong sdtr1;
@@ -349,7 +349,7 @@ static void sdram_tr1_set(int ram_address, int* tr1_value)
  *      so this should be extended for other future boards
  *      using this routine!
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        int i;
        int tr1_bank1;
index 318f23b6461dd1a7589cdc34cf1d1bbbc649e6ab..f3aa46c4f1fb96fac0a4ccef655d558b5c36b698 100644 (file)
@@ -26,7 +26,7 @@ void board_init_f(ulong bootflag)
         * First we need to initialize the SDRAM, so that the real
         * U-Boot or the OS (Linux) can be loaded
         */
-       initdram(0);
+       initdram();
 
        /* Clear bss */
        memset(__bss_start, '\0', __bss_end - __bss_start);
index 3a775be9ae9eec6128722283607de6e9b4dd820f..8a7fa1d97c96d7e1b9ff6895d4d7f067f1ea91b2 100644 (file)
@@ -110,7 +110,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
        puts("Tertiary program loader running in sram...");
 #else
index b1740ee9b9a3ada0698e245768268e53730c0fc0..292752450d4bc348692383b6cdd0ba4ef899be8e 100644 (file)
@@ -35,7 +35,7 @@ int checkboard (void)
        return 0;
 }
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        int size, i;
 
index 55d0bc80c01c1699987fc8ddaf097d98e564d807..b11ff980b8db816a213a6a8951cc60e75bb2ceee 100644 (file)
@@ -76,7 +76,7 @@ static void sdram_start(int hi_addr)
  * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
index 20d8b80f7efea88818fbbad12f9e50eb346d3aaf..88d4942ce74e6778b8b119e68e96b5f06eb3bac9 100644 (file)
@@ -71,7 +71,7 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
        uint svr, pvr;
index 9673118857b7d06f4ad1b7faee09bafa81c84217..841bcfa4bfd245b5cdac8e5ce7a6f0e33452651d 100644 (file)
@@ -41,7 +41,7 @@ static void cram_bcr_write(u32 wr_val)
        return;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        int i;
        u32 val;
index 2838f9a1edd39ab708c459e15ad020d2ab1b0a49..ae69f5a1b1a0e2b75742e0b083fe31f6fa95b404 100644 (file)
@@ -436,7 +436,7 @@ int checkboard(void)
 }
 
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        return spd_sdram();
 }
index 9043de62d36d8d7c26b9d471850b629494e44ce6..e3567173c2aff865c8f92c9467298ae02d89f49d 100644 (file)
@@ -52,10 +52,10 @@ int checkboard(void)
 }
 
 /* -------------------------------------------------------------------------
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  initdram() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
    ------------------------------------------------------------------------- */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return spd_sdram();
 }
index 67640d7edfbced14bd68e90b56ad777dff6b7ac3..bb5c5ee449534d4547d63b639e553c1a93fbc524 100644 (file)
@@ -31,7 +31,7 @@ extern void denali_core_search_data_eye(void);
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 #if !defined(CONFIG_SYS_RAMBOOT)
        ulong speed = get_bus_freq(0);
index c9482094f6b33898418d3fc423b0cf4fbea389e6..ca933d71a659f5b0bb29008c601231a19cc26527 100644 (file)
@@ -71,10 +71,10 @@ int checkboard(void)
 }
 
 /*
- * initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+ * initdram() reads EEPROM via I2c. EEPROM contains all of
  * the necessary info for SDRAM controller configuration
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return spd_sdram();
 }
index 56b5191d6667187467e6b6ba789577b63891b6f3..f61978c5d5ebc7d484ed16d24bdbd5d79495fd30 100644 (file)
@@ -286,7 +286,7 @@ void sdram_tr1_set(int ram_address, int* tr1_value)
        *tr1_value = (first_good + last_bad) / 2;
 }
 
-phys_size_t initdram(int board)
+phys_size_t initdram(void)
 {
        register uint reg;
        int tr1_bank1, tr1_bank2;
index 7ec7cb378f561fc936a8821715e15db1c35ddcc0..70fcd619980e454388fbb67af674f109915d9054 100644 (file)
@@ -27,7 +27,7 @@ int checkboard(void)
        return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
        sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
index 15c934d29b25062509c43ae73880501d93c5e0b2..ba9930d370030130c9d33ba5d334f96f09175571 100644 (file)
@@ -65,7 +65,7 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
index fce998d00fca66da463763e471e63f84425cca47..2ac9fd9cd13692499c1cba2e764340ed30513b95 100644 (file)
@@ -97,14 +97,14 @@ static mem_conf_t* get_mem_config(int board_type)
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
 #ifndef CONFIG_SYS_RAMBOOT
        ulong test1, test2;
        mem_conf_t *mem_conf;
 
-       mem_conf = get_mem_config(board_type);
+       mem_conf = get_mem_config(gd->board_type);
 
        /* configure SDRAM start/end for detection */
        *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
index 0f3bcc592a5ff60d1f6f78ac1f43f8cac404093c..9d4554da1fe5099838e82aeead5d63893de5f532 100644 (file)
@@ -16,7 +16,7 @@ int checkboard (void)
        return 0;
 };
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        volatile sdramctrl_t *sdp = (sdramctrl_t *) (MMAP_SDRAM);
 
index 1b6c40f8d518ccbd167e0551f72e68f6e8817463..709c65ba0d626c1465784900f5199b6b488371c2 100644 (file)
@@ -18,7 +18,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        return fixed_sdram(NULL, NULL, 0);
 }
index 75e6f0ef5adeb6a82d97ffc204eb6aac11181dc7..cf2f88047d486011096c23a60a1f14ed4597417a 100644 (file)
@@ -11,7 +11,7 @@
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        /* Sdram is setup by assembler code */
        /* If memory could be changed, we should return the true value here */
index 656f0fa83fbf72161be4a030c39aba6d43be69cb..b8eb32b1fb713f7fa7338ad35dfaf59e6cc1b6fa 100644 (file)
@@ -62,7 +62,7 @@ int board_early_init_f(void)
        return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
 }
index e7f8115870377f158341632a4895b9256bc5a1f0..82ee289aa61c11b8b1b3822a454559c692e6f731 100644 (file)
@@ -105,7 +105,7 @@ int initdram_by_rb(int rows, int banks)
        return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t size;
        int n;
index f8f1834b59c119a1669fd453ef1eb2360a798a25..bf6ee7a73dc8fa732e7b3600ac50311dcfa48d4d 100644 (file)
@@ -28,7 +28,7 @@
 
 void ddr_enable_ecc(unsigned int dram_size);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize = 0;
index 99cd88466d9420890039e02a9a5aa96048886ff4..d070104618af5bbcc6f236f890c6602b50de9197 100644 (file)
@@ -176,7 +176,7 @@ found:
        popts->cpo_sample = 0x3e;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 35b812cb1843ec90611b27ee7a94ad37d1d51fe8..17e2ba8953d6f5f2763183cd0ea308637d7b761a 100644 (file)
@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        puts("\n\n");
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_NAND_BOOT
        nand_boot();
index 6613216950aaa35e3cb874cf105a11e7efdb422f..785c859beedeacebd4bc241f78f02a688f2e86e1 100644 (file)
@@ -67,7 +67,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        i2c_init_all();
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_NAND_BOOT
        puts("TPL\n");
index 9c1a4c2f7ce09093183341c1a02cb7117fc95d8e..75de247a51e6ff76d51643aa1bd239abc8d4cbdf 100644 (file)
@@ -260,7 +260,7 @@ found:
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 2f66ba9e7f8c0c1f5f8808638fe8b87329737a03..99a4984fbcf9f8e670590cc3bf20eac3a566d63d 100644 (file)
@@ -164,7 +164,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 79078d237b44731ecf8b49efe4459c10fa002df8..57314e2c9fd8c2b30a06d486edf902422daa6b9f 100644 (file)
@@ -162,7 +162,7 @@ int dram_init(void)
         * before accessing DDR SPD.
         */
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
        return 0;
 }
index c74006288700aad4784ad6feccbb44a01230aa1e..817c91a34af2a42469bb1cccacf482ae89d89165 100644 (file)
@@ -108,7 +108,7 @@ found:
 #endif
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 6507c0914342de4a99ddd33af787e5143eee6ad7..755aef384e72861477232a23364ff49ba58c80ca 100644 (file)
@@ -153,7 +153,7 @@ int dram_init(void)
         * before accessing DDR SPD.
         */
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
        /* This will break-before-make MMU for DDR */
        update_early_mmu_table();
index f90b85df1a041775144e2ebff8f64ff8f9c992c1..b5c5b2ede3819df54f0690fc75ca9677285cd655 100644 (file)
@@ -170,7 +170,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index dc4d689adc1286288c97e8002c79a429a0917b5d..6a5cbbf7394b613c44bae903dff324e192f9fb45 100644 (file)
@@ -92,7 +92,7 @@ found:
        popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index af3f70a38b70089177632b0c6c15a7d5d9cb7fde..f30dd233519cb88412aea37d38e3e8370f4999c2 100644 (file)
@@ -149,7 +149,7 @@ int dram_init(void)
         * before accessing DDR SPD.
         */
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
        /* This will break-before-make MMU for DDR */
        update_early_mmu_table();
index efe2ba6eb1b213dc3a17fdf5919c3d4f1ef9aa22..1e995380220899f95b1be0686712d615e14f0c6b 100644 (file)
@@ -96,7 +96,7 @@ found:
        popts->cpo_sample = 0x70;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 5ed9e1461b06c89f4d6fc9f14734ac8615b0b882..0bff922f07ea1b72ac732cd6f80949e737b87a8f 100644 (file)
@@ -158,7 +158,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
        return 0;
 }
 #endif
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 0408c0fc251b0ea6024d8b0ec261cc21bbbae7d3..bd32c54fc15be96f69edb403a2239135fef79138 100644 (file)
@@ -155,7 +155,7 @@ found:
        }
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 2851d5b44385494f2474e25e2d648b3d849eb4d0..b00e575ea29db03ddfbbe8c83c357abc85e4f37e 100644 (file)
@@ -158,7 +158,7 @@ found:
        }
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 1df128b2689ec44c315015c756833a93e3e392ae..612275088232426b6ab52258e84b2fea11a88a97 100644 (file)
@@ -22,7 +22,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
        u32 dramsize, i;
index a1127e52a39d56887bd85f3b8d88ce7a02d65d86..571e1a6528aecb91d17dc867026b276318efece4 100644 (file)
@@ -21,7 +21,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        u32 dramsize;
 
index 68c1631f81dae447ffd552c8138ed6e4ad730002..7aa0edfdc1958619dccf3ed3bf6aadc37491133e 100644 (file)
@@ -22,7 +22,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
        gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
index 7ae842c3d3c6770c1d464c539ed695808af26429..b8544292a7474cf5f5965aba3bdc85076fb10f66 100644 (file)
@@ -29,7 +29,8 @@ int checkboard (void) {
 };
 
 
-phys_size_t initdram (int board_type) {
+phys_size_t initdram(void)
+{
        unsigned long   junk = 0xa5a59696;
 
        /*
index 7e516bfa4079862e1c60f66d099bbb608a563003..fef2ca6af6d45ab12c73ac6cb420a89b617b2418 100644 (file)
@@ -20,7 +20,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        u32 dramsize = 0;
 
index 15ff755a56d1e6fcbe1492a73e7be537def3b4cc..3f4cdfbaf1418151126f4a9de86cd6afb735271d 100644 (file)
@@ -19,7 +19,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        /*
         * Check to see if the SDRAM has already been initialized
index 3ed4a7da9300e1b681027317a4cd7868be41f744..9fab24ebb9de422fed009e7ef1153c13700064de 100644 (file)
@@ -18,7 +18,8 @@ int checkboard (void) {
        return 0;
        };
 
-phys_size_t initdram (int board_type) {
+phys_size_t initdram(void)
+{
        sdramctrl_t * sdp = (sdramctrl_t *)(MMAP_SDRAM);
 
        out_be16(&sdp->sdram_sdtr, 0xf539);
index 16083d1bc0ef5c74681a07b010c65164e6d35821..00ce582249811b783ac5618ef1467345f03349b5 100644 (file)
@@ -23,7 +23,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
        gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
index 39f12fb4aa2db5b3812933aab4a751161eb3e124..19e56957bdda4e55f7b878e8b385c0229a7ecab2 100644 (file)
@@ -16,7 +16,7 @@ int checkboard (void)
        return 0;
 }
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        u32 dramsize, i, dramclk;
 
index dbe886b03ad837464f1ba2ec37b582d0c681e563..821e663b914d09a19b1b59011846615d49513502 100644 (file)
@@ -22,7 +22,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
        u32 dramsize, i;
index 1f77adf4c22a3001004edf70bbb3fa32b2cd6f6f..c4613a4cbda2e9e68272ff5f91aa5ac0fab14593 100644 (file)
@@ -22,7 +22,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
        u32 dramsize, i;
index bfcc4b23b00e0d686e1a57078d07bcb1cc95d878..f1ddee1378679e2bd506c2523f10c503a7ba3da6 100644 (file)
@@ -22,7 +22,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
        u32 dramsize, i;
index 5375d1675dfdd9472d3cae766e05fb0cf006912d..c3bee185d875543173f8ec180008ebfc8ff56e62 100644 (file)
@@ -25,7 +25,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        u32 dramsize;
 
index d2ad42c085fe6864b050d08023f2a6971e8ab1da..a4d11b6815e1661d50d8d8f5b9df5e264542567d 100644 (file)
@@ -26,7 +26,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        u32 dramsize;
 #ifdef CONFIG_CF_SBF
index 76b4322a1976a8cb9ada409297db9b06104a9297..3bdcc332b6c3302fcadf4e7986c88cb755a1ad87 100644 (file)
@@ -22,7 +22,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        u32 dramsize;
 #ifdef CONFIG_CF_SBF
index 1e3cb6179f4da90be70cecf4ede8477600109bbf..e84a5ac4eb94e4a2de129f5cbe0369e56549f87e 100644 (file)
@@ -23,7 +23,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        siu_t *siu = (siu_t *) (MMAP_SIU);
        sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
index 05361550b35d394970a5785741d5a294747b1efb..06f9a5ede032d2927fb938e1e266ea6a0f06becb 100644 (file)
@@ -23,7 +23,7 @@ int checkboard(void)
        return 0;
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        siu_t *siu = (siu_t *) (MMAP_SIU);
        sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
index 7c44282ca2f9426f857ea58f27870a08a300e4fd..e134091468b42debe3879018af9feb6af599ac39 100644 (file)
@@ -95,7 +95,7 @@ int is_micron(void){
        return(ismicron);
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        u32 msize = 0;
        /*
index 89b665e649c5abc67e99159af65a3b308bbe3bea..ed1e84e0033955261fd8b3ffb163b2d75aaba866 100644 (file)
@@ -65,7 +65,7 @@ static long fixed_sdram(void)
        return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize;
index 693dff651a554cd2b0829dec7cadce471939e9bc..e3a5941f20feac7df0dbbc0a606d418d72b1942f 100644 (file)
@@ -134,7 +134,7 @@ void board_init_f(ulong bootflag)
                     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
        puts("NAND boot... ");
        timer_init();
-       initdram(0);
+       initdram();
        relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
                      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
index 6282c3d920e5071d5d3c5108e3ea6a49627f8273..ce6fce539987addd8a28fa8bc1c3102ecfbf3b2c 100644 (file)
@@ -97,7 +97,7 @@ static long fixed_sdram(void)
        return msize;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
        volatile fsl_lbc_t *lbc = &im->im_lbc;
index 1da6e2166d230f37e449e02ba2ce2749a1aff186..7779b6daed258a52c962b181f0f4f554d1225d81 100644 (file)
@@ -222,7 +222,7 @@ void board_init_f(ulong bootflag)
                     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
        puts("NAND boot... ");
        timer_init();
-       initdram(0);
+       initdram();
        relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
                      CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
index 6c9431202f8cf47f416aefa31ec83d7369714e0e..fd8968c71cb08f763141ad64c5a8713e105e9ac2 100644 (file)
@@ -92,7 +92,7 @@ static long fixed_sdram(void)
 }
 #endif /* CONFIG_SYS_RAMBOOT */
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
        u32 msize;
index 0a0152ad9ea30969d8c4de54c5fcbe2a495a1c8a..f9f9a410c53f8a1fa9fc6dc98e910df08582a0f9 100644 (file)
@@ -68,7 +68,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
        u32 msize = 0;
index adf425486e1edb92e9ccc89a84d245c413fffa51..d66ad33bf5e70598a5d9eeaa0f3162ce4df90568 100644 (file)
@@ -88,7 +88,7 @@ int board_early_init_r(void)
 
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
        u32 msize = 0;
index 02b5040ef4af177b18f3421bd709e14b3fb48c3f..3bcfe03065b3715ecd52f91958df0369ae725ebc 100644 (file)
@@ -46,7 +46,7 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        phys_size_t msize = 0;
index 22a1d99c8846ae6bb2115b994f1c90711cd2ed2b..01eac0260fa840b4aa1ce779dfcbc8b045723987 100644 (file)
@@ -116,7 +116,7 @@ volatile static struct pci_controller hose[] = {
 };
 #endif                         /* CONFIG_PCI */
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
        u32 msize = 0;
index 045841d57ba1c6206658aa1d045d79b27d884227..0463940baebc109838701d0909a0f424a9fd8013 100644 (file)
@@ -216,7 +216,7 @@ extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
        u32 msize = 0;
index 07c0599858444fcc68e53a942c5e874eb311f17a..d81778549c482e60e70fc1fa306f897068557ad1 100644 (file)
@@ -60,7 +60,7 @@ void ddr_enable_ecc(unsigned int dram_size);
 #endif
 int fixed_sdram(void);
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
        u32 msize = 0;
index 95e398c9f4958d540026648638c2de16029e7c44..7668226321d0583274c60985e57dd74b0e3238dc 100644 (file)
@@ -116,8 +116,7 @@ int checkboard(void)
 }
 
 
-phys_size_t
-initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size = 0;
 
index 94633b5c99dcc38334c939e24524d14ea1b4ed14..10764425169683bba916f2b5700c9365e1dc7047 100644 (file)
@@ -37,8 +37,7 @@ int checkboard(void)
        return 0;
 }
 
-phys_size_t
-initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size = 0;
 
index 05c76f2e45c08aefd5c9e3211b9fecc219d32464..05da1dac7d550cd9c06f251251845eb217c87a19 100644 (file)
@@ -94,7 +94,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        i2c_init_all();
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
        puts("\nTertiary program loader running in sram...");
 #else
index ef385516005f09fe3b6450f50d47898b6a812838..77ed2577f990410232b46113457f77e4c26f4e4f 100644 (file)
@@ -111,7 +111,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
        puts("Tertiary program loader running in sram...");
 #else
index 2af5576ff72ba9473f7025357eec99be25340a6f..3357702dbabb5fcb00d8c5210ee28ede2ad96b44 100644 (file)
@@ -108,7 +108,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
        i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 #ifdef CONFIG_SPL_NAND_BOOT
        puts("Tertiary program loader running in sram...");
 #else
index b2493e1f618881bea54d771bd73a1710bf7ad40f..b07bd98fb176b97e136b09bc2dc3736068ee7481 100644 (file)
@@ -116,7 +116,7 @@ found:
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size = 0;
 
index b6b11919906fd4543c2cceba0cad5dab25669f45..507929bb707685f537776ede2d70ddc9af80cd24 100644 (file)
@@ -169,7 +169,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 3e96b33c40d82ea561ae439122fc3700d6d257df..a1481e9b630d0fb081bbca1c761c2fa518d601fd 100644 (file)
@@ -142,7 +142,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        i2c_init_all();
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
        mmc_boot();
index e66657869c206706664af8a81834e459db8fe4a3..56f98ac2f9f34ccdfa059999377992d411c34811 100644 (file)
@@ -229,7 +229,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index b70c2c5d7910b8aa5f8d7a4e96ea382d9b4dc09f..f70a337512bb814f8b33abb3b9cf7ee0acb6a539 100644 (file)
@@ -129,7 +129,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        i2c_init_all();
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
        mmc_boot();
index cb58d1e5245b8bb5f4445e2006cbfd9211557a5c..a5d3e54cfe810d6f2f89ac5a7358ae4b658f9ca9 100644 (file)
@@ -117,7 +117,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 302f19be698597115024c4c3e2c984aafd358b9d..4a09cae782c53d60bb612a7ef4418dca8a3dfcdc 100644 (file)
@@ -120,7 +120,7 @@ void board_mem_sleep_setup(void)
 }
 #endif
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 4402e0f4b049d3d03421ab4be3cadd18fd15dae4..076641c1ec437c77d2db314dcefc3c584e49a327 100644 (file)
@@ -125,7 +125,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        puts("\n\n");
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
        mmc_boot();
index d6e4554a807ad051309033f0de792d7faf872781..044ac18562a27eba64e5f3f2b7a57f805a6bf774 100644 (file)
@@ -104,7 +104,7 @@ found:
        popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 334f5083b8edb8167809599e32e81d95dafeb687..caa4de3e7f8be3b64afb2f527b28e709e8a2a1d3 100644 (file)
@@ -128,7 +128,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        i2c_init_all();
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
        mmc_boot();
index 3487261b9d8d0de44af54579ad523fd2e2ed697a..bcb536ae1bf8526f1bc2663963b2c6edebee1f0f 100644 (file)
@@ -97,7 +97,7 @@ found:
        popts->cpo_sample = 0x54;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index aa8e9285fefe595cebafd5d5b1d369517b6b08ba..44be70be87d1981d9c4b92a8ba7234d1e5d40c59 100644 (file)
@@ -98,7 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        i2c_init_all();
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
        mmc_boot();
index 842073b6c6b9240912099d2be7fdf387b1ec9da0..24b187256041207f7b0f9aef36598c94d1c132ab 100644 (file)
@@ -112,7 +112,7 @@ found:
        popts->cpo_sample = 0x63;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 5e946dc84f6263746319fa5b9af986f1aaa10865..bda0003565de8bf6c8ed45a68a5d7f60323b3c12 100644 (file)
@@ -133,7 +133,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        i2c_init_all();
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
 #ifdef CONFIG_SPL_MMC_BOOT
        mmc_boot();
index 7b05821cf792a84c8ff9f8decd69ba6132f109f3..8596ccde1b5ff28f6242f55a7720564ca607ba67 100644 (file)
@@ -105,7 +105,7 @@ found:
        popts->cpo_sample = 0x64;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index a32e34ef96c2a445b74cb96516c2bbc92e27484b..d3a86e6599dd8fba269205259f4e75fde918f4a1 100644 (file)
@@ -91,7 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
        i2c_init_all();
 
-       gd->ram_size = initdram(0);
+       gd->ram_size = initdram();
 
        mmc_boot();
 }
index d26212ea82e23454a081d785344e2a5c4f9ef784..ecdc7e72d336b62e10f9e05f2205b77a7c38011e 100644 (file)
@@ -10,7 +10,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return 1;
 }
index 98fb45fdb8203c17b57ce9a5f65940e50d141704..66fe5a53b04d6f6cb43645ac4e3118dd6ba69de3 100644 (file)
@@ -10,7 +10,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return 1;
 }
index 32fbbe2d7555ca22b17216d01622079075a39e80..1725459af8ff5d425a78e7301d8c90d6d5073f1d 100644 (file)
@@ -9,7 +9,7 @@
 #include <config.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return 1;
 }
index fd73920b62d3ab51f33861df1711224c3d2b63e0..fa097377df06289cb3bc7bcc6bee15626c8ad628 100644 (file)
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return 1;
 }
index 882b0a4247e164d0f5c1da087572563d51ae4b96..12df6bd7efa6c499015fc0300db3a7bed98a7a31 100644 (file)
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/leon.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return 1;
 }
index 0fce8cfbab6002c967bd4b1e72d4f41ac60fd7e6..b7b31fb0242fe7eaf6b591a2fc752e32f131120f 100644 (file)
@@ -66,7 +66,7 @@ static long fixed_sdram(void)
        return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize;
index e7838dcd2a6e73e3c1af7318e78d72129f6c8c34..b40e4b30e8752fe0e41db62d93c229577eb4e36a 100644 (file)
@@ -119,7 +119,7 @@ static int setup_sdram(void)
        return msize;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        fsl_lbc_t *lbc = &im->im_lbc;
index 75bf1bb33cb60451e3075cb9a65e17e6fa3b758d..b107dd196cc14c3e7f22cb0803d27a6d67bb3e26 100644 (file)
@@ -310,7 +310,7 @@ u32 sdram_init_seq[] = {
        /* EMPTY, optional, we don't do it */
 };
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
 }
index 4fc6809ad612bc1b03a12b524e0092a80e0bd323..7452d2b1f0ec116c3c9d55662b304057c17012bd 100644 (file)
@@ -66,7 +66,7 @@ static void sdram_start(int hi_addr)
  *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        struct mpc5xxx_mmap_ctl *mmap_ctl =
                (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
index ceffef61efb39f665437339fec0a208f14bfa322..c841bf02a322a5e00aa1e3af5b249f1b61d8b7f9 100644 (file)
@@ -10,7 +10,7 @@
 
 #include "boston-regs.h"
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0);
 
index 495504372a021831be75d4c8a6a7f55d74a0216a..c269d0a5a35d7ffe905e8c5dcd8b46431d75afd2 100644 (file)
@@ -83,7 +83,7 @@ static enum sys_con malta_sys_con(void)
        }
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return CONFIG_SYS_MEM_SIZE;
 }
index 77a1952c93ca9c6177b8c5e0493b35394a29af3c..dc0a088ecb8bb37d83c8143dce7042d8fc2b72f9 100644 (file)
@@ -12,7 +12,7 @@
 #include <common.h>
 
 /* initialize the DDR Controller and PHY */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        /* MIG IP block is smart and doesn't need SW
         * to do any init */
index 0a32f0e1b9e5a1065a4a8f983f04d54468bd6ece..47c3955c6d8b641b68647f48462e18a1986ca350 100644 (file)
@@ -77,7 +77,7 @@ static void sdram_start (int hi_addr)
  *           is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        volatile struct mpc5xxx_mmap_ctl *mm =
                (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
index 05d673dc89b3265dbd3c4fad8d89f5dce0d115c5..9bada940b7d545ccc07624085d7c2f71ec406f32 100644 (file)
@@ -79,7 +79,7 @@ static void sdram_start(int hi_addr)
  *            CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
  */
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
index 2e62355c48384259399879464c221d7219cca136..ab94c654994c938e84a2d4f665dbae4ec884bd22 100644 (file)
@@ -80,7 +80,7 @@ static void sdram_start (int hi_addr)
  *           CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        struct mpc5xxx_mmap_ctl *mmap_ctl =
                (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
index d56902bcd23c151e4cb5ac0ba52d621a76adc960..ae569d0fc004e1aafcd8a7ae5ef06daa5e8bc1c9 100644 (file)
@@ -76,7 +76,7 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
index c2a7a5f99577fe18196c7cf3277888842aa8d10d..12fd05d2f476190e28ed3b1d205845a36fd68530 100644 (file)
@@ -289,7 +289,7 @@ static long probe_sdram(memctl8260_t *memctl)
 #endif /* CONFIG_SYS_SDRAM_LIST */
 
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        memctl8260_t *memctl = &immap->im_memctl;
index 154f97457b4d368235f3b242f07d2a0dde3c9f04..111a8a7995215e3b145b675f28c5b3aea8bb3cdb 100644 (file)
@@ -328,7 +328,7 @@ static int fixed_sdram(void)
        return msize;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize = 0;
index 77af184c82b5effc4863f8d10618db849501ab38..98fb1adfdd7ba4b6aef8e1eea7bbc01551c8b165 100644 (file)
@@ -48,7 +48,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size = 0;
 
index bcb344940bde9ec8de5476b67011f1c5b5d1c69a..1932e06fd61ae57acaf0511a67223d37a50dd4f3 100644 (file)
@@ -145,7 +145,7 @@ static void program_ecc(u32 start_address,
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        /* CL=4 */
        mtsdram(DDR0_02, 0x00000000);
index 0745ceeb7f785c39f77205543c49390e82c6d86b..f4a6521e94480463a0bb4c7c765e73e31874241e 100644 (file)
@@ -59,7 +59,7 @@ void _machine_restart(void)
  * SDRAM is already configured by the bootstrap code, only return the
  * auto-detected size here
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
                            CONFIG_SYS_MBYTES_SDRAM << 20);
index 7fa81b8677a34e111c1fa21997a2fee4793c8ea0..3e2fe653bd2758339bfac130eb8b32defb439485 100644 (file)
@@ -116,7 +116,7 @@ static void sdram_start(int hi_addr)
 /*
  * Initalize SDRAM - configure SDRAM controller, detect memory size.
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
 #ifndef CONFIG_SYS_RAMBOOT
index da36f63fdd29ca4877cfc1db4904ccec5b59c1c2..96d60c95eefca9091ec29eff325b81be57b6b982 100644 (file)
@@ -61,7 +61,7 @@ static long fixed_sdram(void)
        return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize;
index 8b9892b868b2ed74106434df081d71954d83ed9b..e2961d1d4acb2f8bb797058aeb9aec77fb203ee1 100644 (file)
@@ -615,14 +615,14 @@ int checkboard (void)
 /* ------------------------------------------------------------------------- */
 /* ------------------------------------------------------------------------- */
 /*
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  initdram() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
 */
 /* ------------------------------------------------------------------------- */
 /* ------------------------------------------------------------------------- */
 static int test_dram (unsigned long ramsize);
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
 
        unsigned long bank_reg[4], tmp, bank_size;
index ddc21083d84404379a036a12669c525a765e79a0..951010a6a3d7bc40ad60843898a92800e7ef00dd 100644 (file)
@@ -133,7 +133,7 @@ extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
 /*
  * Get RAM size.
  */
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        unsigned char board_rev;
        unsigned long reg;
index 1bd2fbfc58513adbb96bebd33bd4ca601e34add5..07b30ed293a8605ae24edf607310bfbb1f363e0e 100644 (file)
@@ -605,14 +605,14 @@ int checkboard (void)
 /* ------------------------------------------------------------------------- */
 /* ------------------------------------------------------------------------- */
 /*
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
+  initdram() reads EEPROM via I2c. EEPROM contains all of
   the necessary info for SDRAM controller configuration
 */
 /* ------------------------------------------------------------------------- */
 /* ------------------------------------------------------------------------- */
 static int test_dram (unsigned long ramsize);
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        unsigned long bank_reg[4], tmp, bank_size;
        int i, ds;
index 8f292ea8e2b23f870f0463e9b585657ba098a09c..b88160c8a84449800c4bcab73b70f2d83c53bc95 100644 (file)
@@ -58,7 +58,7 @@ static void sdram_start (int hi_addr)
  *            is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
index eb92914a7986ef014c03896e5bcfbb2bc40ae495..baa5723f4abcf3ce841fa135b4fa29ef5cd4fa5e 100644 (file)
@@ -11,7 +11,7 @@
 #include <asm/mipsregs.h>
 #include <asm/io.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        /* Sdram is setup by assembler code */
        /* If memory could be changed, we should return the true value here */
index d91d427c6bba87b09d815197c67483aaedb7338e..ef19daf3c953de29d290218be5370eb2863ecefc 100644 (file)
@@ -48,7 +48,7 @@ sdram_conf_t mddrc_config[] = {
        },
 };
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        int i;
        u32 msize = 0;
index 8a9de0d963d7cb5e7ed6f84988260c194e86bc09..470bd7079261f594d125470150fc66d534d3c925 100644 (file)
@@ -73,7 +73,7 @@ static void sdram_start(int hi_addr)
  *     is something else than 0x00000000.
  */
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile struct mpc5xxx_mmap_ctl *mm =
                (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
index 563044eb0c4184391c318039c898b931160b2cf7..3cdc91cf4338cd49d8f26c479388f914ee2553a9 100644 (file)
@@ -11,7 +11,7 @@
 #include <asm/io.h>
 #include <netdev.h>
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        /* Sdram is setup by assembler code */
        /* If memory could be changed, we should return the true value here */
index 72786d2ace6516f9ebe251f3bf1371c9107ad00b..b20de4c3c3da51a5a3f18001db86c3e7a7238dd1 100644 (file)
@@ -35,7 +35,7 @@ int board_early_init_f (void)
 
 #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
        u32 msize = 0;
index 6bdf1a28e97bbea16eff991718df3bad378b0c98..a541d25cc384491c367c21d9523927680e1bd8a7 100644 (file)
@@ -37,7 +37,7 @@ int checkboard (void)
        return 0;
 }
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        long dram_size = 0;
 
index 77b5000de6719fdd066fd0575168224b1712294f..b7f6380bec501b56ee999c6edcc03323ca4f9862 100644 (file)
@@ -49,7 +49,7 @@ void fudelay(int usec)
                asm volatile ("nop");
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        u32 dramsize, RC;
 
index fef9d2b29a94290b4d3f47fc9af8d8de6b858ab7..1e843d5b03be86da9e596839ac493bd282daf434 100644 (file)
@@ -133,7 +133,7 @@ static void sdram_start (int hi_addr)
  *           is something else than 0x00000000.
  */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
index eca218c9cf003d8bb95f31678e303dba6c1ae11a..a05ae2a170e002f1f20cc3fe8be1c6241cd5873e 100644 (file)
@@ -66,7 +66,7 @@ int board_early_init_r (void) {
 /**************************************************************************
  * DRAM initalization and size detection
  */
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        long bank_size;
        long size;
index 6d17830575f404e852d4b174269f802a8d0ddf50..99357302f62f90af1c21cd0a0ace5ec46a007f4c 100644 (file)
@@ -126,13 +126,14 @@ int checkboard (void)
 
 /* ------------------------------------------------------------------------- */
 
-phys_size_t initdram (int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
        long int size8, size9, size10;
        long int size_b0 = 0;
        long int size_b1 = 0;
+       int board_type = gd->board_type;
 
        upmconfig (UPMA, (uint *) sdram_table,
                           sizeof (sdram_table) / sizeof (uint));
index a3377299162e44683ab241f4a4698d10fa5b97b9..20490a31570efa9aa97228134cb7ea4b4161a633 100644 (file)
@@ -56,7 +56,7 @@ static void sdram_start(int hi_addr)
 #endif /* !CONFIG_SYS_RAMBOOT */
 
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        ulong dramsize = 0;
        ulong dramsize2 = 0;
index bb1d29a94cdd6cc275bbd307db78170b32e59427..da6f5ad253007dbe413138ff54db7ef35e7e0a27 100644 (file)
@@ -168,7 +168,7 @@ found:
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size;
 
index 7f24a30688ac2468b1048deae5854502ec736b3d..5349a583fc9a8eff057b02c2f7ef37cd79c181eb 100644 (file)
@@ -88,7 +88,7 @@ static long fixed_sdram(void)
        return msize;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
        volatile fsl_lbc_t *lbc = &im->im_lbc;
index 3b8a6683ebbd188ef39eeca4280f08c88f2672c5..ff64483cf4f54222bf9fe15fa2e0f3b7d04f2553 100644 (file)
@@ -116,7 +116,7 @@ int checkboard(void)
        return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return spd_sdram();
 }
index 0028870db07784a6e417cd4f39b305cbecf33dc2..9ec99a1e28f565f54071fb7186397224566f84e5 100644 (file)
@@ -56,7 +56,7 @@ int board_early_init_r(void)
        return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        phys_size_t dram_size = fsl_ddr_sdram();
 
index 3729f07624a3420b2fc733e30363a5f3fe58f410..dfdd3f23103a4617ee44428f1f73832dd2255534 100644 (file)
@@ -21,7 +21,7 @@ int checkboard(void)
        return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
                            CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
index d8233529304d018b1d720d31b67e299a1244135a..67fd66815737c5e8bded44b3b7a5018c22b87073 100644 (file)
@@ -17,7 +17,7 @@ int checkboard(void)
        return 0;
 }
 
-phys_size_t initdram(int board_type)
+phys_size_t initdram(void)
 {
        return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
                            CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
index e98f319b3e1a0c98f69202e9f2abdd20d0b4d213..106fd347219e1502a6acb1342ffcc129ba697809 100644 (file)
@@ -180,13 +180,7 @@ static int announce_dram_init(void)
 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
 static int init_func_ram(void)
 {
-#ifdef CONFIG_BOARD_TYPES
-       int board_type = gd->board_type;
-#else
-       int board_type = 0;     /* use dummy arg */
-#endif
-
-       gd->ram_size = initdram(board_type);
+       gd->ram_size = initdram();
 
        if (gd->ram_size > 0)
                return 0;
index 5b356dd231e3cc3e2e141f92eec243bfc843b8a0..1a77c982fa3a5ab75ac533562312780e271915f2 100644 (file)
@@ -110,6 +110,12 @@ typedef struct global_data {
 } gd_t;
 #endif
 
+#ifdef CONFIG_BOARD_TYPES
+#define gd_board_type()                gd->board_type
+#else
+#define gd_board_type()                0
+#endif
+
 /*
  * Global Data Flags - the top 16 bits are reserved for arch-specific flags
  */
index 35e2b154ae9ed22bd533cfda82397aaa6c42d470..bbdb943cf01951e242fea783417adef38b8c7ebd 100644 (file)
@@ -209,7 +209,7 @@ int timer_init(void);
 int    cpu_init(void);
 
 /* */
-phys_size_t initdram (int);
+phys_size_t initdram(void);
 
 #include <display_options.h>