[people/ms/u-boot.git] / board / freescale / ls1043ardb / ls1043ardb.c

/*
 * Copyright 2015 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <ahci.h>
#include <mmc.h>
#include <scsi.h>
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include "cpld.h"

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
#ifndef CONFIG_SD_BOOT
	u8 cfg_rcw_src1, cfg_rcw_src2;
	u32 cfg_rcw_src;
#endif
	u32 sd1refclk_sel;

	printf("Board: LS1043ARDB, boot from ");

#ifdef CONFIG_SD_BOOT
	puts("SD\n");
#else
	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
	cpld_rev_bit(&cfg_rcw_src1);
	cfg_rcw_src = cfg_rcw_src1;
	cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;

	if (cfg_rcw_src == 0x25)
		printf("vBank %d\n", CPLD_READ(vbank));
	else if (cfg_rcw_src == 0x106)
		puts("NAND\n");
	else
		printf("Invalid setting of SW4\n");
#endif

	printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
	       CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));

	puts("SERDES Reference Clocks:\n");
	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);

	return 0;
}

int dram_init(void)
{
	gd->ram_size = initdram(0);

	return 0;
}

int board_early_init_f(void)
{
	fsl_lsch2_early_init_f();
	return 0;
}

int board_init(void)
{
	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;

	/*
	 * Set CCI-400 control override register to enable barrier
	 * transaction
	 */
	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);

#ifdef CONFIG_FSL_IFC
	init_final_memctl_regs();
#endif

#ifdef CONFIG_ENV_IS_NOWHERE
	gd->env_addr = (ulong)&default_environment[0];
#endif

#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
	enable_layerscape_ns_access();
#endif

	return 0;
}

int config_board_mux(void)
{
	return 0;
}

#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
	config_board_mux();

	return 0;
}
#endif

int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_ethernet(blob);
#endif
	return 0;
}

u8 flash_read8(void *addr)
{
	return __raw_readb(addr + 1);
}

void flash_write16(u16 val, void *addr)
{
	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));

	__raw_writew(shftval, addr);
}

u16 flash_read16(void *addr)
{
	u16 val = __raw_readw(addr);

	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
Commit	Line	Data
f3a8e2b7 MH	1	/*
	2	* Copyright 2015 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/clock.h>
	11	#include <asm/arch/fsl_serdes.h>
	12	#include <asm/arch/soc.h>
	13	#include <hwconfig.h>
	14	#include <ahci.h>
8ef0d5c4	15	#include <mmc.h>
f3a8e2b7	16	#include <scsi.h>
e8297341	17	#include <fm_eth.h>
f3a8e2b7 MH	18	#include <fsl_csu.h>
	19	#include <fsl_esdhc.h>
	20	#include <fsl_ifc.h>
	21	#include "cpld.h"
	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	int checkboard(void)
	26	{
	27	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
c7ca8b07	28	#ifndef CONFIG_SD_BOOT
f3a8e2b7 MH	29	u8 cfg_rcw_src1, cfg_rcw_src2;
f3a8e2b7 MH	30	u32 cfg_rcw_src;
c7ca8b07	31	#endif
f3a8e2b7 MH	32	u32 sd1refclk_sel;
	33
	34	printf("Board: LS1043ARDB, boot from ");
	35
c7ca8b07 GQ	36	#ifdef CONFIG_SD_BOOT
	37	puts("SD\n");
	38	#else
f3a8e2b7 MH	39	cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
	40	cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
	41	cpld_rev_bit(&cfg_rcw_src1);
	42	cfg_rcw_src = cfg_rcw_src1;
	43	cfg_rcw_src = (cfg_rcw_src << 1) \| cfg_rcw_src2;
	44
	45	if (cfg_rcw_src == 0x25)
	46	printf("vBank %d\n", CPLD_READ(vbank));
	47	else if (cfg_rcw_src == 0x106)
	48	puts("NAND\n");
	49	else
	50	printf("Invalid setting of SW4\n");
c7ca8b07	51	#endif
f3a8e2b7 MH	52
	53	printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
	54	CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
	55
	56	puts("SERDES Reference Clocks:\n");
	57	sd1refclk_sel = CPLD_READ(sd1refclk_sel);
	58	printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
	59
	60	return 0;
	61	}
	62
	63	int dram_init(void)
	64	{
	65	gd->ram_size = initdram(0);
	66
	67	return 0;
	68	}
	69
	70	int board_early_init_f(void)
	71	{
	72	fsl_lsch2_early_init_f();
	73	return 0;
	74	}
	75
	76	int board_init(void)
	77	{
	78	struct ccsr_cci400 cci = (struct ccsr_cci400 )CONFIG_SYS_CCI400_ADDR;
	79
	80	/*
	81	* Set CCI-400 control override register to enable barrier
	82	* transaction
	83	*/
	84	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
	85
	86	#ifdef CONFIG_FSL_IFC
	87	init_final_memctl_regs();
	88	#endif
	89
	90	#ifdef CONFIG_ENV_IS_NOWHERE
	91	gd->env_addr = (ulong)&default_environment[0];
	92	#endif
	93
	94	#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
	95	enable_layerscape_ns_access();
	96	#endif
	97
	98	return 0;
	99	}
	100
	101	int config_board_mux(void)
	102	{
	103	return 0;
	104	}
	105
	106	#if defined(CONFIG_MISC_INIT_R)
	107	int misc_init_r(void)
	108	{
	109	config_board_mux();
	110
	111	return 0;
	112	}
	113	#endif
	114
	115	int ft_board_setup(void blob, bd_t bd)
116	{
117	ft_cpu_setup(blob, bd);
118
e8297341 SX	119	#ifdef CONFIG_SYS_DPAA_FMAN
	120	fdt_fixup_fman_ethernet(blob);
	121	#endif
f3a8e2b7 MH	122	return 0;
	123	}
	124
	125	u8 flash_read8(void *addr)
	126	{
	127	return __raw_readb(addr + 1);
	128	}
	129
	130	void flash_write16(u16 val, void *addr)
	131	{
	132	u16 shftval = (((val >> 8) & 0xff) \| ((val << 8) & 0xff00));
	133
	134	__raw_writew(shftval, addr);
	135	}
	136
	137	u16 flash_read16(void *addr)
	138	{
	139	u16 val = __raw_readw(addr);
	140
	141	return (((val) >> 8) & 0x00ff) \| (((val) << 8) & 0xff00);
	142	}