[people/ms/u-boot.git] / board / freescale / mpc8568mds / mpc8568mds.c

/*
 * Copyright 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
#include <libfdt.h>
#include <fdt_support.h>

#include "bcsr.h"

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GETH1 */
	{4, 10, 1, 0, 2}, /* TxD0 */
	{4,  9, 1, 0, 2}, /* TxD1 */
	{4,  8, 1, 0, 2}, /* TxD2 */
	{4,  7, 1, 0, 2}, /* TxD3 */
	{4, 23, 1, 0, 2}, /* TxD4 */
	{4, 22, 1, 0, 2}, /* TxD5 */
	{4, 21, 1, 0, 2}, /* TxD6 */
	{4, 20, 1, 0, 2}, /* TxD7 */
	{4, 15, 2, 0, 2}, /* RxD0 */
	{4, 14, 2, 0, 2}, /* RxD1 */
	{4, 13, 2, 0, 2}, /* RxD2 */
	{4, 12, 2, 0, 2}, /* RxD3 */
	{4, 29, 2, 0, 2}, /* RxD4 */
	{4, 28, 2, 0, 2}, /* RxD5 */
	{4, 27, 2, 0, 2}, /* RxD6 */
	{4, 26, 2, 0, 2}, /* RxD7 */
	{4, 11, 1, 0, 2}, /* TX_EN */
	{4, 24, 1, 0, 2}, /* TX_ER */
	{4, 16, 2, 0, 2}, /* RX_DV */
	{4, 30, 2, 0, 2}, /* RX_ER */
	{4, 17, 2, 0, 2}, /* RX_CLK */
	{4, 19, 1, 0, 2}, /* GTX_CLK */
	{1, 31, 2, 0, 3}, /* GTX125 */

	/* GETH2 */
	{5, 10, 1, 0, 2}, /* TxD0 */
	{5,  9, 1, 0, 2}, /* TxD1 */
	{5,  8, 1, 0, 2}, /* TxD2 */
	{5,  7, 1, 0, 2}, /* TxD3 */
	{5, 23, 1, 0, 2}, /* TxD4 */
	{5, 22, 1, 0, 2}, /* TxD5 */
	{5, 21, 1, 0, 2}, /* TxD6 */
	{5, 20, 1, 0, 2}, /* TxD7 */
	{5, 15, 2, 0, 2}, /* RxD0 */
	{5, 14, 2, 0, 2}, /* RxD1 */
	{5, 13, 2, 0, 2}, /* RxD2 */
	{5, 12, 2, 0, 2}, /* RxD3 */
	{5, 29, 2, 0, 2}, /* RxD4 */
	{5, 28, 2, 0, 2}, /* RxD5 */
	{5, 27, 2, 0, 3}, /* RxD6 */
	{5, 26, 2, 0, 2}, /* RxD7 */
	{5, 11, 1, 0, 2}, /* TX_EN */
	{5, 24, 1, 0, 2}, /* TX_ER */
	{5, 16, 2, 0, 2}, /* RX_DV */
	{5, 30, 2, 0, 2}, /* RX_ER */
	{5, 17, 2, 0, 2}, /* RX_CLK */
	{5, 19, 1, 0, 2}, /* GTX_CLK */
	{1, 31, 2, 0, 3}, /* GTX125 */
	{4,  6, 3, 0, 2}, /* MDIO */
	{4,  5, 1, 0, 2}, /* MDC */

	/* UART1 */
	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
	{2, 1, 1, 0, 2}, /* UART_RTS1 */
	{2, 2, 2, 0, 2}, /* UART_CTS1 */
	{2, 3, 2, 0, 2}, /* UART_SIN1 */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};

void local_bus_init(void);
void sdram_init(void);

int board_early_init_f (void)
{
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	enable_8568mds_duart();
	enable_8568mds_flash_write();
#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
	reset_8568mds_uccs();
#endif
#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	enable_8568mds_qe_mdio();
#endif

#ifdef CONFIG_SYS_I2C2_OFFSET
	/* Enable I2C2_SCL and I2C2_SDA */
	volatile struct par_io *port_c;
	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
	port_c->cpdir2 |= 0x0f000000;
	port_c->cppar2 &= ~0x0f000000;
	port_c->cppar2 |= 0x0a000000;
#endif

	return 0;
}

int checkboard (void)
{
	printf ("Board: 8568 MDS\n");

	return 0;
}

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */

		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif

	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

	/*
	 * SDRAM Initialization
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	gur->lbiuiplldcr1 = 0x00078080;
	if (clkdiv == 16) {
		gur->lbiuiplldcr0 = 0x7c0f1bf0;
	} else if (clkdiv == 8) {
		gur->lbiuiplldcr0 = 0x6c0f1bf0;
	} else if (clkdiv == 4) {
		gur->lbiuiplldcr0 = 0x5c0f1bf0;
	}

	lbc->lcrr |= 0x00030000;

	asm("sync;isync;msync");
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void
sdram_init(void)
{
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)

	uint idx;
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint lsdmr_common;

	puts("    SDRAM: ");

	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
	asm("msync");

	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
	asm("msync");

	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	asm("msync");


	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("msync");

	/*
	 * MPC8568 uses "new" 15-16 style addressing.
	 */
	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
	lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_PCI)
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc8568mds_config_table[] = {
	{
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 pci_cfgfunc_config_device,
	 {PCI_ENET0_IOADDR,
	  PCI_ENET0_MEMADDR,
	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
	 },
	{}
};
#endif

static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_mpc8568mds_config_table,
#endif
};
#endif	/* CONFIG_PCI */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif  /* CONFIG_PCIE1 */

extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);

int first_free_busno = 0;

/*
 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
 */
void
pib_init(void)
{
	u8 val8, orig_i2c_bus;
	/*
	 * Assign PIB PMC2/3 to PCI bus
	 */

	/*switch temporarily to I2C bus #2 */
	orig_i2c_bus = i2c_get_bus_num();
	i2c_set_bus_num(1);

	val8 = 0x00;
	i2c_write(0x23, 0x6, 1, &val8, 1);
	i2c_write(0x23, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x23, 0x2, 1, &val8, 1);
	i2c_write(0x23, 0x3, 1, &val8, 1);

	val8 = 0x00;
	i2c_write(0x26, 0x6, 1, &val8, 1);
	val8 = 0x34;
	i2c_write(0x26, 0x7, 1, &val8, 1);
	val8 = 0xf9;
	i2c_write(0x26, 0x2, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x26, 0x3, 1, &val8, 1);

	val8 = 0x00;
	i2c_write(0x27, 0x6, 1, &val8, 1);
	i2c_write(0x27, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x27, 0x2, 1, &val8, 1);
	val8 = 0xef;
	i2c_write(0x27, 0x3, 1, &val8, 1);

	asm("eieio");
}

#ifdef CONFIG_PCI
void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

#ifdef CONFIG_PCI1
{
	pib_init();

	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	struct pci_controller *hose = &pci1_hose;
	struct pci_region *r = hose->regions;

	uint pci_32 = 1;      /* PORDEVSR[15] */
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */

	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);

	uint pci_speed = 66666000;

	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter"
			);

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
				CONFIG_SYS_PCI1_MEM_BUS,
				CONFIG_SYS_PCI1_MEM_PHYS,
				CONFIG_SYS_PCI1_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
				CONFIG_SYS_PCI1_IO_BASE,
				CONFIG_SYS_PCI1_IO_PHYS,
				CONFIG_SYS_PCI1_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = r - hose->regions;

		hose->first_busno = first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno = hose->last_busno+1;
		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
	} else {
	printf ("    PCI: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif

#ifdef CONFIG_PCIE1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
	struct pci_region *r = hose->regions;

	int pcie_configured  = io_sel >= 1;

	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE connected to slot as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);

		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		r += fsl_pci_setup_inbound_windows(r);

		/* outbound memory */
		pci_set_region(r++,
				CONFIG_SYS_PCIE1_MEM_BUS,
				CONFIG_SYS_PCIE1_MEM_PHYS,
				CONFIG_SYS_PCIE1_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(r++,
				CONFIG_SYS_PCIE1_IO_BASE,
				CONFIG_SYS_PCIE1_IO_PHYS,
				CONFIG_SYS_PCIE1_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = r - hose->regions;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);

		first_free_busno=hose->last_busno+1;

	} else {
		printf ("    PCIE: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif
}
#endif /* CONFIG_PCI */

#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
			struct pci_controller *hose);

void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_PCI1
	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
}
#endif
Commit	Line	Data
67431059 AF	1	/*
	2	* Copyright 2007 Freescale Semiconductor.
	3	*
	4	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <pci.h>
	27	#include <asm/processor.h>
e6f5b35b	28	#include <asm/mmu.h>
67431059	29	#include <asm/immap_85xx.h>
1563f56e	30	#include <asm/immap_fsl_pci.h>
e6f5b35b	31	#include <asm/fsl_ddr_sdram.h>
a30a549a	32	#include <spd_sdram.h>
c59e4091	33	#include <i2c.h>
da9d4610	34	#include <ioports.h>
c480861b KG	35	#include <libfdt.h>
c480861b KG	36	#include <fdt_support.h>
1563f56e	37
67431059 AF	38	#include "bcsr.h"
67431059 AF	39
da9d4610 AF	40	const qe_iop_conf_t qe_iop_conf_tab[] = {
	41	/* GETH1 */
	42	{4, 10, 1, 0, 2}, /* TxD0 */
	43	{4, 9, 1, 0, 2}, /* TxD1 */
	44	{4, 8, 1, 0, 2}, /* TxD2 */
	45	{4, 7, 1, 0, 2}, /* TxD3 */
	46	{4, 23, 1, 0, 2}, /* TxD4 */
	47	{4, 22, 1, 0, 2}, /* TxD5 */
	48	{4, 21, 1, 0, 2}, /* TxD6 */
	49	{4, 20, 1, 0, 2}, /* TxD7 */
	50	{4, 15, 2, 0, 2}, /* RxD0 */
	51	{4, 14, 2, 0, 2}, /* RxD1 */
	52	{4, 13, 2, 0, 2}, /* RxD2 */
	53	{4, 12, 2, 0, 2}, /* RxD3 */
	54	{4, 29, 2, 0, 2}, /* RxD4 */
	55	{4, 28, 2, 0, 2}, /* RxD5 */
	56	{4, 27, 2, 0, 2}, /* RxD6 */
	57	{4, 26, 2, 0, 2}, /* RxD7 */
	58	{4, 11, 1, 0, 2}, /* TX_EN */
	59	{4, 24, 1, 0, 2}, /* TX_ER */
	60	{4, 16, 2, 0, 2}, /* RX_DV */
	61	{4, 30, 2, 0, 2}, /* RX_ER */
	62	{4, 17, 2, 0, 2}, /* RX_CLK */
	63	{4, 19, 1, 0, 2}, /* GTX_CLK */
	64	{1, 31, 2, 0, 3}, /* GTX125 */
	65
	66	/* GETH2 */
	67	{5, 10, 1, 0, 2}, /* TxD0 */
	68	{5, 9, 1, 0, 2}, /* TxD1 */
	69	{5, 8, 1, 0, 2}, /* TxD2 */
	70	{5, 7, 1, 0, 2}, /* TxD3 */
	71	{5, 23, 1, 0, 2}, /* TxD4 */
	72	{5, 22, 1, 0, 2}, /* TxD5 */
	73	{5, 21, 1, 0, 2}, /* TxD6 */
	74	{5, 20, 1, 0, 2}, /* TxD7 */
	75	{5, 15, 2, 0, 2}, /* RxD0 */
	76	{5, 14, 2, 0, 2}, /* RxD1 */
	77	{5, 13, 2, 0, 2}, /* RxD2 */
	78	{5, 12, 2, 0, 2}, /* RxD3 */
	79	{5, 29, 2, 0, 2}, /* RxD4 */
	80	{5, 28, 2, 0, 2}, /* RxD5 */
	81	{5, 27, 2, 0, 3}, /* RxD6 */
	82	{5, 26, 2, 0, 2}, /* RxD7 */
	83	{5, 11, 1, 0, 2}, /* TX_EN */
	84	{5, 24, 1, 0, 2}, /* TX_ER */
	85	{5, 16, 2, 0, 2}, /* RX_DV */
	86	{5, 30, 2, 0, 2}, /* RX_ER */
	87	{5, 17, 2, 0, 2}, /* RX_CLK */
	88	{5, 19, 1, 0, 2}, /* GTX_CLK */
	89	{1, 31, 2, 0, 3}, /* GTX125 */
	90	{4, 6, 3, 0, 2}, /* MDIO */
	91	{4, 5, 1, 0, 2}, /* MDC */
64d4bcb0 AV	92
	93	/* UART1 */
	94	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
	95	{2, 1, 1, 0, 2}, /* UART_RTS1 */
	96	{2, 2, 2, 0, 2}, /* UART_CTS1 */
	97	{2, 3, 2, 0, 2}, /* UART_SIN1 */
	98
da9d4610 AF	99	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	100	};
	101
67431059 AF	102	void local_bus_init(void);
	103	void sdram_init(void);
	104
	105	int board_early_init_f (void)
	106	{
	107	/*
	108	* Initialize local bus.
	109	*/
	110	local_bus_init ();
	111
	112	enable_8568mds_duart();
	113	enable_8568mds_flash_write();
ad162249 AV	114	#if defined(CONFIG_UEC_ETH1) \|\| defined(CONFIG_UEC_ETH2)
	115	reset_8568mds_uccs();
	116	#endif
da9d4610 AF	117	#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	118	enable_8568mds_qe_mdio();
	119	#endif
67431059	120
6d0f6bcf	121	#ifdef CONFIG_SYS_I2C2_OFFSET
c59e4091 HW	122	/* Enable I2C2_SCL and I2C2_SDA */
c59e4091 HW	123	volatile struct par_io *port_c;
6d0f6bcf	124	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
c59e4091 HW	125	port_c->cpdir2 \|= 0x0f000000;
	126	port_c->cppar2 &= ~0x0f000000;
	127	port_c->cppar2 \|= 0x0a000000;
	128	#endif
	129
67431059 AF	130	return 0;
	131	}
	132
	133	int checkboard (void)
	134	{
	135	printf ("Board: 8568 MDS\n");
	136
	137	return 0;
	138	}
	139
9973e3c6	140	phys_size_t
67431059 AF	141	initdram(int board_type)
	142	{
	143	long dram_size = 0;
67431059 AF	144
	145	puts("Initializing\n");
	146
	147	#if defined(CONFIG_DDR_DLL)
	148	{
	149	/*
	150	* Work around to stabilize DDR DLL MSYNC_IN.
	151	* Errata DDR9 seems to have been fixed.
	152	* This is now the workaround for Errata DDR11:
	153	* Override DLL = 1, Course Adj = 1, Tap Select = 0
	154	*/
	155
6d0f6bcf	156	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
67431059 AF	157
	158	gur->ddrdllcr = 0x81000000;
	159	asm("sync;isync;msync");
	160	udelay(200);
	161	}
	162	#endif
e6f5b35b JL	163
	164	dram_size = fsl_ddr_sdram();
	165	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	166	dram_size *= 0x100000;
67431059	167
67431059 AF	168	/*
	169	* SDRAM Initialization
	170	*/
	171	sdram_init();
	172
	173	puts(" DDR: ");
	174	return dram_size;
	175	}
	176
	177	/*
	178	* Initialize Local Bus
	179	*/
	180	void
	181	local_bus_init(void)
	182	{
6d0f6bcf JCPV	183	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
6d0f6bcf JCPV	184	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
67431059 AF	185
	186	uint clkdiv;
	187	uint lbc_hz;
	188	sys_info_t sysinfo;
	189
	190	get_sys_info(&sysinfo);
a5d212a2	191	clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
67431059 AF	192	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	193
	194	gur->lbiuiplldcr1 = 0x00078080;
	195	if (clkdiv == 16) {
	196	gur->lbiuiplldcr0 = 0x7c0f1bf0;
	197	} else if (clkdiv == 8) {
	198	gur->lbiuiplldcr0 = 0x6c0f1bf0;
	199	} else if (clkdiv == 4) {
	200	gur->lbiuiplldcr0 = 0x5c0f1bf0;
	201	}
	202
	203	lbc->lcrr \|= 0x00030000;
	204
	205	asm("sync;isync;msync");
	206	}
	207
	208	/*
	209	* Initialize SDRAM memory on the Local Bus.
	210	*/
	211	void
	212	sdram_init(void)
	213	{
6d0f6bcf	214	#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
67431059 AF	215
67431059 AF	216	uint idx;
6d0f6bcf JCPV	217	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
6d0f6bcf JCPV	218	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
67431059 AF	219	uint lsdmr_common;
	220
	221	puts(" SDRAM: ");
	222
6d0f6bcf	223	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
67431059 AF	224
	225	/*
	226	* Setup SDRAM Base and Option Registers
	227	*/
6d0f6bcf	228	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
67431059 AF	229	asm("msync");
67431059 AF	230
6d0f6bcf	231	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
67431059 AF	232	asm("msync");
67431059 AF	233
6d0f6bcf	234	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
67431059 AF	235	asm("msync");
	236
	237
6d0f6bcf JCPV	238	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
6d0f6bcf JCPV	239	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
67431059 AF	240	asm("msync");
	241
	242	/*
	243	* MPC8568 uses "new" 15-16 style addressing.
	244	*/
6d0f6bcf JCPV	245	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
6d0f6bcf JCPV	246	lsdmr_common \|= CONFIG_SYS_LBC_LSDMR_BSMA1516;
67431059 AF	247
	248	/*
	249	* Issue PRECHARGE ALL command.
	250	*/
6d0f6bcf	251	lbc->lsdmr = lsdmr_common \| CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
67431059 AF	252	asm("sync;msync");
	253	*sdram_addr = 0xff;
	254	ppcDcbf((unsigned long) sdram_addr);
	255	udelay(100);
	256
	257	/*
	258	* Issue 8 AUTO REFRESH commands.
	259	*/
	260	for (idx = 0; idx < 8; idx++) {
6d0f6bcf	261	lbc->lsdmr = lsdmr_common \| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
67431059 AF	262	asm("sync;msync");
	263	*sdram_addr = 0xff;
	264	ppcDcbf((unsigned long) sdram_addr);
	265	udelay(100);
	266	}
	267
	268	/*
	269	* Issue 8 MODE-set command.
	270	*/
6d0f6bcf	271	lbc->lsdmr = lsdmr_common \| CONFIG_SYS_LBC_LSDMR_OP_MRW;
67431059 AF	272	asm("sync;msync");
	273	*sdram_addr = 0xff;
	274	ppcDcbf((unsigned long) sdram_addr);
	275	udelay(100);
	276
	277	/*
	278	* Issue NORMAL OP command.
	279	*/
6d0f6bcf	280	lbc->lsdmr = lsdmr_common \| CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
67431059 AF	281	asm("sync;msync");
	282	*sdram_addr = 0xff;
	283	ppcDcbf((unsigned long) sdram_addr);
	284	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	285
	286	#endif /* enable SDRAM init */
	287	}
	288
67431059 AF	289	#if defined(CONFIG_PCI)
	290	#ifndef CONFIG_PCI_PNP
	291	static struct pci_config_table pci_mpc8568mds_config_table[] = {
	292	{
	293	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	294	pci_cfgfunc_config_device,
	295	{PCI_ENET0_IOADDR,
	296	PCI_ENET0_MEMADDR,
	297	PCI_COMMON_MEMORY \| PCI_COMMAND_MASTER}
	298	},
	299	{}
	300	};
	301	#endif
	302
1563f56e	303	static struct pci_controller pci1_hose = {
67431059	304	#ifndef CONFIG_PCI_PNP
c59e4091	305	config_table: pci_mpc8568mds_config_table,
67431059 AF	306	#endif
67431059 AF	307	};
67431059 AF	308	#endif /* CONFIG_PCI */
67431059 AF	309
1563f56e HW	310	#ifdef CONFIG_PCIE1
	311	static struct pci_controller pcie1_hose;
	312	#endif /* CONFIG_PCIE1 */
	313
2dba0dea KG	314	extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
	315	extern void fsl_pci_init(struct pci_controller *hose);
	316
1563f56e HW	317	int first_free_busno = 0;
1563f56e HW	318
c59e4091 HW	319	/*
	320	* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
	321	*/
	322	void
	323	pib_init(void)
	324	{
	325	u8 val8, orig_i2c_bus;
	326	/*
	327	* Assign PIB PMC2/3 to PCI bus
	328	*/
	329
	330	/switch temporarily to I2C bus #2 /
	331	orig_i2c_bus = i2c_get_bus_num();
	332	i2c_set_bus_num(1);
	333
	334	val8 = 0x00;
	335	i2c_write(0x23, 0x6, 1, &val8, 1);
	336	i2c_write(0x23, 0x7, 1, &val8, 1);
	337	val8 = 0xff;
	338	i2c_write(0x23, 0x2, 1, &val8, 1);
	339	i2c_write(0x23, 0x3, 1, &val8, 1);
	340
	341	val8 = 0x00;
	342	i2c_write(0x26, 0x6, 1, &val8, 1);
	343	val8 = 0x34;
	344	i2c_write(0x26, 0x7, 1, &val8, 1);
	345	val8 = 0xf9;
	346	i2c_write(0x26, 0x2, 1, &val8, 1);
	347	val8 = 0xff;
	348	i2c_write(0x26, 0x3, 1, &val8, 1);
	349
	350	val8 = 0x00;
	351	i2c_write(0x27, 0x6, 1, &val8, 1);
	352	i2c_write(0x27, 0x7, 1, &val8, 1);
	353	val8 = 0xff;
	354	i2c_write(0x27, 0x2, 1, &val8, 1);
	355	val8 = 0xef;
	356	i2c_write(0x27, 0x3, 1, &val8, 1);
	357
	358	asm("eieio");
	359	}
	360
1563f56e	361	#ifdef CONFIG_PCI
67431059 AF	362	void
	363	pci_init_board(void)
	364	{
6d0f6bcf	365	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1563f56e HW	366	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	367	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	368
	369	#ifdef CONFIG_PCI1
	370	{
c59e4091	371	pib_init();
1563f56e	372
6d0f6bcf	373	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
1563f56e	374	struct pci_controller *hose = &pci1_hose;
2dba0dea	375	struct pci_region *r = hose->regions;
1563f56e HW	376
	377	uint pci_32 = 1; /* PORDEVSR[15] */
	378	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	379	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	380
	381	uint pci_agent = (host_agent == 3) \|\| (host_agent == 4 ) \|\| (host_agent == 6);
	382
	383	uint pci_speed = 66666000;
	384
	385	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
	386	printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
	387	(pci_32) ? 32 : 64,
	388	(pci_speed == 33333000) ? "33" :
	389	(pci_speed == 66666000) ? "66" : "unknown",
	390	pci_clk_sel ? "sync" : "async",
	391	pci_agent ? "agent" : "host",
	392	pci_arb ? "arbiter" : "external-arbiter"
	393	);
	394
	395	/* inbound */
2dba0dea	396	r += fsl_pci_setup_inbound_windows(r);
1563f56e HW	397
1563f56e HW	398	/* outbound memory */
2dba0dea	399	pci_set_region(r++,
10795f42	400	CONFIG_SYS_PCI1_MEM_BUS,
6d0f6bcf JCPV	401	CONFIG_SYS_PCI1_MEM_PHYS,
6d0f6bcf JCPV	402	CONFIG_SYS_PCI1_MEM_SIZE,
1563f56e HW	403	PCI_REGION_MEM);
	404
	405	/* outbound io */
2dba0dea	406	pci_set_region(r++,
6d0f6bcf JCPV	407	CONFIG_SYS_PCI1_IO_BASE,
	408	CONFIG_SYS_PCI1_IO_PHYS,
	409	CONFIG_SYS_PCI1_IO_SIZE,
1563f56e HW	410	PCI_REGION_IO);
1563f56e HW	411
2dba0dea	412	hose->region_count = r - hose->regions;
1563f56e HW	413
	414	hose->first_busno = first_free_busno;
	415	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	416
	417	fsl_pci_init(hose);
	418	first_free_busno = hose->last_busno+1;
	419	printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
	420	} else {
	421	printf (" PCI: disabled\n");
	422	}
	423	}
	424	#else
	425	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	426	#endif
	427
	428	#ifdef CONFIG_PCIE1
	429	{
6d0f6bcf	430	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
1563f56e HW	431	struct pci_controller *hose = &pcie1_hose;
1563f56e HW	432	int pcie_ep = (host_agent == 0) \|\| (host_agent == 2 ) \|\| (host_agent == 3);
2dba0dea	433	struct pci_region *r = hose->regions;
1563f56e HW	434
	435	int pcie_configured = io_sel >= 1;
	436
	437	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
	438	printf ("\n PCIE connected to slot as %s (base address %x)",
	439	pcie_ep ? "End Point" : "Root Complex",
	440	(uint)pci);
	441
	442	if (pci->pme_msg_det) {
	443	pci->pme_msg_det = 0xffffffff;
	444	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	445	}
	446	printf ("\n");
	447
	448	/* inbound */
2dba0dea	449	r += fsl_pci_setup_inbound_windows(r);
1563f56e HW	450
1563f56e HW	451	/* outbound memory */
2dba0dea	452	pci_set_region(r++,
10795f42	453	CONFIG_SYS_PCIE1_MEM_BUS,
6d0f6bcf JCPV	454	CONFIG_SYS_PCIE1_MEM_PHYS,
6d0f6bcf JCPV	455	CONFIG_SYS_PCIE1_MEM_SIZE,
1563f56e HW	456	PCI_REGION_MEM);
	457
	458	/* outbound io */
2dba0dea	459	pci_set_region(r++,
6d0f6bcf JCPV	460	CONFIG_SYS_PCIE1_IO_BASE,
	461	CONFIG_SYS_PCIE1_IO_PHYS,
	462	CONFIG_SYS_PCIE1_IO_SIZE,
1563f56e HW	463	PCI_REGION_IO);
1563f56e HW	464
2dba0dea	465	hose->region_count = r - hose->regions;
1563f56e HW	466
	467	hose->first_busno=first_free_busno;
	468	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	469
	470	fsl_pci_init(hose);
	471	printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
	472
	473	first_free_busno=hose->last_busno+1;
	474
	475	} else {
	476	printf (" PCIE: disabled\n");
	477	}
	478	}
	479	#else
	480	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
67431059 AF	481	#endif
67431059 AF	482	}
1563f56e HW	483	#endif /* CONFIG_PCI */
1563f56e HW	484
c480861b	485	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea	486	extern void ft_fsl_pci_setup(void blob, const char pci_alias,
3cbd8231	487	struct pci_controller *hose);
1563f56e	488
2dba0dea KG	489	void ft_board_setup(void blob, bd_t bd)
2dba0dea KG	490	{
1563f56e	491	ft_cpu_setup(blob, bd);
1563f56e HW	492
1563f56e HW	493	#ifdef CONFIG_PCI1
2dba0dea	494	ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
1563f56e	495	#endif
1563f56e	496	#ifdef CONFIG_PCIE1
2dba0dea	497	ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
1563f56e HW	498	#endif
	499	}
	500	#endif