[people/ms/u-boot.git] / board / freescale / mpc8568mds / mpc8568mds.c

/*
 * Copyright 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <ioports.h>
#include <libfdt.h>
#include <fdt_support.h>

#include "bcsr.h"

const qe_iop_conf_t qe_iop_conf_tab[] = {
	/* GETH1 */
	{4, 10, 1, 0, 2}, /* TxD0 */
	{4,  9, 1, 0, 2}, /* TxD1 */
	{4,  8, 1, 0, 2}, /* TxD2 */
	{4,  7, 1, 0, 2}, /* TxD3 */
	{4, 23, 1, 0, 2}, /* TxD4 */
	{4, 22, 1, 0, 2}, /* TxD5 */
	{4, 21, 1, 0, 2}, /* TxD6 */
	{4, 20, 1, 0, 2}, /* TxD7 */
	{4, 15, 2, 0, 2}, /* RxD0 */
	{4, 14, 2, 0, 2}, /* RxD1 */
	{4, 13, 2, 0, 2}, /* RxD2 */
	{4, 12, 2, 0, 2}, /* RxD3 */
	{4, 29, 2, 0, 2}, /* RxD4 */
	{4, 28, 2, 0, 2}, /* RxD5 */
	{4, 27, 2, 0, 2}, /* RxD6 */
	{4, 26, 2, 0, 2}, /* RxD7 */
	{4, 11, 1, 0, 2}, /* TX_EN */
	{4, 24, 1, 0, 2}, /* TX_ER */
	{4, 16, 2, 0, 2}, /* RX_DV */
	{4, 30, 2, 0, 2}, /* RX_ER */
	{4, 17, 2, 0, 2}, /* RX_CLK */
	{4, 19, 1, 0, 2}, /* GTX_CLK */
	{1, 31, 2, 0, 3}, /* GTX125 */

	/* GETH2 */
	{5, 10, 1, 0, 2}, /* TxD0 */
	{5,  9, 1, 0, 2}, /* TxD1 */
	{5,  8, 1, 0, 2}, /* TxD2 */
	{5,  7, 1, 0, 2}, /* TxD3 */
	{5, 23, 1, 0, 2}, /* TxD4 */
	{5, 22, 1, 0, 2}, /* TxD5 */
	{5, 21, 1, 0, 2}, /* TxD6 */
	{5, 20, 1, 0, 2}, /* TxD7 */
	{5, 15, 2, 0, 2}, /* RxD0 */
	{5, 14, 2, 0, 2}, /* RxD1 */
	{5, 13, 2, 0, 2}, /* RxD2 */
	{5, 12, 2, 0, 2}, /* RxD3 */
	{5, 29, 2, 0, 2}, /* RxD4 */
	{5, 28, 2, 0, 2}, /* RxD5 */
	{5, 27, 2, 0, 3}, /* RxD6 */
	{5, 26, 2, 0, 2}, /* RxD7 */
	{5, 11, 1, 0, 2}, /* TX_EN */
	{5, 24, 1, 0, 2}, /* TX_ER */
	{5, 16, 2, 0, 2}, /* RX_DV */
	{5, 30, 2, 0, 2}, /* RX_ER */
	{5, 17, 2, 0, 2}, /* RX_CLK */
	{5, 19, 1, 0, 2}, /* GTX_CLK */
	{1, 31, 2, 0, 3}, /* GTX125 */
	{4,  6, 3, 0, 2}, /* MDIO */
	{4,  5, 1, 0, 2}, /* MDC */

	/* UART1 */
	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
	{2, 1, 1, 0, 2}, /* UART_RTS1 */
	{2, 2, 2, 0, 2}, /* UART_CTS1 */
	{2, 3, 2, 0, 2}, /* UART_SIN1 */

	{0,  0, 0, 0, QE_IOP_TAB_END}, /* END of table */
};


#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

void local_bus_init(void);
void sdram_init(void);

int board_early_init_f (void)
{
	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	enable_8568mds_duart();
	enable_8568mds_flash_write();
#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
	reset_8568mds_uccs();
#endif
#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	enable_8568mds_qe_mdio();
#endif

#ifdef CONFIG_SYS_I2C2_OFFSET
	/* Enable I2C2_SCL and I2C2_SDA */
	volatile struct par_io *port_c;
	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
	port_c->cpdir2 |= 0x0f000000;
	port_c->cppar2 &= ~0x0f000000;
	port_c->cppar2 |= 0x0a000000;
#endif

	return 0;
}

int checkboard (void)
{
	printf ("Board: 8568 MDS\n");

	return 0;
}

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_DDR_DLL)
	{
		/*
		 * Work around to stabilize DDR DLL MSYNC_IN.
		 * Errata DDR9 seems to have been fixed.
		 * This is now the workaround for Errata DDR11:
		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
		 */

		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

		gur->ddrdllcr = 0x81000000;
		asm("sync;isync;msync");
		udelay(200);
	}
#endif

	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

	/*
	 * SDRAM Initialization
	 */
	sdram_init();

	puts("    DDR: ");
	return dram_size;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);

	uint clkdiv;
	uint lbc_hz;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (lbc->lcrr & 0x0f) * 2;
	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;

	gur->lbiuiplldcr1 = 0x00078080;
	if (clkdiv == 16) {
		gur->lbiuiplldcr0 = 0x7c0f1bf0;
	} else if (clkdiv == 8) {
		gur->lbiuiplldcr0 = 0x6c0f1bf0;
	} else if (clkdiv == 4) {
		gur->lbiuiplldcr0 = 0x5c0f1bf0;
	}

	lbc->lcrr |= 0x00030000;

	asm("sync;isync;msync");
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void
sdram_init(void)
{
#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)

	uint idx;
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint lsdmr_common;

	puts("    SDRAM: ");

	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
	asm("msync");

	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
	asm("msync");

	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
	asm("msync");


	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
	asm("msync");

	/*
	 * MPC8568 uses "new" 15-16 style addressing.
	 */
	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
	lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;

	/*
	 * Issue PRECHARGE ALL command.
	 */
	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(100);

	/*
	 * Issue NORMAL OP command.
	 */
	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_PCI)
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc8568mds_config_table[] = {
	{
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 pci_cfgfunc_config_device,
	 {PCI_ENET0_IOADDR,
	  PCI_ENET0_MEMADDR,
	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
	 },
	{}
};
#endif

static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
	config_table: pci_mpc8568mds_config_table,
#endif
};
#endif	/* CONFIG_PCI */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif  /* CONFIG_PCIE1 */

int first_free_busno = 0;

/*
 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
 */
void
pib_init(void)
{
	u8 val8, orig_i2c_bus;
	/*
	 * Assign PIB PMC2/3 to PCI bus
	 */

	/*switch temporarily to I2C bus #2 */
	orig_i2c_bus = i2c_get_bus_num();
	i2c_set_bus_num(1);

	val8 = 0x00;
	i2c_write(0x23, 0x6, 1, &val8, 1);
	i2c_write(0x23, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x23, 0x2, 1, &val8, 1);
	i2c_write(0x23, 0x3, 1, &val8, 1);

	val8 = 0x00;
	i2c_write(0x26, 0x6, 1, &val8, 1);
	val8 = 0x34;
	i2c_write(0x26, 0x7, 1, &val8, 1);
	val8 = 0xf9;
	i2c_write(0x26, 0x2, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x26, 0x3, 1, &val8, 1);

	val8 = 0x00;
	i2c_write(0x27, 0x6, 1, &val8, 1);
	i2c_write(0x27, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x27, 0x2, 1, &val8, 1);
	val8 = 0xef;
	i2c_write(0x27, 0x3, 1, &val8, 1);

	asm("eieio");
}

#ifdef CONFIG_PCI
void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

#ifdef CONFIG_PCI1
{
	pib_init();

	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci1_hose;

	uint pci_32 = 1;      /* PORDEVSR[15] */
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */

	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);

	uint pci_speed = 66666000;

	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter"
			);

		/* inbound */
		pci_set_region(hose->regions + 0,
				CONFIG_SYS_PCI_MEMORY_BUS,
				CONFIG_SYS_PCI_MEMORY_PHYS,
				CONFIG_SYS_PCI_MEMORY_SIZE,
				PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
				CONFIG_SYS_PCI1_MEM_BASE,
				CONFIG_SYS_PCI1_MEM_PHYS,
				CONFIG_SYS_PCI1_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
				CONFIG_SYS_PCI1_IO_BASE,
				CONFIG_SYS_PCI1_IO_PHYS,
				CONFIG_SYS_PCI1_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = 3;

		hose->first_busno = first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno = hose->last_busno+1;
		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
	} else {
	printf ("    PCI: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif

#ifdef CONFIG_PCIE1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);

	int pcie_configured  = io_sel >= 1;

	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE connected to slot as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);

		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		pci_set_region(hose->regions + 0,
				CONFIG_SYS_PCI_MEMORY_BUS,
				CONFIG_SYS_PCI_MEMORY_PHYS,
				CONFIG_SYS_PCI_MEMORY_SIZE,
				PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
				CONFIG_SYS_PCIE1_MEM_BASE,
				CONFIG_SYS_PCIE1_MEM_PHYS,
				CONFIG_SYS_PCIE1_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
				CONFIG_SYS_PCIE1_IO_BASE,
				CONFIG_SYS_PCIE1_IO_PHYS,
				CONFIG_SYS_PCIE1_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = 3;

		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);

		first_free_busno=hose->last_busno+1;

	} else {
		printf ("    PCIE: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif
}
#endif /* CONFIG_PCI */

#if defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	ft_cpu_setup(blob, bd);

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI1
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
#ifdef CONFIG_PCIE1
		path = fdt_getprop(blob, node, "pci1", NULL);
		if (path) {
			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif
Commit	Line	Data
67431059 AF	1	/*
	2	* Copyright 2007 Freescale Semiconductor.
	3	*
	4	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <pci.h>
	27	#include <asm/processor.h>
e6f5b35b	28	#include <asm/mmu.h>
67431059	29	#include <asm/immap_85xx.h>
1563f56e	30	#include <asm/immap_fsl_pci.h>
e6f5b35b	31	#include <asm/fsl_ddr_sdram.h>
a30a549a	32	#include <spd_sdram.h>
c59e4091	33	#include <i2c.h>
da9d4610	34	#include <ioports.h>
c480861b KG	35	#include <libfdt.h>
c480861b KG	36	#include <fdt_support.h>
1563f56e	37
67431059 AF	38	#include "bcsr.h"
67431059 AF	39
da9d4610 AF	40	const qe_iop_conf_t qe_iop_conf_tab[] = {
	41	/* GETH1 */
	42	{4, 10, 1, 0, 2}, /* TxD0 */
	43	{4, 9, 1, 0, 2}, /* TxD1 */
	44	{4, 8, 1, 0, 2}, /* TxD2 */
	45	{4, 7, 1, 0, 2}, /* TxD3 */
	46	{4, 23, 1, 0, 2}, /* TxD4 */
	47	{4, 22, 1, 0, 2}, /* TxD5 */
	48	{4, 21, 1, 0, 2}, /* TxD6 */
	49	{4, 20, 1, 0, 2}, /* TxD7 */
	50	{4, 15, 2, 0, 2}, /* RxD0 */
	51	{4, 14, 2, 0, 2}, /* RxD1 */
	52	{4, 13, 2, 0, 2}, /* RxD2 */
	53	{4, 12, 2, 0, 2}, /* RxD3 */
	54	{4, 29, 2, 0, 2}, /* RxD4 */
	55	{4, 28, 2, 0, 2}, /* RxD5 */
	56	{4, 27, 2, 0, 2}, /* RxD6 */
	57	{4, 26, 2, 0, 2}, /* RxD7 */
	58	{4, 11, 1, 0, 2}, /* TX_EN */
	59	{4, 24, 1, 0, 2}, /* TX_ER */
	60	{4, 16, 2, 0, 2}, /* RX_DV */
	61	{4, 30, 2, 0, 2}, /* RX_ER */
	62	{4, 17, 2, 0, 2}, /* RX_CLK */
	63	{4, 19, 1, 0, 2}, /* GTX_CLK */
	64	{1, 31, 2, 0, 3}, /* GTX125 */
	65
	66	/* GETH2 */
	67	{5, 10, 1, 0, 2}, /* TxD0 */
	68	{5, 9, 1, 0, 2}, /* TxD1 */
	69	{5, 8, 1, 0, 2}, /* TxD2 */
	70	{5, 7, 1, 0, 2}, /* TxD3 */
	71	{5, 23, 1, 0, 2}, /* TxD4 */
	72	{5, 22, 1, 0, 2}, /* TxD5 */
	73	{5, 21, 1, 0, 2}, /* TxD6 */
	74	{5, 20, 1, 0, 2}, /* TxD7 */
	75	{5, 15, 2, 0, 2}, /* RxD0 */
	76	{5, 14, 2, 0, 2}, /* RxD1 */
	77	{5, 13, 2, 0, 2}, /* RxD2 */
	78	{5, 12, 2, 0, 2}, /* RxD3 */
	79	{5, 29, 2, 0, 2}, /* RxD4 */
	80	{5, 28, 2, 0, 2}, /* RxD5 */
	81	{5, 27, 2, 0, 3}, /* RxD6 */
	82	{5, 26, 2, 0, 2}, /* RxD7 */
	83	{5, 11, 1, 0, 2}, /* TX_EN */
	84	{5, 24, 1, 0, 2}, /* TX_ER */
	85	{5, 16, 2, 0, 2}, /* RX_DV */
	86	{5, 30, 2, 0, 2}, /* RX_ER */
	87	{5, 17, 2, 0, 2}, /* RX_CLK */
	88	{5, 19, 1, 0, 2}, /* GTX_CLK */
	89	{1, 31, 2, 0, 3}, /* GTX125 */
	90	{4, 6, 3, 0, 2}, /* MDIO */
	91	{4, 5, 1, 0, 2}, /* MDC */
64d4bcb0 AV	92
	93	/* UART1 */
	94	{2, 0, 1, 0, 2}, /* UART_SOUT1 */
	95	{2, 1, 1, 0, 2}, /* UART_RTS1 */
	96	{2, 2, 2, 0, 2}, /* UART_CTS1 */
	97	{2, 3, 2, 0, 2}, /* UART_SIN1 */
	98
da9d4610 AF	99	{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
	100	};
	101
67431059 AF	102
	103	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	104	extern void ddr_enable_ecc(unsigned int dram_size);
	105	#endif
	106
67431059 AF	107	void local_bus_init(void);
	108	void sdram_init(void);
	109
	110	int board_early_init_f (void)
	111	{
	112	/*
	113	* Initialize local bus.
	114	*/
	115	local_bus_init ();
	116
	117	enable_8568mds_duart();
	118	enable_8568mds_flash_write();
ad162249 AV	119	#if defined(CONFIG_UEC_ETH1) \|\| defined(CONFIG_UEC_ETH2)
	120	reset_8568mds_uccs();
	121	#endif
da9d4610 AF	122	#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
	123	enable_8568mds_qe_mdio();
	124	#endif
67431059	125
6d0f6bcf	126	#ifdef CONFIG_SYS_I2C2_OFFSET
c59e4091 HW	127	/* Enable I2C2_SCL and I2C2_SDA */
c59e4091 HW	128	volatile struct par_io *port_c;
6d0f6bcf	129	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
c59e4091 HW	130	port_c->cpdir2 \|= 0x0f000000;
	131	port_c->cppar2 &= ~0x0f000000;
	132	port_c->cppar2 \|= 0x0a000000;
	133	#endif
	134
67431059 AF	135	return 0;
	136	}
	137
	138	int checkboard (void)
	139	{
	140	printf ("Board: 8568 MDS\n");
	141
	142	return 0;
	143	}
	144
9973e3c6	145	phys_size_t
67431059 AF	146	initdram(int board_type)
	147	{
	148	long dram_size = 0;
67431059 AF	149
	150	puts("Initializing\n");
	151
	152	#if defined(CONFIG_DDR_DLL)
	153	{
	154	/*
	155	* Work around to stabilize DDR DLL MSYNC_IN.
	156	* Errata DDR9 seems to have been fixed.
	157	* This is now the workaround for Errata DDR11:
	158	* Override DLL = 1, Course Adj = 1, Tap Select = 0
	159	*/
	160
6d0f6bcf	161	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
67431059 AF	162
	163	gur->ddrdllcr = 0x81000000;
	164	asm("sync;isync;msync");
	165	udelay(200);
	166	}
	167	#endif
e6f5b35b JL	168
	169	dram_size = fsl_ddr_sdram();
	170	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	171	dram_size *= 0x100000;
67431059 AF	172
	173	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	174	/*
	175	* Initialize and enable DDR ECC.
	176	*/
	177	ddr_enable_ecc(dram_size);
	178	#endif
e6f5b35b	179
67431059 AF	180	/*
	181	* SDRAM Initialization
	182	*/
	183	sdram_init();
	184
	185	puts(" DDR: ");
	186	return dram_size;
	187	}
	188
	189	/*
	190	* Initialize Local Bus
	191	*/
	192	void
	193	local_bus_init(void)
	194	{
6d0f6bcf JCPV	195	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
6d0f6bcf JCPV	196	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
67431059 AF	197
	198	uint clkdiv;
	199	uint lbc_hz;
	200	sys_info_t sysinfo;
	201
	202	get_sys_info(&sysinfo);
	203	clkdiv = (lbc->lcrr & 0x0f) * 2;
	204	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
	205
	206	gur->lbiuiplldcr1 = 0x00078080;
	207	if (clkdiv == 16) {
	208	gur->lbiuiplldcr0 = 0x7c0f1bf0;
	209	} else if (clkdiv == 8) {
	210	gur->lbiuiplldcr0 = 0x6c0f1bf0;
	211	} else if (clkdiv == 4) {
	212	gur->lbiuiplldcr0 = 0x5c0f1bf0;
	213	}
	214
	215	lbc->lcrr \|= 0x00030000;
	216
	217	asm("sync;isync;msync");
	218	}
	219
	220	/*
	221	* Initialize SDRAM memory on the Local Bus.
	222	*/
	223	void
	224	sdram_init(void)
	225	{
6d0f6bcf	226	#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
67431059 AF	227
67431059 AF	228	uint idx;
6d0f6bcf JCPV	229	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
6d0f6bcf JCPV	230	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
67431059 AF	231	uint lsdmr_common;
	232
	233	puts(" SDRAM: ");
	234
6d0f6bcf	235	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
67431059 AF	236
	237	/*
	238	* Setup SDRAM Base and Option Registers
	239	*/
6d0f6bcf	240	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
67431059 AF	241	asm("msync");
67431059 AF	242
6d0f6bcf	243	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
67431059 AF	244	asm("msync");
67431059 AF	245
6d0f6bcf	246	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
67431059 AF	247	asm("msync");
	248
	249
6d0f6bcf JCPV	250	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
6d0f6bcf JCPV	251	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
67431059 AF	252	asm("msync");
	253
	254	/*
	255	* MPC8568 uses "new" 15-16 style addressing.
	256	*/
6d0f6bcf JCPV	257	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
6d0f6bcf JCPV	258	lsdmr_common \|= CONFIG_SYS_LBC_LSDMR_BSMA1516;
67431059 AF	259
	260	/*
	261	* Issue PRECHARGE ALL command.
	262	*/
6d0f6bcf	263	lbc->lsdmr = lsdmr_common \| CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
67431059 AF	264	asm("sync;msync");
	265	*sdram_addr = 0xff;
	266	ppcDcbf((unsigned long) sdram_addr);
	267	udelay(100);
	268
	269	/*
	270	* Issue 8 AUTO REFRESH commands.
	271	*/
	272	for (idx = 0; idx < 8; idx++) {
6d0f6bcf	273	lbc->lsdmr = lsdmr_common \| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
67431059 AF	274	asm("sync;msync");
	275	*sdram_addr = 0xff;
	276	ppcDcbf((unsigned long) sdram_addr);
	277	udelay(100);
	278	}
	279
	280	/*
	281	* Issue 8 MODE-set command.
	282	*/
6d0f6bcf	283	lbc->lsdmr = lsdmr_common \| CONFIG_SYS_LBC_LSDMR_OP_MRW;
67431059 AF	284	asm("sync;msync");
	285	*sdram_addr = 0xff;
	286	ppcDcbf((unsigned long) sdram_addr);
	287	udelay(100);
	288
	289	/*
	290	* Issue NORMAL OP command.
	291	*/
6d0f6bcf	292	lbc->lsdmr = lsdmr_common \| CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
67431059 AF	293	asm("sync;msync");
	294	*sdram_addr = 0xff;
	295	ppcDcbf((unsigned long) sdram_addr);
	296	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	297
	298	#endif /* enable SDRAM init */
	299	}
	300
67431059 AF	301	#if defined(CONFIG_PCI)
	302	#ifndef CONFIG_PCI_PNP
	303	static struct pci_config_table pci_mpc8568mds_config_table[] = {
	304	{
	305	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	306	pci_cfgfunc_config_device,
	307	{PCI_ENET0_IOADDR,
	308	PCI_ENET0_MEMADDR,
	309	PCI_COMMON_MEMORY \| PCI_COMMAND_MASTER}
	310	},
	311	{}
	312	};
	313	#endif
	314
1563f56e	315	static struct pci_controller pci1_hose = {
67431059	316	#ifndef CONFIG_PCI_PNP
c59e4091	317	config_table: pci_mpc8568mds_config_table,
67431059 AF	318	#endif
67431059 AF	319	};
67431059 AF	320	#endif /* CONFIG_PCI */
67431059 AF	321
1563f56e HW	322	#ifdef CONFIG_PCIE1
	323	static struct pci_controller pcie1_hose;
	324	#endif /* CONFIG_PCIE1 */
	325
	326	int first_free_busno = 0;
	327
c59e4091 HW	328	/*
	329	* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
	330	*/
	331	void
	332	pib_init(void)
	333	{
	334	u8 val8, orig_i2c_bus;
	335	/*
	336	* Assign PIB PMC2/3 to PCI bus
	337	*/
	338
	339	/switch temporarily to I2C bus #2 /
	340	orig_i2c_bus = i2c_get_bus_num();
	341	i2c_set_bus_num(1);
	342
	343	val8 = 0x00;
	344	i2c_write(0x23, 0x6, 1, &val8, 1);
	345	i2c_write(0x23, 0x7, 1, &val8, 1);
	346	val8 = 0xff;
	347	i2c_write(0x23, 0x2, 1, &val8, 1);
	348	i2c_write(0x23, 0x3, 1, &val8, 1);
	349
	350	val8 = 0x00;
	351	i2c_write(0x26, 0x6, 1, &val8, 1);
	352	val8 = 0x34;
	353	i2c_write(0x26, 0x7, 1, &val8, 1);
	354	val8 = 0xf9;
	355	i2c_write(0x26, 0x2, 1, &val8, 1);
	356	val8 = 0xff;
	357	i2c_write(0x26, 0x3, 1, &val8, 1);
	358
	359	val8 = 0x00;
	360	i2c_write(0x27, 0x6, 1, &val8, 1);
	361	i2c_write(0x27, 0x7, 1, &val8, 1);
	362	val8 = 0xff;
	363	i2c_write(0x27, 0x2, 1, &val8, 1);
	364	val8 = 0xef;
	365	i2c_write(0x27, 0x3, 1, &val8, 1);
	366
	367	asm("eieio");
	368	}
	369
1563f56e	370	#ifdef CONFIG_PCI
67431059 AF	371	void
	372	pci_init_board(void)
	373	{
6d0f6bcf	374	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
1563f56e HW	375	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	376	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	377
	378	#ifdef CONFIG_PCI1
	379	{
c59e4091	380	pib_init();
1563f56e	381
6d0f6bcf	382	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
1563f56e HW	383	extern void fsl_pci_init(struct pci_controller *hose);
	384	struct pci_controller *hose = &pci1_hose;
	385
	386	uint pci_32 = 1; /* PORDEVSR[15] */
	387	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	388	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	389
	390	uint pci_agent = (host_agent == 3) \|\| (host_agent == 4 ) \|\| (host_agent == 6);
	391
	392	uint pci_speed = 66666000;
	393
	394	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
	395	printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
	396	(pci_32) ? 32 : 64,
	397	(pci_speed == 33333000) ? "33" :
	398	(pci_speed == 66666000) ? "66" : "unknown",
	399	pci_clk_sel ? "sync" : "async",
	400	pci_agent ? "agent" : "host",
	401	pci_arb ? "arbiter" : "external-arbiter"
	402	);
	403
	404	/* inbound */
	405	pci_set_region(hose->regions + 0,
6d0f6bcf JCPV	406	CONFIG_SYS_PCI_MEMORY_BUS,
	407	CONFIG_SYS_PCI_MEMORY_PHYS,
	408	CONFIG_SYS_PCI_MEMORY_SIZE,
1563f56e HW	409	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	410
	411	/* outbound memory */
	412	pci_set_region(hose->regions + 1,
6d0f6bcf JCPV	413	CONFIG_SYS_PCI1_MEM_BASE,
	414	CONFIG_SYS_PCI1_MEM_PHYS,
	415	CONFIG_SYS_PCI1_MEM_SIZE,
1563f56e HW	416	PCI_REGION_MEM);
	417
	418	/* outbound io */
	419	pci_set_region(hose->regions + 2,
6d0f6bcf JCPV	420	CONFIG_SYS_PCI1_IO_BASE,
	421	CONFIG_SYS_PCI1_IO_PHYS,
	422	CONFIG_SYS_PCI1_IO_SIZE,
1563f56e HW	423	PCI_REGION_IO);
	424
	425	hose->region_count = 3;
	426
	427	hose->first_busno = first_free_busno;
	428	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	429
	430	fsl_pci_init(hose);
	431	first_free_busno = hose->last_busno+1;
	432	printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
	433	} else {
	434	printf (" PCI: disabled\n");
	435	}
	436	}
	437	#else
	438	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	439	#endif
	440
	441	#ifdef CONFIG_PCIE1
	442	{
6d0f6bcf	443	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
1563f56e HW	444	extern void fsl_pci_init(struct pci_controller *hose);
	445	struct pci_controller *hose = &pcie1_hose;
	446	int pcie_ep = (host_agent == 0) \|\| (host_agent == 2 ) \|\| (host_agent == 3);
	447
	448	int pcie_configured = io_sel >= 1;
	449
	450	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
	451	printf ("\n PCIE connected to slot as %s (base address %x)",
	452	pcie_ep ? "End Point" : "Root Complex",
	453	(uint)pci);
	454
	455	if (pci->pme_msg_det) {
	456	pci->pme_msg_det = 0xffffffff;
	457	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	458	}
	459	printf ("\n");
	460
	461	/* inbound */
	462	pci_set_region(hose->regions + 0,
6d0f6bcf JCPV	463	CONFIG_SYS_PCI_MEMORY_BUS,
	464	CONFIG_SYS_PCI_MEMORY_PHYS,
	465	CONFIG_SYS_PCI_MEMORY_SIZE,
1563f56e HW	466	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	467
	468	/* outbound memory */
	469	pci_set_region(hose->regions + 1,
6d0f6bcf JCPV	470	CONFIG_SYS_PCIE1_MEM_BASE,
	471	CONFIG_SYS_PCIE1_MEM_PHYS,
	472	CONFIG_SYS_PCIE1_MEM_SIZE,
1563f56e HW	473	PCI_REGION_MEM);
	474
	475	/* outbound io */
	476	pci_set_region(hose->regions + 2,
6d0f6bcf JCPV	477	CONFIG_SYS_PCIE1_IO_BASE,
	478	CONFIG_SYS_PCIE1_IO_PHYS,
	479	CONFIG_SYS_PCIE1_IO_SIZE,
1563f56e HW	480	PCI_REGION_IO);
	481
	482	hose->region_count = 3;
	483
	484	hose->first_busno=first_free_busno;
	485	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	486
	487	fsl_pci_init(hose);
	488	printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
	489
	490	first_free_busno=hose->last_busno+1;
	491
	492	} else {
	493	printf (" PCIE: disabled\n");
	494	}
	495	}
	496	#else
	497	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
67431059 AF	498	#endif
67431059 AF	499	}
1563f56e HW	500	#endif /* CONFIG_PCI */
1563f56e HW	501
c480861b	502	#if defined(CONFIG_OF_BOARD_SETUP)
1563f56e HW	503	void
	504	ft_board_setup(void blob, bd_t bd)
	505	{
c480861b KG	506	int node, tmp[2];
c480861b KG	507	const char *path;
1563f56e HW	508
1563f56e HW	509	ft_cpu_setup(blob, bd);
1563f56e	510
c480861b KG	511	node = fdt_path_offset(blob, "/aliases");
	512	tmp[0] = 0;
	513	if (node >= 0) {
1563f56e	514	#ifdef CONFIG_PCI1
c480861b KG	515	path = fdt_getprop(blob, node, "pci0", NULL);
	516	if (path) {
	517	tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
	518	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	519	}
1563f56e	520	#endif
1563f56e	521	#ifdef CONFIG_PCIE1
c480861b KG	522	path = fdt_getprop(blob, node, "pci1", NULL);
	523	if (path) {
	524	tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
	525	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	526	}
1563f56e	527	#endif
c480861b	528	}
1563f56e HW	529	}
1563f56e HW	530	#endif