[people/ms/u-boot.git] / board / freescale / mpc8610hpcd / mpc8610hpcd.c

/*
 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <i2c.h>
#include <asm/io.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <netdev.h>

DECLARE_GLOBAL_DATA_PTR;

void sdram_init(void);
phys_size_t fixed_sdram(void);
int mpc8610hpcd_diu_init(void);


/* called before any console output */
int board_early_init_f(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_gur_t *gur = &immap->im_gur;

	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */

	return 0;
}

int misc_init_r(void)
{
	u8 tmp_val, version;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	/*Do not use 8259PIC*/
	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);

	/*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
	version = in_8(pixis_base + PIXIS_PVER);
	if(version >= 0x07) {
		tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
		out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
	}

	/* Using this for DIU init before the driver in linux takes over
	 *  Enable the TFP410 Encoder (I2C address 0x38)
	 */

	tmp_val = 0xBF;
	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	/* Verify if enabled */
	tmp_val = 0;
	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	debug("DVI Encoder Read: 0x%02x\n", tmp_val);

	tmp_val = 0x10;
	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	/* Verify if enabled */
	tmp_val = 0;
	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	debug("DVI Encoder Read: 0x%02x\n", tmp_val);

	return 0;
}

int checkboard(void)
{
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
		in_8(pixis_base + PIXIS_PVER));

	/*
	 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
	 * bank and LBMAP=00 is the alternate bank.  However, the pixis
	 * altbank code can only set bits, not clear them, so we treat 00 as
	 * the normal bank and 11 as the alternate.
	 */
	switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
	case 0:
		puts("vBank: Standard\n");
		break;
	case 0x40:
		puts("Promjet\n");
		break;
	case 0x80:
		puts("NAND\n");
		break;
	case 0xC0:
		puts("vBank: Alternate\n");
		break;
	}

	mcm->abcr |= 0x00010000; /* 0 */
	mcm->hpmr3 = 0x80000008; /* 4c */
	mcm->hpmr0 = 0;
	mcm->hpmr1 = 0;
	mcm->hpmr2 = 0;
	mcm->hpmr4 = 0;
	mcm->hpmr5 = 0;

	return 0;
}


int initdram(void)
{
	phys_size_t dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram();
#endif

	setup_ddr_bat(dram_size);

	debug(" DDR: ");
	gd->ram_size = dram_size;

	return 0;
}


#if !defined(CONFIG_SPD_EEPROM)
/*
 * Fixed sdram init -- doesn't use serial presence detect.
 */

phys_size_t fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
	uint d_init;

	ddr->cs0_bnds = 0x0000001f;
	ddr->cs0_config = 0x80010202;

	ddr->timing_cfg_3 = 0x00000000;
	ddr->timing_cfg_0 = 0x00260802;
	ddr->timing_cfg_1 = 0x3935d322;
	ddr->timing_cfg_2 = 0x14904cc8;
	ddr->sdram_mode = 0x00480432;
	ddr->sdram_mode_2 = 0x00000000;
	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
	ddr->sdram_data_init = 0xDEADBEEF;
	ddr->sdram_clk_cntl = 0x03800000;
	ddr->sdram_cfg_2 = 0x04400010;

#if defined(CONFIG_DDR_ECC)
	ddr->err_int_en = 0x0000000d;
	ddr->err_disable = 0x00000000;
	ddr->err_sbe = 0x00010000;
#endif
	asm("sync;isync");

	udelay(500);

	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/


#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	d_init = 1;
	debug("DDR - 1st controller: memory initializing\n");
	/*
	 * Poll until memory is initialized.
	 * 512 Meg at 400 might hit this 200 times or so.
	 */
	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
		udelay(1000);

	debug("DDR: memory initialized\n\n");
	asm("sync; isync");
	udelay(500);
#endif

	return 512 * 1024 * 1024;
#endif
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}

#endif

#if defined(CONFIG_PCI)
/*
 * Initialize PCI Devices, report devices found.
 */

#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_fsl86xxads_config_table[] = {
	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 PCI_IDSEL_NUMBER, PCI_ANY_ID,
	 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
				 PCI_ENET0_MEMADDR,
				 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
	{}
};
#endif


static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI */

void pci_init_board(void)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
	volatile ccsr_gur_t *gur = &immap->im_gur;
	struct fsl_pci_info pci_info;
	u32 devdisr;
	int first_free_busno;
	int pci_agent;

	devdisr = in_be32(&gur->devdisr);

	first_free_busno = fsl_pcie_init_board(0);

#ifdef CONFIG_PCI1
	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
		printf("PCI: connected to PCI slots as %s" \
			" (base address %lx)\n",
			pci_agent ? "Agent" : "Host",
			pci_info.regs);
#ifndef CONFIG_PCI_PNP
		pci1_hose.config_table = pci_mpc86xxcts_config_table;
#endif
		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
#endif

	fsl_pcie_init_board(first_free_busno);
}

#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

	FT_FSL_PCI_SETUP;

	return 0;
}
#endif

/*
 * get_board_sys_clk
 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 */

unsigned long
get_board_sys_clk(ulong dummy)
{
	u8 i;
	ulong val = 0;
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	i = in_8(pixis_base + PIXIS_SPD);
	i &= 0x07;

	switch (i) {
	case 0:
		val = 33333000;
		break;
	case 1:
		val = 39999600;
		break;
	case 2:
		val = 49999500;
		break;
	case 3:
		val = 66666000;
		break;
	case 4:
		val = 83332500;
		break;
	case 5:
		val = 99999000;
		break;
	case 6:
		val = 133332000;
		break;
	case 7:
		val = 166665000;
		break;
	}

	return val;
}

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}

void board_reset(void)
{
	u8 *pixis_base = (u8 *)PIXIS_BASE;

	out_8(pixis_base + PIXIS_RST, 0);

	while (1)
		;
}
Commit	Line	Data
3dd2db53	1	/*
d5c784ed	2	* Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
3dd2db53	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
3dd2db53	5	*/
c9974ab0	6
3dd2db53 JL	7	#include <common.h>
	8	#include <command.h>
	9	#include <pci.h>
	10	#include <asm/processor.h>
	11	#include <asm/immap_86xx.h>
c8514622	12	#include <asm/fsl_pci.h>
5614e71b	13	#include <fsl_ddr_sdram.h>
5d27e02c	14	#include <asm/fsl_serdes.h>
c9974ab0	15	#include <i2c.h>
3dd2db53	16	#include <asm/io.h>
1df170f8 JL	17	#include <libfdt.h>
1df170f8 JL	18	#include <fdt_support.h>
a30a549a	19	#include <spd_sdram.h>
89973f8a	20	#include <netdev.h>
3dd2db53	21
088454cd SG	22	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	23
3dd2db53	24	void sdram_init(void);
4c77de3f	25	phys_size_t fixed_sdram(void);
e69e520f	26	int mpc8610hpcd_diu_init(void);
c9974ab0	27
3dd2db53 JL	28
	29	/* called before any console output */
	30	int board_early_init_f(void)
	31	{
6d0f6bcf	32	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
3dd2db53 JL	33	volatile ccsr_gur_t *gur = &immap->im_gur;
3dd2db53 JL	34
a877880c YS	35	gur->gpiocr \|= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
	36
	37	return 0;
	38	}
	39
	40	int misc_init_r(void)
	41	{
	42	u8 tmp_val, version;
048e7efe	43	u8 pixis_base = (u8 )PIXIS_BASE;
a877880c YS	44
a877880c YS	45	/Do not use 8259PIC/
048e7efe KG	46	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
048e7efe KG	47	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val \| 0x80);
a877880c YS	48
a877880c YS	49	/For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt/
048e7efe	50	version = in_8(pixis_base + PIXIS_PVER);
a877880c	51	if(version >= 0x07) {
048e7efe KG	52	tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
048e7efe KG	53	out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
a877880c YS	54	}
	55
	56	/* Using this for DIU init before the driver in linux takes over
	57	* Enable the TFP410 Encoder (I2C address 0x38)
	58	*/
	59
	60	tmp_val = 0xBF;
	61	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	62	/* Verify if enabled */
	63	tmp_val = 0;
	64	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
7315ab22	65	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
a877880c YS	66
	67	tmp_val = 0x10;
	68	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	69	/* Verify if enabled */
	70	tmp_val = 0;
	71	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
7315ab22	72	debug("DVI Encoder Read: 0x%02x\n", tmp_val);
a877880c	73
3dd2db53 JL	74	return 0;
	75	}
	76
	77	int checkboard(void)
	78	{
6d0f6bcf	79	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
3dd2db53	80	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
048e7efe	81	u8 pixis_base = (u8 )PIXIS_BASE;
3dd2db53	82
26fd33b9 TT	83	printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
26fd33b9 TT	84	"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
048e7efe KG	85	in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
048e7efe KG	86	in_8(pixis_base + PIXIS_PVER));
3dd2db53	87
26fd33b9 TT	88	/*
	89	* The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
	90	* bank and LBMAP=00 is the alternate bank. However, the pixis
	91	* altbank code can only set bits, not clear them, so we treat 00 as
	92	* the normal bank and 11 as the alternate.
	93	*/
	94	switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
	95	case 0:
	96	puts("vBank: Standard\n");
	97	break;
	98	case 0x40:
	99	puts("Promjet\n");
	100	break;
	101	case 0x80:
	102	puts("NAND\n");
	103	break;
	104	case 0xC0:
	105	puts("vBank: Alternate\n");
	106	break;
	107	}
	108
3dd2db53 JL	109	mcm->abcr \|= 0x00010000; /* 0 */
	110	mcm->hpmr3 = 0x80000008; /* 4c */
	111	mcm->hpmr0 = 0;
	112	mcm->hpmr1 = 0;
	113	mcm->hpmr2 = 0;
	114	mcm->hpmr4 = 0;
	115	mcm->hpmr5 = 0;
	116
	117	return 0;
	118	}
	119
	120
088454cd	121	int initdram(void)
3dd2db53	122	{
4c77de3f	123	phys_size_t dram_size = 0;
3dd2db53 JL	124
3dd2db53 JL	125	#if defined(CONFIG_SPD_EEPROM)
39aa1a73	126	dram_size = fsl_ddr_sdram();
3dd2db53 JL	127	#else
	128	dram_size = fixed_sdram();
	129	#endif
	130
9ff32d8c TT	131	setup_ddr_bat(dram_size);
9ff32d8c TT	132
21cd5815	133	debug(" DDR: ");
088454cd SG	134	gd->ram_size = dram_size;
	135
	136	return 0;
3dd2db53 JL	137	}
	138
	139
3dd2db53 JL	140	#if !defined(CONFIG_SPD_EEPROM)
	141	/*
	142	* Fixed sdram init -- doesn't use serial presence detect.
	143	*/
	144
4c77de3f	145	phys_size_t fixed_sdram(void)
3dd2db53	146	{
6d0f6bcf JCPV	147	#if !defined(CONFIG_SYS_RAMBOOT)
6d0f6bcf JCPV	148	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
9a17eb5b	149	struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
3dd2db53 JL	150	uint d_init;
	151
	152	ddr->cs0_bnds = 0x0000001f;
	153	ddr->cs0_config = 0x80010202;
	154
45239cf4	155	ddr->timing_cfg_3 = 0x00000000;
3dd2db53 JL	156	ddr->timing_cfg_0 = 0x00260802;
	157	ddr->timing_cfg_1 = 0x3935d322;
	158	ddr->timing_cfg_2 = 0x14904cc8;
e7ee23ec	159	ddr->sdram_mode = 0x00480432;
3dd2db53 JL	160	ddr->sdram_mode_2 = 0x00000000;
	161	ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
	162	ddr->sdram_data_init = 0xDEADBEEF;
	163	ddr->sdram_clk_cntl = 0x03800000;
	164	ddr->sdram_cfg_2 = 0x04400010;
	165
	166	#if defined(CONFIG_DDR_ECC)
	167	ddr->err_int_en = 0x0000000d;
	168	ddr->err_disable = 0x00000000;
	169	ddr->err_sbe = 0x00010000;
	170	#endif
	171	asm("sync;isync");
	172
	173	udelay(500);
	174
e7ee23ec	175	ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
3dd2db53 JL	176
	177
	178	#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	179	d_init = 1;
	180	debug("DDR - 1st controller: memory initializing\n");
	181	/*
	182	* Poll until memory is initialized.
	183	* 512 Meg at 400 might hit this 200 times or so.
	184	*/
	185	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
	186	udelay(1000);
	187
	188	debug("DDR: memory initialized\n\n");
	189	asm("sync; isync");
	190	udelay(500);
	191	#endif
	192
	193	return 512 * 1024 * 1024;
	194	#endif
6d0f6bcf	195	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
3dd2db53 JL	196	}
	197
	198	#endif
	199
	200	#if defined(CONFIG_PCI)
	201	/*
	202	* Initialize PCI Devices, report devices found.
	203	*/
	204
	205	#ifndef CONFIG_PCI_PNP
	206	static struct pci_config_table pci_fsl86xxads_config_table[] = {
	207	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	208	PCI_IDSEL_NUMBER, PCI_ANY_ID,
	209	pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
	210	PCI_ENET0_MEMADDR,
	211	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER} },
	212	{}
	213	};
	214	#endif
	215
	216
d5c784ed	217	static struct pci_controller pci1_hose;
3dd2db53 JL	218	#endif /* CONFIG_PCI */
3dd2db53 JL	219
3dd2db53 JL	220	void pci_init_board(void)
3dd2db53 JL	221	{
6d0f6bcf	222	volatile immap_t immap = (immap_t ) CONFIG_SYS_CCSRBAR;
3dd2db53	223	volatile ccsr_gur_t *gur = &immap->im_gur;
b8526212	224	struct fsl_pci_info pci_info;
e38cc2c7	225	u32 devdisr;
b8526212 KG	226	int first_free_busno;
b8526212 KG	227	int pci_agent;
5e3d7050 KG	228
5e3d7050 KG	229	devdisr = in_be32(&gur->devdisr);
3dd2db53	230
b8526212	231	first_free_busno = fsl_pcie_init_board(0);
3dd2db53 JL	232
3dd2db53 JL	233	#ifdef CONFIG_PCI1
5e3d7050	234	if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
b8526212 KG	235	SET_STD_PCI_INFO(pci_info, 1);
	236	set_next_law(pci_info.mem_phys,
	237	law_size_bits(pci_info.mem_size), pci_info.law);
	238	set_next_law(pci_info.io_phys,
	239	law_size_bits(pci_info.io_size), pci_info.law);
	240
	241	pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
8ca78f2c	242	printf("PCI: connected to PCI slots as %s" \
5e3d7050	243	" (base address %lx)\n",
3dd2db53	244	pci_agent ? "Agent" : "Host",
b8526212	245	pci_info.regs);
d5c784ed ZC	246	#ifndef CONFIG_PCI_PNP
	247	pci1_hose.config_table = pci_mpc86xxcts_config_table;
	248	#endif
b8526212	249	first_free_busno = fsl_pci_init_port(&pci_info,
5e3d7050 KG	250	&pci1_hose, first_free_busno);
5e3d7050 KG	251	} else {
8ca78f2c	252	printf("PCI: disabled\n");
5e3d7050	253	}
3dd2db53	254
5e3d7050 KG	255	puts("\n");
	256	#else
	257	setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
	258	#endif
b8526212 KG	259
b8526212 KG	260	fsl_pcie_init_board(first_free_busno);
3dd2db53 JL	261	}
3dd2db53 JL	262
1df170f8	263	#if defined(CONFIG_OF_BOARD_SETUP)
e895a4b0	264	int ft_board_setup(void blob, bd_t bd)
3dd2db53	265	{
8439f05c	266	ft_cpu_setup(blob, bd);
1df170f8	267
6525d51f	268	FT_FSL_PCI_SETUP;
e895a4b0 SG	269
e895a4b0 SG	270	return 0;
3dd2db53 JL	271	}
	272	#endif
	273
	274	/*
	275	* get_board_sys_clk
	276	* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
	277	*/
	278
	279	unsigned long
	280	get_board_sys_clk(ulong dummy)
	281	{
a877880c	282	u8 i;
3dd2db53	283	ulong val = 0;
048e7efe	284	u8 pixis_base = (u8 )PIXIS_BASE;
3dd2db53	285
048e7efe	286	i = in_8(pixis_base + PIXIS_SPD);
3dd2db53 JL	287	i &= 0x07;
	288
	289	switch (i) {
	290	case 0:
	291	val = 33333000;
	292	break;
	293	case 1:
	294	val = 39999600;
	295	break;
	296	case 2:
	297	val = 49999500;
	298	break;
	299	case 3:
	300	val = 66666000;
	301	break;
	302	case 4:
	303	val = 83332500;
	304	break;
	305	case 5:
	306	val = 99999000;
	307	break;
	308	case 6:
	309	val = 133332000;
	310	break;
	311	case 7:
	312	val = 166665000;
	313	break;
	314	}
	315
	316	return val;
	317	}
65d3d99c	318
65d3d99c BW	319	int board_eth_init(bd_t *bis)
65d3d99c BW	320	{
89973f8a	321	return pci_eth_init(bis);
65d3d99c	322	}
4ef630df PT	323
	324	void board_reset(void)
	325	{
048e7efe KG	326	u8 pixis_base = (u8 )PIXIS_BASE;
	327
	328	out_8(pixis_base + PIXIS_RST, 0);
4ef630df PT	329
	330	while (1)
	331	;
	332	}