]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/freescale/mx6sabresd/mx6sabresd.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mx6sabresd: Add SPL support for the mx6dl variant
[people/ms/u-boot.git] / board / freescale / mx6sabresd / mx6sabresd.c
CommitLineData
7891e258
FE		 1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
7891e258
FE		 7 */
8
7891e258
FE		 9#include <asm/arch/clock.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/iomux.h>
c1747970 12#include <asm/arch/mx6-pins.h>
1221ce45 13#include <linux/errno.h>
7891e258 14#include <asm/gpio.h>
66ca09fc 15#include <asm/imx-common/mxc_i2c.h>
7891e258 16#include <asm/imx-common/iomux-v3.h>
85449dbd 17#include <asm/imx-common/boot_mode.h>
053b795e 18#include <asm/imx-common/video.h>
7891e258
FE		 19#include <mmc.h>
20#include <fsl_esdhc.h>
21#include <miiphy.h>
22#include <netdev.h>
58cc9787
PKS		 23#include <asm/arch/mxc_hdmi.h>
24#include <asm/arch/crm_regs.h>
58cc9787
PKS		 25#include <asm/io.h>
26#include <asm/arch/sys_proto.h>
66ca09fc
FE		 27#include <i2c.h>
28#include <power/pmic.h>
29#include <power/pfuze100_pmic.h>
f0fabb79 30#include "../common/pfuze.h"
5a3d63c5 31#include <usb.h>
75f2ba42 32
7891e258
FE		 33DECLARE_GLOBAL_DATA_PTR;
34
7e2173cf
BT		 35#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
37 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
7891e258 38
7e2173cf
BT		 39#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
41 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
7891e258 42
7e2173cf
BT		 43#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
7891e258 45
8bfa9c69
FE		 46#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
47 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
48
66ca09fc
FE		 49#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
51 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
52
53#define I2C_PMIC 1
54
55#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
56
ca9d817a
FE		 57#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
58
d96796ca
DD		 59#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
60
7891e258
FE		 61int dram_init(void)
62{
75f2ba42 63 gd->ram_size = imx_ddr_size();
7891e258
FE		 64 return 0;
65}
66
3302c275 67static iomux_v3_cfg_t const uart1_pads[] = {
ff9f71b4
FE		 68 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
69 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
7891e258
FE		 70};
71
3302c275 72static iomux_v3_cfg_t const enet_pads[] = {
ff9f71b4
FE		 73 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
74 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
a0d21fc0 88 /* AR8031 PHY Reset */
ff9f71b4 89 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
a0d21fc0
FE		 90};
91
92static void setup_iomux_enet(void)
93{
ff9f71b4 94 SETUP_IOMUX_PADS(enet_pads);
a0d21fc0
FE		 95
96 /* Reset AR8031 PHY */
97 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
a307760a 98 mdelay(10);
a0d21fc0 99 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
a307760a 100 udelay(100);
a0d21fc0
FE		 101}
102
3302c275 103static iomux_v3_cfg_t const usdhc2_pads[] = {
ff9f71b4
FE		 104 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
105 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
106 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
107 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
108 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
109 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
110 IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
111 IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
112 IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
113 IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
114 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
de7d02ae
SG		 115};
116
3302c275 117static iomux_v3_cfg_t const usdhc3_pads[] = {
ff9f71b4
FE		 118 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
119 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
120 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
121 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
122 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
123 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
124 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
125 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
126 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
127 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
128 IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
7891e258
FE		 129};
130
3302c275 131static iomux_v3_cfg_t const usdhc4_pads[] = {
ff9f71b4
FE		 132 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
133 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
134 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
135 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
136 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
137 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
138 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
139 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
140 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
141 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
de7d02ae
SG		 142};
143
3302c275 144static iomux_v3_cfg_t const ecspi1_pads[] = {
ff9f71b4
FE		 145 IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
146 IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
147 IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
148 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
8bfa9c69
FE		 149};
150
ca9d817a 151static iomux_v3_cfg_t const rgb_pads[] = {
ff9f71b4
FE		 152 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
153 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
154 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
155 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
156 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
157 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
158 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
159 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
160 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
161 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
162 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
163 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
164 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
165 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
166 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
167 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
168 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
169 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
170 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
171 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
172 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
173 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
174 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
175 IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
176 IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
177 IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
178 IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
179 IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
180 IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
6c51a364
MF		 181};
182
183static iomux_v3_cfg_t const bl_pads[] = {
ff9f71b4 184 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
ca9d817a
FE		 185};
186
6c51a364
MF		 187static void enable_backlight(void)
188{
ff9f71b4 189 SETUP_IOMUX_PADS(bl_pads);
6c51a364
MF		 190 gpio_direction_output(DISP0_PWR_EN, 1);
191}
192
ca9d817a
FE		 193static void enable_rgb(struct display_info_t const *dev)
194{
ff9f71b4 195 SETUP_IOMUX_PADS(rgb_pads);
6c51a364
MF		 196 enable_backlight();
197}
198
199static void enable_lvds(struct display_info_t const *dev)
200{
201 enable_backlight();
ca9d817a
FE		 202}
203
ff9f71b4 204static struct i2c_pads_info mx6q_i2c_pad_info1 = {
66ca09fc 205 .scl = {
ff9f71b4
FE		 206 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
207 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
66ca09fc
FE		 208 .gp = IMX_GPIO_NR(4, 12)
209 },
210 .sda = {
ff9f71b4
FE		 211 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
212 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
213 .gp = IMX_GPIO_NR(4, 13)
214 }
215};
216
217static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
218 .scl = {
219 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
220 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
221 .gp = IMX_GPIO_NR(4, 12)
222 },
223 .sda = {
224 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
225 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
66ca09fc
FE		 226 .gp = IMX_GPIO_NR(4, 13)
227 }
228};
229
8bfa9c69
FE		 230static void setup_spi(void)
231{
ff9f71b4 232 SETUP_IOMUX_PADS(ecspi1_pads);
8bfa9c69
FE		 233}
234
e919aa23 235iomux_v3_cfg_t const pcie_pads[] = {
ff9f71b4
FE		 236 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
237 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
e919aa23
MV		 238};
239
240static void setup_pcie(void)
241{
ff9f71b4 242 SETUP_IOMUX_PADS(pcie_pads);
e919aa23
MV		 243}
244
be4ab3dd 245iomux_v3_cfg_t const di0_pads[] = {
ff9f71b4
FE		 246 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
247 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
248 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
be4ab3dd
FE		 249};
250
7891e258
FE		 251static void setup_iomux_uart(void)
252{
ff9f71b4 253 SETUP_IOMUX_PADS(uart1_pads);
7891e258
FE		 254}
255
256#ifdef CONFIG_FSL_ESDHC
de7d02ae
SG		 257struct fsl_esdhc_cfg usdhc_cfg[3] = {
258 {USDHC2_BASE_ADDR},
7891e258 259 {USDHC3_BASE_ADDR},
de7d02ae 260 {USDHC4_BASE_ADDR},
7891e258
FE		 261};
262
de7d02ae
SG		 263#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
264#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
265
fb0d0428
PF		 266int board_mmc_get_env_dev(int devno)
267{
268 return devno - 1;
269}
270
7891e258
FE		 271int board_mmc_getcd(struct mmc *mmc)
272{
de7d02ae 273 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
60bb4621 274 int ret = 0;
de7d02ae
SG		 275
276 switch (cfg->esdhc_base) {
277 case USDHC2_BASE_ADDR:
60bb4621
OS		 278 ret = !gpio_get_value(USDHC2_CD_GPIO);
279 break;
de7d02ae 280 case USDHC3_BASE_ADDR:
60bb4621
OS		 281 ret = !gpio_get_value(USDHC3_CD_GPIO);
282 break;
283 case USDHC4_BASE_ADDR:
284 ret = 1; /* eMMC/uSDHC4 is always present */
285 break;
de7d02ae 286 }
60bb4621
OS		 287
288 return ret;
7891e258
FE		 289}
290
291int board_mmc_init(bd_t *bis)
292{
75f2ba42 293#ifndef CONFIG_SPL_BUILD
952fdc4e 294 int ret;
de7d02ae
SG		 295 int i;
296
28ff917c
OS		 297 /*
298 * According to the board_mmc_init() the following map is done:
a187559e 299 * (U-Boot device node) (Physical Port)
28ff917c
OS		 300 * mmc0 SD2
301 * mmc1 SD3
302 * mmc2 eMMC
303 */
de7d02ae
SG		 304 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
305 switch (i) {
306 case 0:
ff9f71b4 307 SETUP_IOMUX_PADS(usdhc2_pads);
de7d02ae
SG		 308 gpio_direction_input(USDHC2_CD_GPIO);
309 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
310 break;
311 case 1:
ff9f71b4 312 SETUP_IOMUX_PADS(usdhc3_pads);
de7d02ae
SG		 313 gpio_direction_input(USDHC3_CD_GPIO);
314 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
315 break;
316 case 2:
ff9f71b4 317 SETUP_IOMUX_PADS(usdhc4_pads);
de7d02ae
SG		 318 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
319 break;
320 default:
321 printf("Warning: you configured more USDHC controllers"
f07e286c
OS		 322 "(%d) then supported by the board (%d)\n",
323 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
952fdc4e 324 return -EINVAL;
f07e286c 325 }
de7d02ae 326
952fdc4e
FE		 327 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
328 if (ret)
329 return ret;
de7d02ae 330 }
7891e258 331
952fdc4e 332 return 0;
75f2ba42 333#else
ae80eecc
FE		 334 struct src *psrc = (struct src *)SRC_BASE_ADDR;
335 unsigned reg = readl(&psrc->sbmr1) >> 11;
75f2ba42
JT		 336 /*
337 * Upon reading BOOT_CFG register the following map is done:
338 * Bit 11 and 12 of BOOT_CFG register can determine the current
339 * mmc port
340 * 0x1 SD1
341 * 0x2 SD2
342 * 0x3 SD4
343 */
344
345 switch (reg & 0x3) {
346 case 0x1:
ff9f71b4 347 SETUP_IOMUX_PADS(usdhc2_pads);
75f2ba42
JT		 348 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
349 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
350 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
351 break;
352 case 0x2:
ff9f71b4 353 SETUP_IOMUX_PADS(usdhc3_pads);
75f2ba42
JT		 354 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
355 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
356 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
357 break;
358 case 0x3:
ff9f71b4 359 SETUP_IOMUX_PADS(usdhc4_pads);
75f2ba42
JT		 360 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
361 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
362 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
363 break;
364 }
365
366 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
367#endif
7891e258
FE		 368}
369#endif
370
4b6035da
FE		 371static int ar8031_phy_fixup(struct phy_device *phydev)
372{
373 unsigned short val;
374
375 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
376 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
377 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
378 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
379
380 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
381 val &= 0xffe3;
382 val |= 0x18;
383 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
384
385 /* introduce tx clock delay */
386 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
387 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
388 val |= 0x0100;
389 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
390
391 return 0;
392}
393
394int board_phy_config(struct phy_device *phydev)
395{
396 ar8031_phy_fixup(phydev);
397
398 if (phydev->drv->config)
399 phydev->drv->config(phydev);
400
401 return 0;
402}
403
58cc9787 404#if defined(CONFIG_VIDEO_IPUV3)
b48e3b04
FE		 405static void disable_lvds(struct display_info_t const *dev)
406{
407 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
408
409 int reg = readl(&iomux->gpr[2]);
410
411 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
412 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
413
414 writel(reg, &iomux->gpr[2]);
415}
416
d9b89460
FE		 417static void do_enable_hdmi(struct display_info_t const *dev)
418{
b48e3b04 419 disable_lvds(dev);
d9b89460
FE		 420 imx_enable_hdmi_phy();
421}
58cc9787 422
053b795e 423struct display_info_t const displays[] = {{
d9b89460
FE		 424 .bus = -1,
425 .addr = 0,
119e9909 426 .pixfmt = IPU_PIX_FMT_RGB666,
b48e3b04 427 .detect = NULL,
6c51a364 428 .enable = enable_lvds,
d9b89460 429 .mode = {
b48e3b04 430 .name = "Hannstar-XGA",
d9b89460
FE		 431 .refresh = 60,
432 .xres = 1024,
433 .yres = 768,
779594d3
FE		 434 .pixclock = 15384,
435 .left_margin = 160,
436 .right_margin = 24,
437 .upper_margin = 29,
438 .lower_margin = 3,
439 .hsync_len = 136,
440 .vsync_len = 6,
d9b89460
FE		 441 .sync = FB_SYNC_EXT,
442 .vmode = FB_VMODE_NONINTERLACED
443} }, {
444 .bus = -1,
445 .addr = 0,
b48e3b04
FE		 446 .pixfmt = IPU_PIX_FMT_RGB24,
447 .detect = detect_hdmi,
448 .enable = do_enable_hdmi,
d9b89460 449 .mode = {
b48e3b04 450 .name = "HDMI",
d9b89460
FE		 451 .refresh = 60,
452 .xres = 1024,
453 .yres = 768,
779594d3
FE		 454 .pixclock = 15384,
455 .left_margin = 160,
456 .right_margin = 24,
457 .upper_margin = 29,
458 .lower_margin = 3,
459 .hsync_len = 136,
460 .vsync_len = 6,
d9b89460
FE		 461 .sync = FB_SYNC_EXT,
462 .vmode = FB_VMODE_NONINTERLACED
ca9d817a
FE		 463} }, {
464 .bus = 0,
465 .addr = 0,
466 .pixfmt = IPU_PIX_FMT_RGB24,
467 .detect = NULL,
468 .enable = enable_rgb,
469 .mode = {
470 .name = "SEIKO-WVGA",
471 .refresh = 60,
472 .xres = 800,
473 .yres = 480,
474 .pixclock = 29850,
475 .left_margin = 89,
476 .right_margin = 164,
477 .upper_margin = 23,
478 .lower_margin = 10,
479 .hsync_len = 10,
480 .vsync_len = 10,
481 .sync = 0,
482 .vmode = FB_VMODE_NONINTERLACED
d9b89460 483} } };
053b795e 484size_t display_count = ARRAY_SIZE(displays);
58cc9787
PKS		 485
486static void setup_display(void)
487{
488 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
d9b89460 489 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
58cc9787
PKS		 490 int reg;
491
be4ab3dd 492 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
ff9f71b4 493 SETUP_IOMUX_PADS(di0_pads);
be4ab3dd 494
58cc9787
PKS		 495 enable_ipu_clock();
496 imx_setup_hdmi();
497
d9b89460 498 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
12307437 499 reg = readl(&mxc_ccm->CCGR3);
d9b89460
FE		 500 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
501 writel(reg, &mxc_ccm->CCGR3);
502
503 /* set LDB0, LDB1 clk select to 011/011 */
504 reg = readl(&mxc_ccm->cs2cdr);
505 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
506 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
507 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
508 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
509 writel(reg, &mxc_ccm->cs2cdr);
510
511 reg = readl(&mxc_ccm->cscmr2);
512 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
513 writel(reg, &mxc_ccm->cscmr2);
514
58cc9787
PKS		 515 reg = readl(&mxc_ccm->chsccdr);
516 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
517 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
d9b89460
FE		 518 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
519 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
58cc9787 520 writel(reg, &mxc_ccm->chsccdr);
d9b89460
FE		 521
522 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
523 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
524 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
525 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
526 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
527 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
528 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
529 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
530 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
531 writel(reg, &iomux->gpr[2]);
532
533 reg = readl(&iomux->gpr[3]);
534 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
535 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
536 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
537 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
538 writel(reg, &iomux->gpr[3]);
58cc9787
PKS		 539}
540#endif /* CONFIG_VIDEO_IPUV3 */
541
542/*
543 * Do not overwrite the console
544 * Use always serial for U-Boot console
545 */
546int overwrite_console(void)
547{
548 return 1;
549}
550
a0d21fc0
FE		 551int board_eth_init(bd_t *bis)
552{
a0d21fc0 553 setup_iomux_enet();
e919aa23 554 setup_pcie();
a0d21fc0 555
92c707a5 556 return cpu_eth_init(bis);
a0d21fc0
FE		 557}
558
5a3d63c5
PF		 559#ifdef CONFIG_USB_EHCI_MX6
560#define USB_OTHERREGS_OFFSET 0x800
561#define UCTRL_PWR_POL (1 << 9)
562
563static iomux_v3_cfg_t const usb_otg_pads[] = {
ff9f71b4
FE		 564 IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
565 IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
5a3d63c5
PF		 566};
567
568static iomux_v3_cfg_t const usb_hc1_pads[] = {
ff9f71b4 569 IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
5a3d63c5
PF		 570};
571
572static void setup_usb(void)
573{
ff9f71b4 574 SETUP_IOMUX_PADS(usb_otg_pads);
5a3d63c5
PF		 575
576 /*
577 * set daisy chain for otg_pin_id on 6q.
578 * for 6dl, this bit is reserved
579 */
580 imx_iomux_set_gpr_register(1, 13, 1, 0);
581
ff9f71b4 582 SETUP_IOMUX_PADS(usb_hc1_pads);
5a3d63c5
PF		 583}
584
585int board_ehci_hcd_init(int port)
586{
587 u32 *usbnc_usb_ctrl;
588
589 if (port > 1)
590 return -EINVAL;
591
592 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
593 port * 4);
594
595 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
596
597 return 0;
598}
599
600int board_ehci_power(int port, int on)
601{
602 switch (port) {
603 case 0:
604 break;
605 case 1:
606 if (on)
607 gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
608 else
609 gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
610 break;
611 default:
612 printf("MXC USB port %d not yet supported\n", port);
613 return -EINVAL;
614 }
615
616 return 0;
617}
618#endif
619
7891e258
FE		 620int board_early_init_f(void)
621{
622 setup_iomux_uart();
58cc9787
PKS		 623#if defined(CONFIG_VIDEO_IPUV3)
624 setup_display();
625#endif
7891e258
FE		 626
627 return 0;
628}
629
630int board_init(void)
631{
632 /* address of boot parameters */
633 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
634
8bfa9c69
FE		 635#ifdef CONFIG_MXC_SPI
636 setup_spi();
637#endif
ff9f71b4
FE		 638 if (is_mx6dq() || is_mx6dqp())
639 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
640 else
641 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
5a3d63c5
PF		 642#ifdef CONFIG_USB_EHCI_MX6
643 setup_usb();
644#endif
645
66ca09fc
FE		 646 return 0;
647}
648
f0fabb79 649int power_init_board(void)
66ca09fc
FE		 650{
651 struct pmic *p;
e4b984d7
FE		 652 unsigned int reg;
653 int ret;
66ca09fc 654
f0fabb79
YL		 655 p = pfuze_common_init(I2C_PMIC);
656 if (!p)
657 return -ENODEV;
66ca09fc 658
258c98f8
PF		 659 ret = pfuze_mode_init(p, APS_PFM);
660 if (ret < 0)
661 return ret;
662
66ca09fc
FE		 663 /* Increase VGEN3 from 2.5 to 2.8V */
664 pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
f0fabb79
YL		 665 reg &= ~LDO_VOL_MASK;
666 reg |= LDOB_2_80V;
66ca09fc
FE		 667 pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
668
669 /* Increase VGEN5 from 2.8 to 3V */
670 pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
f0fabb79
YL		 671 reg &= ~LDO_VOL_MASK;
672 reg |= LDOB_3_00V;
66ca09fc
FE		 673 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
674
7891e258
FE		 675 return 0;
676}
677
155fa9af
NK		 678#ifdef CONFIG_MXC_SPI
679int board_spi_cs_gpio(unsigned bus, unsigned cs)
680{
681 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
682}
683#endif
684
85449dbd
OS		 685#ifdef CONFIG_CMD_BMODE
686static const struct boot_mode board_boot_modes[] = {
687 /* 4 bit bus width */
688 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
689 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
690 /* 8 bit bus width */
214c3f0f 691 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
85449dbd
OS		 692 {NULL, 0},
693};
694#endif
695
696int board_late_init(void)
697{
698#ifdef CONFIG_CMD_BMODE
699 add_board_boot_modes(board_boot_modes);
700#endif
e6fc8995
PF		 701
702#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
703 setenv("board_name", "SABRESD");
704
e469719c
PF		 705 if (is_mx6dqp())
706 setenv("board_rev", "MX6QP");
83e13942 707 else if (is_mx6dq())
e6fc8995 708 setenv("board_rev", "MX6Q");
83e13942 709 else if (is_mx6sdl())
e6fc8995
PF		 710 setenv("board_rev", "MX6DL");
711#endif
712
85449dbd
OS		 713 return 0;
714}
715
7891e258
FE		 716int checkboard(void)
717{
c1747970 718 puts("Board: MX6-SabreSD\n");
7891e258
FE		 719 return 0;
720}
75f2ba42
JT		 721
722#ifdef CONFIG_SPL_BUILD
ff9f71b4 723#include <asm/arch/mx6-ddr.h>
75f2ba42
JT		 724#include <spl.h>
725#include <libfdt.h>
726
d96796ca
DD		 727#ifdef CONFIG_SPL_OS_BOOT
728int spl_start_uboot(void)
729{
730 gpio_direction_input(KEY_VOL_UP);
731
732 /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
733 return gpio_get_value(KEY_VOL_UP);
734}
735#endif
736
6e9b6bb5
FE		 737static void ccgr_init(void)
738{
739 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
740
741 writel(0x00C03F3F, &ccm->CCGR0);
742 writel(0x0030FC03, &ccm->CCGR1);
743 writel(0x0FFFC000, &ccm->CCGR2);
744 writel(0x3FF00000, &ccm->CCGR3);
745 writel(0x00FFF300, &ccm->CCGR4);
746 writel(0x0F0000C3, &ccm->CCGR5);
747 writel(0x000003FF, &ccm->CCGR6);
748}
749
750static void gpr_init(void)
751{
752 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
753
754 /* enable AXI cache for VDOA/VPU/IPU */
755 writel(0xF00000CF, &iomux->gpr[4]);
e469719c
PF		 756 if (is_mx6dqp()) {
757 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
758 writel(0x007F007F, &iomux->gpr[6]);
759 writel(0x007F007F, &iomux->gpr[7]);
760 } else {
761 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
762 writel(0x007F007F, &iomux->gpr[6]);
763 writel(0x007F007F, &iomux->gpr[7]);
764 }
6e9b6bb5
FE		 765}
766
3b30eece
FE		 767static int mx6q_dcd_table[] = {
768 0x020e0798, 0x000C0000,
769 0x020e0758, 0x00000000,
770 0x020e0588, 0x00000030,
771 0x020e0594, 0x00000030,
772 0x020e056c, 0x00000030,
773 0x020e0578, 0x00000030,
774 0x020e074c, 0x00000030,
775 0x020e057c, 0x00000030,
776 0x020e058c, 0x00000000,
777 0x020e059c, 0x00000030,
778 0x020e05a0, 0x00000030,
779 0x020e078c, 0x00000030,
780 0x020e0750, 0x00020000,
781 0x020e05a8, 0x00000030,
782 0x020e05b0, 0x00000030,
783 0x020e0524, 0x00000030,
784 0x020e051c, 0x00000030,
785 0x020e0518, 0x00000030,
786 0x020e050c, 0x00000030,
787 0x020e05b8, 0x00000030,
788 0x020e05c0, 0x00000030,
789 0x020e0774, 0x00020000,
790 0x020e0784, 0x00000030,
791 0x020e0788, 0x00000030,
792 0x020e0794, 0x00000030,
793 0x020e079c, 0x00000030,
794 0x020e07a0, 0x00000030,
795 0x020e07a4, 0x00000030,
796 0x020e07a8, 0x00000030,
797 0x020e0748, 0x00000030,
798 0x020e05ac, 0x00000030,
799 0x020e05b4, 0x00000030,
800 0x020e0528, 0x00000030,
801 0x020e0520, 0x00000030,
802 0x020e0514, 0x00000030,
803 0x020e0510, 0x00000030,
804 0x020e05bc, 0x00000030,
805 0x020e05c4, 0x00000030,
806 0x021b0800, 0xa1390003,
807 0x021b080c, 0x001F001F,
808 0x021b0810, 0x001F001F,
809 0x021b480c, 0x001F001F,
810 0x021b4810, 0x001F001F,
811 0x021b083c, 0x43270338,
812 0x021b0840, 0x03200314,
813 0x021b483c, 0x431A032F,
814 0x021b4840, 0x03200263,
815 0x021b0848, 0x4B434748,
816 0x021b4848, 0x4445404C,
817 0x021b0850, 0x38444542,
818 0x021b4850, 0x4935493A,
819 0x021b081c, 0x33333333,
820 0x021b0820, 0x33333333,
821 0x021b0824, 0x33333333,
822 0x021b0828, 0x33333333,
823 0x021b481c, 0x33333333,
824 0x021b4820, 0x33333333,
825 0x021b4824, 0x33333333,
826 0x021b4828, 0x33333333,
827 0x021b08b8, 0x00000800,
828 0x021b48b8, 0x00000800,
829 0x021b0004, 0x00020036,
830 0x021b0008, 0x09444040,
831 0x021b000c, 0x555A7975,
832 0x021b0010, 0xFF538F64,
833 0x021b0014, 0x01FF00DB,
834 0x021b0018, 0x00001740,
835 0x021b001c, 0x00008000,
836 0x021b002c, 0x000026d2,
837 0x021b0030, 0x005A1023,
838 0x021b0040, 0x00000027,
839 0x021b0000, 0x831A0000,
840 0x021b001c, 0x04088032,
841 0x021b001c, 0x00008033,
842 0x021b001c, 0x00048031,
843 0x021b001c, 0x09408030,
844 0x021b001c, 0x04008040,
845 0x021b0020, 0x00005800,
846 0x021b0818, 0x00011117,
847 0x021b4818, 0x00011117,
848 0x021b0004, 0x00025576,
849 0x021b0404, 0x00011006,
850 0x021b001c, 0x00000000,
851};
852
853static int mx6qp_dcd_table[] = {
854 0x020e0798, 0x000c0000,
855 0x020e0758, 0x00000000,
856 0x020e0588, 0x00000030,
857 0x020e0594, 0x00000030,
858 0x020e056c, 0x00000030,
859 0x020e0578, 0x00000030,
860 0x020e074c, 0x00000030,
861 0x020e057c, 0x00000030,
862 0x020e058c, 0x00000000,
863 0x020e059c, 0x00000030,
864 0x020e05a0, 0x00000030,
865 0x020e078c, 0x00000030,
866 0x020e0750, 0x00020000,
867 0x020e05a8, 0x00000030,
868 0x020e05b0, 0x00000030,
869 0x020e0524, 0x00000030,
870 0x020e051c, 0x00000030,
871 0x020e0518, 0x00000030,
872 0x020e050c, 0x00000030,
873 0x020e05b8, 0x00000030,
874 0x020e05c0, 0x00000030,
875 0x020e0774, 0x00020000,
876 0x020e0784, 0x00000030,
877 0x020e0788, 0x00000030,
878 0x020e0794, 0x00000030,
879 0x020e079c, 0x00000030,
880 0x020e07a0, 0x00000030,
881 0x020e07a4, 0x00000030,
882 0x020e07a8, 0x00000030,
883 0x020e0748, 0x00000030,
884 0x020e05ac, 0x00000030,
885 0x020e05b4, 0x00000030,
886 0x020e0528, 0x00000030,
887 0x020e0520, 0x00000030,
888 0x020e0514, 0x00000030,
889 0x020e0510, 0x00000030,
890 0x020e05bc, 0x00000030,
891 0x020e05c4, 0x00000030,
892 0x021b0800, 0xa1390003,
893 0x021b080c, 0x001b001e,
894 0x021b0810, 0x002e0029,
895 0x021b480c, 0x001b002a,
896 0x021b4810, 0x0019002c,
897 0x021b083c, 0x43240334,
898 0x021b0840, 0x0324031a,
899 0x021b483c, 0x43340344,
900 0x021b4840, 0x03280276,
901 0x021b0848, 0x44383A3E,
902 0x021b4848, 0x3C3C3846,
903 0x021b0850, 0x2e303230,
904 0x021b4850, 0x38283E34,
905 0x021b081c, 0x33333333,
906 0x021b0820, 0x33333333,
907 0x021b0824, 0x33333333,
908 0x021b0828, 0x33333333,
909 0x021b481c, 0x33333333,
910 0x021b4820, 0x33333333,
911 0x021b4824, 0x33333333,
912 0x021b4828, 0x33333333,
913 0x021b08c0, 0x24912249,
914 0x021b48c0, 0x24914289,
915 0x021b08b8, 0x00000800,
916 0x021b48b8, 0x00000800,
917 0x021b0004, 0x00020036,
918 0x021b0008, 0x24444040,
919 0x021b000c, 0x555A7955,
920 0x021b0010, 0xFF320F64,
921 0x021b0014, 0x01ff00db,
922 0x021b0018, 0x00001740,
923 0x021b001c, 0x00008000,
924 0x021b002c, 0x000026d2,
925 0x021b0030, 0x005A1023,
926 0x021b0040, 0x00000027,
927 0x021b0400, 0x14420000,
928 0x021b0000, 0x831A0000,
929 0x021b0890, 0x00400C58,
930 0x00bb0008, 0x00000000,
931 0x00bb000c, 0x2891E41A,
932 0x00bb0038, 0x00000564,
933 0x00bb0014, 0x00000040,
934 0x00bb0028, 0x00000020,
935 0x00bb002c, 0x00000020,
936 0x021b001c, 0x04088032,
937 0x021b001c, 0x00008033,
938 0x021b001c, 0x00048031,
939 0x021b001c, 0x09408030,
940 0x021b001c, 0x04008040,
941 0x021b0020, 0x00005800,
942 0x021b0818, 0x00011117,
943 0x021b4818, 0x00011117,
944 0x021b0004, 0x00025576,
945 0x021b0404, 0x00011006,
946 0x021b001c, 0x00000000,
947};
948
b22841e5
FE		 949static int mx6dl_dcd_table[] = {
950 0x020e0774, 0x000C0000,
951 0x020e0754, 0x00000000,
952 0x020e04ac, 0x00000030,
953 0x020e04b0, 0x00000030,
954 0x020e0464, 0x00000030,
955 0x020e0490, 0x00000030,
956 0x020e074c, 0x00000030,
957 0x020e0494, 0x00000030,
958 0x020e04a0, 0x00000000,
959 0x020e04b4, 0x00000030,
960 0x020e04b8, 0x00000030,
961 0x020e076c, 0x00000030,
962 0x020e0750, 0x00020000,
963 0x020e04bc, 0x00000030,
964 0x020e04c0, 0x00000030,
965 0x020e04c4, 0x00000030,
966 0x020e04c8, 0x00000030,
967 0x020e04cc, 0x00000030,
968 0x020e04d0, 0x00000030,
969 0x020e04d4, 0x00000030,
970 0x020e04d8, 0x00000030,
971 0x020e0760, 0x00020000,
972 0x020e0764, 0x00000030,
973 0x020e0770, 0x00000030,
974 0x020e0778, 0x00000030,
975 0x020e077c, 0x00000030,
976 0x020e0780, 0x00000030,
977 0x020e0784, 0x00000030,
978 0x020e078c, 0x00000030,
979 0x020e0748, 0x00000030,
980 0x020e0470, 0x00000030,
981 0x020e0474, 0x00000030,
982 0x020e0478, 0x00000030,
983 0x020e047c, 0x00000030,
984 0x020e0480, 0x00000030,
985 0x020e0484, 0x00000030,
986 0x020e0488, 0x00000030,
987 0x020e048c, 0x00000030,
988 0x021b0800, 0xa1390003,
989 0x021b080c, 0x001F001F,
990 0x021b0810, 0x001F001F,
991 0x021b480c, 0x001F001F,
992 0x021b4810, 0x001F001F,
993 0x021b083c, 0x4220021F,
994 0x021b0840, 0x0207017E,
995 0x021b483c, 0x4201020C,
996 0x021b4840, 0x01660172,
997 0x021b0848, 0x4A4D4E4D,
998 0x021b4848, 0x4A4F5049,
999 0x021b0850, 0x3F3C3D31,
1000 0x021b4850, 0x3238372B,
1001 0x021b081c, 0x33333333,
1002 0x021b0820, 0x33333333,
1003 0x021b0824, 0x33333333,
1004 0x021b0828, 0x33333333,
1005 0x021b481c, 0x33333333,
1006 0x021b4820, 0x33333333,
1007 0x021b4824, 0x33333333,
1008 0x021b4828, 0x33333333,
1009 0x021b08b8, 0x00000800,
1010 0x021b48b8, 0x00000800,
1011 0x021b0004, 0x0002002D,
1012 0x021b0008, 0x00333030,
1013 0x021b000c, 0x3F435313,
1014 0x021b0010, 0xB66E8B63,
1015 0x021b0014, 0x01FF00DB,
1016 0x021b0018, 0x00001740,
1017 0x021b001c, 0x00008000,
1018 0x021b002c, 0x000026d2,
1019 0x021b0030, 0x00431023,
1020 0x021b0040, 0x00000027,
1021 0x021b0000, 0x831A0000,
1022 0x021b001c, 0x04008032,
1023 0x021b001c, 0x00008033,
1024 0x021b001c, 0x00048031,
1025 0x021b001c, 0x05208030,
1026 0x021b001c, 0x04008040,
1027 0x021b0020, 0x00005800,
1028 0x021b0818, 0x00011117,
1029 0x021b4818, 0x00011117,
1030 0x021b0004, 0x0002556D,
1031 0x021b0404, 0x00011006,
1032 0x021b001c, 0x00000000,
1033};
1034
3b30eece 1035static void ddr_init(int *table, int size)
75f2ba42 1036{
3b30eece 1037 int i;
75f2ba42 1038
3b30eece
FE		 1039 for (i = 0; i < size / 2 ; i++)
1040 writel(table[2 * i + 1], table[2 * i]);
1041}
1042
1043static void spl_dram_init(void)
1044{
1045 if (is_mx6dq())
1046 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
1047 else if (is_mx6dqp())
1048 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
b22841e5
FE		 1049 else if (is_mx6sdl())
1050 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
75f2ba42
JT		 1051}
1052
1053void board_init_f(ulong dummy)
1054{
3b30eece
FE		 1055 /* DDR initialization */
1056 spl_dram_init();
1057
75f2ba42
JT		 1058 /* setup AIPS and disable watchdog */
1059 arch_cpu_init();
1060
6e9b6bb5
FE		 1061 ccgr_init();
1062 gpr_init();
1063
75f2ba42
JT		 1064 /* iomux and setup of i2c */
1065 board_early_init_f();
1066
1067 /* setup GP timer */
1068 timer_init();
1069
1070 /* UART clocks enabled and gd valid - init serial console */
1071 preloader_console_init();
1072
75f2ba42
JT		 1073 /* Clear the BSS. */
1074 memset(__bss_start, 0, __bss_end - __bss_start);
1075
1076 /* load/boot image from boot device */
1077 board_init_r(NULL, 0);
1078}
75f2ba42 1079#endif
"Das U-Boot" Source Tree