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Commit | Line | Data |
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ee52b188 YS |
1 | /* |
2 | * Copyright 2009-2012 Freescale Semiconductor, Inc. | |
3 | * | |
3aab0cd8 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
ee52b188 YS |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <command.h> | |
9 | #include <i2c.h> | |
10 | #include <netdev.h> | |
11 | #include <linux/compiler.h> | |
12 | #include <asm/mmu.h> | |
13 | #include <asm/processor.h> | |
14 | #include <asm/cache.h> | |
15 | #include <asm/immap_85xx.h> | |
16 | #include <asm/fsl_law.h> | |
17 | #include <asm/fsl_serdes.h> | |
ee52b188 YS |
18 | #include <asm/fsl_liodn.h> |
19 | #include <fm_eth.h> | |
20 | ||
21 | #include "../common/qixis.h" | |
22 | #include "../common/vsc3316_3308.h" | |
23 | #include "t4qds.h" | |
24 | #include "t4240qds_qixis.h" | |
25 | ||
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
7d0d355f | 28 | static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7}, |
de757a7a TT |
29 | {8, 8}, {9, 9}, {14, 14}, {15, 15} }; |
30 | ||
7d0d355f | 31 | static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5}, |
de757a7a TT |
32 | {10, 10}, {11, 11}, {12, 12}, {13, 13} }; |
33 | ||
7d0d355f | 34 | static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4}, |
de757a7a TT |
35 | {10, 11}, {11, 10}, {12, 2}, {13, 3} }; |
36 | ||
7d0d355f | 37 | static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6}, |
de757a7a TT |
38 | {8, 9}, {9, 8}, {14, 1}, {15, 0} }; |
39 | ||
ee52b188 YS |
40 | int checkboard(void) |
41 | { | |
afa2b72b | 42 | char buf[64]; |
ee52b188 | 43 | u8 sw; |
67ac13b1 | 44 | struct cpu_type *cpu = gd->arch.cpu; |
ee52b188 YS |
45 | unsigned int i; |
46 | ||
47 | printf("Board: %sQDS, ", cpu->name); | |
afa2b72b | 48 | printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", |
1cb19fbb | 49 | QIXIS_READ(id), QIXIS_READ(arch)); |
ee52b188 YS |
50 | |
51 | sw = QIXIS_READ(brdcfg[0]); | |
52 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; | |
53 | ||
54 | if (sw < 0x8) | |
55 | printf("vBank: %d\n", sw); | |
56 | else if (sw == 0x8) | |
57 | puts("Promjet\n"); | |
58 | else if (sw == 0x9) | |
59 | puts("NAND\n"); | |
60 | else | |
61 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); | |
62 | ||
afa2b72b | 63 | printf("FPGA: v%d (%s), build %d", |
1cb19fbb YS |
64 | (int)QIXIS_READ(scver), qixis_read_tag(buf), |
65 | (int)qixis_read_minor()); | |
afa2b72b PK |
66 | /* the timestamp string contains "\n" at the end */ |
67 | printf(" on %s", qixis_read_time(buf)); | |
68 | ||
ee52b188 YS |
69 | /* |
70 | * Display the actual SERDES reference clocks as configured by the | |
71 | * dip switches on the board. Note that the SWx registers could | |
72 | * technically be set to force the reference clocks to match the | |
73 | * values that the SERDES expects (or vice versa). For now, however, | |
74 | * we just display both values and hope the user notices when they | |
75 | * don't match. | |
76 | */ | |
77 | puts("SERDES Reference Clocks: "); | |
78 | sw = QIXIS_READ(brdcfg[2]); | |
79 | for (i = 0; i < MAX_SERDES; i++) { | |
1cb19fbb | 80 | static const char * const freq[] = { |
ee52b188 | 81 | "100", "125", "156.25", "161.1328125"}; |
9458f6d8 | 82 | unsigned int clock = (sw >> (6 - 2 * i)) & 3; |
ee52b188 YS |
83 | |
84 | printf("SERDES%u=%sMHz ", i+1, freq[clock]); | |
85 | } | |
86 | puts("\n"); | |
87 | ||
88 | return 0; | |
89 | } | |
90 | ||
91 | int select_i2c_ch_pca9547(u8 ch) | |
92 | { | |
93 | int ret; | |
94 | ||
95 | ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); | |
96 | if (ret) { | |
97 | puts("PCA: failed to select proper channel\n"); | |
98 | return ret; | |
99 | } | |
100 | ||
101 | return 0; | |
102 | } | |
103 | ||
97c7fe61 YS |
104 | /* |
105 | * read_voltage from sensor on I2C bus | |
106 | * We use average of 4 readings, waiting for 532us befor another reading | |
107 | */ | |
108 | #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ | |
109 | #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ | |
110 | ||
111 | static inline int read_voltage(void) | |
112 | { | |
113 | int i, ret, voltage_read = 0; | |
114 | u16 vol_mon; | |
115 | ||
116 | for (i = 0; i < NUM_READINGS; i++) { | |
117 | ret = i2c_read(I2C_VOL_MONITOR_ADDR, | |
118 | I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); | |
119 | if (ret) { | |
120 | printf("VID: failed to read core voltage\n"); | |
121 | return ret; | |
122 | } | |
123 | if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { | |
124 | printf("VID: Core voltage sensor error\n"); | |
125 | return -1; | |
126 | } | |
127 | debug("VID: bus voltage reads 0x%04x\n", vol_mon); | |
128 | /* LSB = 4mv */ | |
129 | voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; | |
130 | udelay(WAIT_FOR_ADC); | |
131 | } | |
132 | /* calculate the average */ | |
133 | voltage_read /= NUM_READINGS; | |
134 | ||
135 | return voltage_read; | |
136 | } | |
137 | ||
138 | /* | |
139 | * We need to calculate how long before the voltage starts to drop or increase | |
140 | * It returns with the loop count. Each loop takes several readings (532us) | |
141 | */ | |
142 | static inline int wait_for_voltage_change(int vdd_last) | |
143 | { | |
144 | int timeout, vdd_current; | |
145 | ||
146 | vdd_current = read_voltage(); | |
147 | /* wait until voltage starts to drop */ | |
148 | for (timeout = 0; abs(vdd_last - vdd_current) <= 4 && | |
149 | timeout < 100; timeout++) { | |
150 | vdd_current = read_voltage(); | |
151 | } | |
152 | if (timeout >= 100) { | |
153 | printf("VID: Voltage adjustment timeout\n"); | |
154 | return -1; | |
155 | } | |
156 | return timeout; | |
157 | } | |
158 | ||
159 | /* | |
160 | * argument 'wait' is the time we know the voltage difference can be measured | |
161 | * this function keeps reading the voltage until it is stable | |
162 | */ | |
163 | static inline int wait_for_voltage_stable(int wait) | |
164 | { | |
165 | int timeout, vdd_current, vdd_last; | |
166 | ||
167 | vdd_last = read_voltage(); | |
168 | udelay(wait * NUM_READINGS * WAIT_FOR_ADC); | |
169 | /* wait until voltage is stable */ | |
170 | vdd_current = read_voltage(); | |
171 | for (timeout = 0; abs(vdd_last - vdd_current) >= 4 && | |
172 | timeout < 100; timeout++) { | |
173 | vdd_last = vdd_current; | |
174 | udelay(wait * NUM_READINGS * WAIT_FOR_ADC); | |
175 | vdd_current = read_voltage(); | |
176 | } | |
177 | if (timeout >= 100) { | |
178 | printf("VID: Voltage adjustment timeout\n"); | |
179 | return -1; | |
180 | } | |
181 | ||
182 | return vdd_current; | |
183 | } | |
184 | ||
185 | static inline int set_voltage(u8 vid) | |
186 | { | |
187 | int wait, vdd_last; | |
188 | ||
189 | vdd_last = read_voltage(); | |
190 | QIXIS_WRITE(brdcfg[6], vid); | |
191 | wait = wait_for_voltage_change(vdd_last); | |
192 | if (wait < 0) | |
193 | return -1; | |
194 | debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC); | |
195 | wait = wait ? wait : 1; | |
196 | ||
197 | vdd_last = wait_for_voltage_stable(wait); | |
198 | if (vdd_last < 0) | |
199 | return -1; | |
200 | debug("VID: Current voltage is %d mV\n", vdd_last); | |
201 | ||
202 | return vdd_last; | |
203 | } | |
204 | ||
205 | ||
0aadf4aa | 206 | static int adjust_vdd(ulong vdd_override) |
97c7fe61 YS |
207 | { |
208 | int re_enable = disable_interrupts(); | |
209 | ccsr_gur_t __iomem *gur = | |
210 | (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
211 | u32 fusesr; | |
212 | u8 vid, vid_current; | |
213 | int vdd_target, vdd_current, vdd_last; | |
214 | int ret; | |
0aadf4aa YS |
215 | unsigned long vdd_string_override; |
216 | char *vdd_string; | |
97c7fe61 YS |
217 | static const uint16_t vdd[32] = { |
218 | 0, /* unused */ | |
219 | 9875, /* 0.9875V */ | |
220 | 9750, | |
221 | 9625, | |
222 | 9500, | |
223 | 9375, | |
224 | 9250, | |
225 | 9125, | |
226 | 9000, | |
227 | 8875, | |
228 | 8750, | |
229 | 8625, | |
230 | 8500, | |
231 | 8375, | |
232 | 8250, | |
233 | 8125, | |
234 | 10000, /* 1.0000V */ | |
235 | 10125, | |
236 | 10250, | |
237 | 10375, | |
238 | 10500, | |
239 | 10625, | |
240 | 10750, | |
241 | 10875, | |
242 | 11000, | |
243 | 0, /* reserved */ | |
244 | }; | |
245 | struct vdd_drive { | |
246 | u8 vid; | |
247 | unsigned voltage; | |
248 | }; | |
249 | ||
250 | ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR); | |
251 | if (ret) { | |
252 | debug("VID: I2c failed to switch channel\n"); | |
253 | ret = -1; | |
254 | goto exit; | |
255 | } | |
256 | ||
257 | /* get the voltage ID from fuse status register */ | |
258 | fusesr = in_be32(&gur->dcfg_fusesr); | |
259 | vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & | |
260 | FSL_CORENET_DCFG_FUSESR_VID_MASK; | |
261 | if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { | |
262 | vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & | |
263 | FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; | |
264 | } | |
265 | vdd_target = vdd[vid]; | |
0aadf4aa YS |
266 | |
267 | /* check override variable for overriding VDD */ | |
00caae6d | 268 | vdd_string = env_get("t4240qds_vdd_mv"); |
0aadf4aa YS |
269 | if (vdd_override == 0 && vdd_string && |
270 | !strict_strtoul(vdd_string, 10, &vdd_string_override)) | |
271 | vdd_override = vdd_string_override; | |
272 | if (vdd_override >= 819 && vdd_override <= 1212) { | |
273 | vdd_target = vdd_override * 10; /* convert to 1/10 mV */ | |
274 | debug("VDD override is %lu\n", vdd_override); | |
275 | } else if (vdd_override != 0) { | |
276 | printf("Invalid value.\n"); | |
277 | } | |
278 | ||
97c7fe61 YS |
279 | if (vdd_target == 0) { |
280 | debug("VID: VID not used\n"); | |
281 | ret = 0; | |
282 | goto exit; | |
283 | } else { | |
284 | /* round up and divice by 10 to get a value in mV */ | |
285 | vdd_target = DIV_ROUND_UP(vdd_target, 10); | |
286 | debug("VID: vid = %d mV\n", vdd_target); | |
287 | } | |
288 | ||
289 | /* | |
290 | * Check current board VID setting | |
291 | * Voltage regulator support output to 6.250mv step | |
292 | * The highes voltage allowed for this board is (vid=0x40) 1.21250V | |
293 | * the lowest is (vid=0x7f) 0.81875V | |
294 | */ | |
295 | vid_current = QIXIS_READ(brdcfg[6]); | |
296 | vdd_current = 121250 - (vid_current - 0x40) * 625; | |
297 | debug("VID: Current vid setting is (0x%x) %d mV\n", | |
298 | vid_current, vdd_current/100); | |
299 | ||
300 | /* | |
301 | * Read voltage monitor to check real voltage. | |
302 | * Voltage monitor LSB is 4mv. | |
303 | */ | |
304 | vdd_last = read_voltage(); | |
305 | if (vdd_last < 0) { | |
306 | printf("VID: Could not read voltage sensor abort VID adjustment\n"); | |
307 | ret = -1; | |
308 | goto exit; | |
309 | } | |
310 | debug("VID: Core voltage is at %d mV\n", vdd_last); | |
311 | /* | |
312 | * Adjust voltage to at or 8mV above target. | |
313 | * Each step of adjustment is 6.25mV. | |
314 | * Stepping down too fast may cause over current. | |
315 | */ | |
316 | while (vdd_last > 0 && vid_current < 0x80 && | |
317 | vdd_last > (vdd_target + 8)) { | |
318 | vid_current++; | |
319 | vdd_last = set_voltage(vid_current); | |
320 | } | |
321 | /* | |
322 | * Check if we need to step up | |
323 | * This happens when board voltage switch was set too low | |
324 | */ | |
325 | while (vdd_last > 0 && vid_current >= 0x40 && | |
326 | vdd_last < vdd_target + 2) { | |
327 | vid_current--; | |
328 | vdd_last = set_voltage(vid_current); | |
329 | } | |
330 | if (vdd_last > 0) | |
331 | printf("VID: Core voltage %d mV\n", vdd_last); | |
332 | else | |
333 | ret = -1; | |
334 | ||
335 | exit: | |
336 | if (re_enable) | |
337 | enable_interrupts(); | |
338 | return ret; | |
339 | } | |
340 | ||
ee52b188 YS |
341 | /* Configure Crossbar switches for Front-Side SerDes Ports */ |
342 | int config_frontside_crossbar_vsc3316(void) | |
343 | { | |
344 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
345 | u32 srds_prtcl_s1, srds_prtcl_s2; | |
346 | int ret; | |
347 | ||
348 | ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS); | |
349 | if (ret) | |
350 | return ret; | |
351 | ||
352 | srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & | |
353 | FSL_CORENET2_RCWSR4_SRDS1_PRTCL; | |
354 | srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; | |
ae3dcd04 | 355 | switch (srds_prtcl_s1) { |
94752f60 | 356 | case 37: |
ae3dcd04 SX |
357 | case 38: |
358 | /* swap first lane and third lane on slot1 */ | |
359 | vsc3316_fsm1_tx[0][1] = 14; | |
360 | vsc3316_fsm1_tx[6][1] = 0; | |
361 | vsc3316_fsm1_rx[1][1] = 2; | |
362 | vsc3316_fsm1_rx[6][1] = 13; | |
94752f60 | 363 | case 39: |
ae3dcd04 | 364 | case 40: |
94752f60 | 365 | case 45: |
ae3dcd04 | 366 | case 46: |
94752f60 | 367 | case 47: |
ae3dcd04 SX |
368 | case 48: |
369 | /* swap first lane and third lane on slot2 */ | |
370 | vsc3316_fsm1_tx[2][1] = 8; | |
371 | vsc3316_fsm1_tx[4][1] = 6; | |
372 | vsc3316_fsm1_rx[2][1] = 10; | |
373 | vsc3316_fsm1_rx[5][1] = 5; | |
374 | default: | |
ee52b188 YS |
375 | ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8); |
376 | if (ret) | |
377 | return ret; | |
378 | ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8); | |
379 | if (ret) | |
380 | return ret; | |
ae3dcd04 | 381 | break; |
ee52b188 YS |
382 | } |
383 | ||
384 | srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & | |
385 | FSL_CORENET2_RCWSR4_SRDS2_PRTCL; | |
386 | srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; | |
ae3dcd04 | 387 | switch (srds_prtcl_s2) { |
94752f60 | 388 | case 37: |
ae3dcd04 SX |
389 | case 38: |
390 | /* swap first lane and third lane on slot3 */ | |
391 | vsc3316_fsm2_tx[2][1] = 11; | |
392 | vsc3316_fsm2_tx[5][1] = 4; | |
393 | vsc3316_fsm2_rx[2][1] = 9; | |
394 | vsc3316_fsm2_rx[4][1] = 7; | |
94752f60 | 395 | case 39: |
ae3dcd04 | 396 | case 40: |
94752f60 | 397 | case 45: |
ae3dcd04 | 398 | case 46: |
94752f60 | 399 | case 47: |
ae3dcd04 | 400 | case 48: |
94752f60 | 401 | case 49: |
ae3dcd04 | 402 | case 50: |
94752f60 | 403 | case 51: |
ae3dcd04 | 404 | case 52: |
94752f60 | 405 | case 53: |
ae3dcd04 SX |
406 | case 54: |
407 | /* swap first lane and third lane on slot4 */ | |
408 | vsc3316_fsm2_tx[6][1] = 3; | |
409 | vsc3316_fsm2_tx[1][1] = 12; | |
410 | vsc3316_fsm2_rx[0][1] = 1; | |
411 | vsc3316_fsm2_rx[6][1] = 15; | |
412 | default: | |
ee52b188 YS |
413 | ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8); |
414 | if (ret) | |
415 | return ret; | |
416 | ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8); | |
417 | if (ret) | |
418 | return ret; | |
ae3dcd04 | 419 | break; |
ee52b188 YS |
420 | } |
421 | ||
422 | return 0; | |
423 | } | |
424 | ||
425 | int config_backside_crossbar_mux(void) | |
426 | { | |
427 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); | |
428 | u32 srds_prtcl_s3, srds_prtcl_s4; | |
429 | u8 brdcfg; | |
430 | ||
431 | srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & | |
432 | FSL_CORENET2_RCWSR4_SRDS3_PRTCL; | |
433 | srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; | |
434 | switch (srds_prtcl_s3) { | |
435 | case 0: | |
436 | /* SerDes3 is not enabled */ | |
437 | break; | |
94752f60 | 438 | case 1: |
ee52b188 YS |
439 | case 2: |
440 | case 9: | |
441 | case 10: | |
442 | /* SD3(0:7) => SLOT5(0:7) */ | |
443 | brdcfg = QIXIS_READ(brdcfg[12]); | |
444 | brdcfg &= ~BRDCFG12_SD3MX_MASK; | |
445 | brdcfg |= BRDCFG12_SD3MX_SLOT5; | |
446 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
447 | break; | |
94752f60 | 448 | case 3: |
ee52b188 | 449 | case 4: |
94752f60 | 450 | case 5: |
ee52b188 | 451 | case 6: |
94752f60 | 452 | case 7: |
ee52b188 | 453 | case 8: |
94752f60 | 454 | case 11: |
ee52b188 | 455 | case 12: |
94752f60 | 456 | case 13: |
ee52b188 | 457 | case 14: |
94752f60 | 458 | case 15: |
ee52b188 YS |
459 | case 16: |
460 | case 17: | |
94752f60 | 461 | case 18: |
ee52b188 YS |
462 | case 19: |
463 | case 20: | |
464 | /* SD3(4:7) => SLOT6(0:3) */ | |
465 | brdcfg = QIXIS_READ(brdcfg[12]); | |
466 | brdcfg &= ~BRDCFG12_SD3MX_MASK; | |
467 | brdcfg |= BRDCFG12_SD3MX_SLOT6; | |
468 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
469 | break; | |
470 | default: | |
471 | printf("WARNING: unsupported for SerDes3 Protocol %d\n", | |
1cb19fbb | 472 | srds_prtcl_s3); |
ee52b188 YS |
473 | return -1; |
474 | } | |
475 | ||
476 | srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & | |
477 | FSL_CORENET2_RCWSR4_SRDS4_PRTCL; | |
478 | srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; | |
479 | switch (srds_prtcl_s4) { | |
480 | case 0: | |
481 | /* SerDes4 is not enabled */ | |
482 | break; | |
94752f60 | 483 | case 1: |
ee52b188 YS |
484 | case 2: |
485 | /* 10b, SD4(0:7) => SLOT7(0:7) */ | |
486 | brdcfg = QIXIS_READ(brdcfg[12]); | |
487 | brdcfg &= ~BRDCFG12_SD4MX_MASK; | |
488 | brdcfg |= BRDCFG12_SD4MX_SLOT7; | |
489 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
490 | break; | |
94752f60 | 491 | case 3: |
ee52b188 | 492 | case 4: |
94752f60 | 493 | case 5: |
ee52b188 | 494 | case 6: |
94752f60 | 495 | case 7: |
ee52b188 YS |
496 | case 8: |
497 | /* x1b, SD4(4:7) => SLOT8(0:3) */ | |
498 | brdcfg = QIXIS_READ(brdcfg[12]); | |
499 | brdcfg &= ~BRDCFG12_SD4MX_MASK; | |
500 | brdcfg |= BRDCFG12_SD4MX_SLOT8; | |
501 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
502 | break; | |
94752f60 | 503 | case 9: |
ee52b188 | 504 | case 10: |
94752f60 | 505 | case 11: |
ee52b188 | 506 | case 12: |
94752f60 | 507 | case 13: |
ee52b188 | 508 | case 14: |
94752f60 | 509 | case 15: |
ee52b188 YS |
510 | case 16: |
511 | case 18: | |
512 | /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */ | |
513 | brdcfg = QIXIS_READ(brdcfg[12]); | |
514 | brdcfg &= ~BRDCFG12_SD4MX_MASK; | |
515 | brdcfg |= BRDCFG12_SD4MX_AURO_SATA; | |
516 | QIXIS_WRITE(brdcfg[12], brdcfg); | |
517 | break; | |
518 | default: | |
519 | printf("WARNING: unsupported for SerDes4 Protocol %d\n", | |
1cb19fbb | 520 | srds_prtcl_s4); |
ee52b188 YS |
521 | return -1; |
522 | } | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | int board_early_init_r(void) | |
528 | { | |
529 | const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; | |
9d045682 | 530 | int flash_esel = find_tlb_idx((void *)flashbase, 1); |
ee52b188 YS |
531 | |
532 | /* | |
533 | * Remap Boot flash + PROMJET region to caching-inhibited | |
534 | * so that flash can be erased properly. | |
535 | */ | |
536 | ||
537 | /* Flush d-cache and invalidate i-cache of any FLASH data */ | |
538 | flush_dcache(); | |
539 | invalidate_icache(); | |
540 | ||
9d045682 YS |
541 | if (flash_esel == -1) { |
542 | /* very unlikely unless something is messed up */ | |
543 | puts("Error: Could not find TLB for FLASH BASE\n"); | |
544 | flash_esel = 2; /* give our best effort to continue */ | |
545 | } else { | |
546 | /* invalidate existing TLB entry for flash + promjet */ | |
547 | disable_tlb(flash_esel); | |
548 | } | |
ee52b188 YS |
549 | |
550 | set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, | |
1cb19fbb YS |
551 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
552 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); | |
ee52b188 | 553 | |
9c0a6de2 ES |
554 | /* Disable remote I2C connection to qixis fpga */ |
555 | QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE); | |
ee52b188 | 556 | |
97c7fe61 YS |
557 | /* |
558 | * Adjust core voltage according to voltage ID | |
559 | * This function changes I2C mux to channel 2. | |
560 | */ | |
0aadf4aa | 561 | if (adjust_vdd(0)) |
97c7fe61 YS |
562 | printf("Warning: Adjusting core voltage failed.\n"); |
563 | ||
ee52b188 YS |
564 | /* Configure board SERDES ports crossbar */ |
565 | config_frontside_crossbar_vsc3316(); | |
566 | config_backside_crossbar_mux(); | |
567 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); | |
568 | ||
569 | return 0; | |
570 | } | |
571 | ||
572 | unsigned long get_board_sys_clk(void) | |
573 | { | |
574 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); | |
f4138815 ES |
575 | #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT |
576 | /* use accurate clock measurement */ | |
577 | int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]); | |
578 | int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); | |
579 | u32 val; | |
580 | ||
581 | val = freq * base; | |
582 | if (val) { | |
583 | debug("SYS Clock measurement is: %d\n", val); | |
584 | return val; | |
585 | } else { | |
586 | printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n"); | |
587 | } | |
588 | #endif | |
ee52b188 YS |
589 | |
590 | switch (sysclk_conf & 0x0F) { | |
591 | case QIXIS_SYSCLK_83: | |
592 | return 83333333; | |
593 | case QIXIS_SYSCLK_100: | |
594 | return 100000000; | |
595 | case QIXIS_SYSCLK_125: | |
596 | return 125000000; | |
597 | case QIXIS_SYSCLK_133: | |
598 | return 133333333; | |
599 | case QIXIS_SYSCLK_150: | |
600 | return 150000000; | |
601 | case QIXIS_SYSCLK_160: | |
602 | return 160000000; | |
603 | case QIXIS_SYSCLK_166: | |
604 | return 166666666; | |
605 | } | |
606 | return 66666666; | |
607 | } | |
608 | ||
609 | unsigned long get_board_ddr_clk(void) | |
610 | { | |
611 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); | |
f4138815 ES |
612 | #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT |
613 | /* use accurate clock measurement */ | |
614 | int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]); | |
615 | int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]); | |
616 | u32 val; | |
617 | ||
618 | val = freq * base; | |
619 | if (val) { | |
620 | debug("DDR Clock measurement is: %d\n", val); | |
621 | return val; | |
622 | } else { | |
623 | printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n"); | |
624 | } | |
625 | #endif | |
ee52b188 YS |
626 | |
627 | switch ((ddrclk_conf & 0x30) >> 4) { | |
628 | case QIXIS_DDRCLK_100: | |
629 | return 100000000; | |
630 | case QIXIS_DDRCLK_125: | |
631 | return 125000000; | |
632 | case QIXIS_DDRCLK_133: | |
633 | return 133333333; | |
634 | } | |
635 | return 66666666; | |
636 | } | |
637 | ||
ee52b188 YS |
638 | int misc_init_r(void) |
639 | { | |
640 | u8 sw; | |
e55782ec SX |
641 | void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; |
642 | serdes_corenet_t *srds_regs; | |
ee52b188 | 643 | u32 actual[MAX_SERDES]; |
e55782ec | 644 | u32 pllcr0, expected; |
ee52b188 YS |
645 | unsigned int i; |
646 | ||
647 | sw = QIXIS_READ(brdcfg[2]); | |
648 | for (i = 0; i < MAX_SERDES; i++) { | |
9458f6d8 | 649 | unsigned int clock = (sw >> (6 - 2 * i)) & 3; |
ee52b188 YS |
650 | switch (clock) { |
651 | case 0: | |
652 | actual[i] = SRDS_PLLCR0_RFCK_SEL_100; | |
653 | break; | |
654 | case 1: | |
655 | actual[i] = SRDS_PLLCR0_RFCK_SEL_125; | |
656 | break; | |
657 | case 2: | |
658 | actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; | |
659 | break; | |
660 | case 3: | |
661 | actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13; | |
662 | break; | |
663 | } | |
664 | } | |
665 | ||
666 | for (i = 0; i < MAX_SERDES; i++) { | |
e55782ec SX |
667 | srds_regs = srds_base + i * 0x1000; |
668 | pllcr0 = srds_regs->bank[0].pllcr0; | |
669 | expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; | |
ee52b188 | 670 | if (expected != actual[i]) { |
1cb19fbb YS |
671 | printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n", |
672 | i + 1, serdes_clock_to_string(expected), | |
ee52b188 YS |
673 | serdes_clock_to_string(actual[i])); |
674 | } | |
675 | } | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
e895a4b0 | 680 | int ft_board_setup(void *blob, bd_t *bd) |
ee52b188 YS |
681 | { |
682 | phys_addr_t base; | |
683 | phys_size_t size; | |
684 | ||
685 | ft_cpu_setup(blob, bd); | |
686 | ||
723806cc SG |
687 | base = env_get_bootm_low(); |
688 | size = env_get_bootm_size(); | |
ee52b188 YS |
689 | |
690 | fdt_fixup_memory(blob, (u64)base, (u64)size); | |
691 | ||
692 | #ifdef CONFIG_PCI | |
693 | pci_of_setup(blob, bd); | |
694 | #endif | |
695 | ||
696 | fdt_fixup_liodn(blob); | |
a5c289b9 | 697 | fsl_fdt_fixup_dr_usb(blob, bd); |
ee52b188 YS |
698 | |
699 | #ifdef CONFIG_SYS_DPAA_FMAN | |
700 | fdt_fixup_fman_ethernet(blob); | |
701 | fdt_fixup_board_enet(blob); | |
702 | #endif | |
e895a4b0 SG |
703 | |
704 | return 0; | |
ee52b188 | 705 | } |
4457e3e6 | 706 | |
9cefbd64 YS |
707 | /* |
708 | * This function is called by bdinfo to print detail board information. | |
709 | * As an exmaple for future board, we organize the messages into | |
710 | * several sections. If applicable, the message is in the format of | |
711 | * <name> = <value> | |
712 | * It should aligned with normal output of bdinfo command. | |
713 | * | |
714 | * Voltage: Core, DDR and another configurable voltages | |
715 | * Clock : Critical clocks which are not printed already | |
716 | * RCW : RCW source if not printed already | |
717 | * Misc : Other important information not in above catagories | |
718 | */ | |
719 | void board_detail(void) | |
720 | { | |
721 | int i; | |
722 | u8 brdcfg[16], dutcfg[16], rst_ctl; | |
723 | int vdd, rcwsrc; | |
724 | static const char * const clk[] = {"66.67", "100", "125", "133.33"}; | |
725 | ||
726 | for (i = 0; i < 16; i++) { | |
727 | brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); | |
728 | dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); | |
729 | } | |
730 | ||
731 | /* Voltage secion */ | |
732 | if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) { | |
733 | vdd = read_voltage(); | |
734 | if (vdd > 0) | |
735 | printf("Core voltage= %d mV\n", vdd); | |
736 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); | |
737 | } | |
738 | ||
739 | printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25); | |
740 | ||
741 | /* clock section */ | |
742 | printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n", | |
743 | clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]); | |
744 | ||
745 | /* RCW section */ | |
746 | rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1); | |
747 | puts("RCW source = "); | |
748 | switch (rcwsrc) { | |
749 | case 0x017: | |
750 | case 0x01f: | |
751 | puts("8-bit NOR\n"); | |
752 | break; | |
753 | case 0x027: | |
754 | case 0x02F: | |
755 | puts("16-bit NOR\n"); | |
756 | break; | |
757 | case 0x040: | |
758 | puts("SDHC/eMMC\n"); | |
759 | break; | |
760 | case 0x044: | |
761 | puts("SPI 16-bit addressing\n"); | |
762 | break; | |
763 | case 0x045: | |
764 | puts("SPI 24-bit addressing\n"); | |
765 | break; | |
766 | case 0x048: | |
767 | puts("I2C normal addressing\n"); | |
768 | break; | |
769 | case 0x049: | |
770 | puts("I2C extended addressing\n"); | |
771 | break; | |
772 | case 0x108: | |
773 | case 0x109: | |
774 | case 0x10a: | |
775 | case 0x10b: | |
776 | puts("8-bit NAND, 2KB\n"); | |
777 | break; | |
778 | default: | |
779 | if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f)) | |
780 | puts("Hard-coded RCW\n"); | |
781 | else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f)) | |
782 | puts("8-bit NAND, 4KB\n"); | |
783 | else | |
784 | puts("unknown\n"); | |
785 | break; | |
786 | } | |
787 | ||
788 | /* Misc section */ | |
789 | rst_ctl = QIXIS_READ(rst_ctl); | |
790 | puts("HRESET_REQ = "); | |
791 | switch (rst_ctl & 0x30) { | |
792 | case 0x00: | |
793 | puts("Ignored\n"); | |
794 | break; | |
795 | case 0x10: | |
796 | puts("Assert HRESET\n"); | |
797 | break; | |
798 | case 0x30: | |
799 | puts("Reset system\n"); | |
800 | break; | |
801 | default: | |
802 | puts("N/A\n"); | |
803 | break; | |
804 | } | |
805 | } | |
806 | ||
4457e3e6 SL |
807 | /* |
808 | * Reverse engineering switch settings. | |
809 | * Some bits cannot be figured out. They will be displayed as | |
810 | * underscore in binary format. mask[] has those bits. | |
811 | * Some bits are calculated differently than the actual switches | |
812 | * if booting with overriding by FPGA. | |
813 | */ | |
814 | void qixis_dump_switch(void) | |
815 | { | |
816 | int i; | |
817 | u8 sw[9]; | |
818 | ||
819 | /* | |
820 | * Any bit with 1 means that bit cannot be reverse engineered. | |
821 | * It will be displayed as _ in binary format. | |
822 | */ | |
e1379b07 | 823 | static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f}; |
4457e3e6 SL |
824 | char buf[10]; |
825 | u8 brdcfg[16], dutcfg[16]; | |
826 | ||
827 | for (i = 0; i < 16; i++) { | |
828 | brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); | |
829 | dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); | |
830 | } | |
831 | ||
832 | sw[0] = dutcfg[0]; | |
1cb19fbb YS |
833 | sw[1] = (dutcfg[1] << 0x07) | |
834 | ((dutcfg[12] & 0xC0) >> 1) | | |
835 | ((dutcfg[11] & 0xE0) >> 3) | | |
836 | ((dutcfg[6] & 0x80) >> 6) | | |
4457e3e6 | 837 | ((dutcfg[1] & 0x80) >> 7); |
1cb19fbb YS |
838 | sw[2] = ((brdcfg[1] & 0x0f) << 4) | |
839 | ((brdcfg[1] & 0x30) >> 2) | | |
840 | ((brdcfg[1] & 0x40) >> 5) | | |
4457e3e6 SL |
841 | ((brdcfg[1] & 0x80) >> 7); |
842 | sw[3] = brdcfg[2]; | |
1cb19fbb YS |
843 | sw[4] = ((dutcfg[2] & 0x01) << 7) | |
844 | ((dutcfg[2] & 0x06) << 4) | | |
845 | ((~QIXIS_READ(present)) & 0x10) | | |
846 | ((brdcfg[3] & 0x80) >> 4) | | |
847 | ((brdcfg[3] & 0x01) << 2) | | |
848 | ((brdcfg[6] == 0x62) ? 3 : | |
849 | ((brdcfg[6] == 0x5a) ? 2 : | |
4457e3e6 | 850 | ((brdcfg[6] == 0x5e) ? 1 : 0))); |
1cb19fbb YS |
851 | sw[5] = ((brdcfg[0] & 0x0f) << 4) | |
852 | ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | | |
4457e3e6 | 853 | ((brdcfg[0] & 0x40) >> 5); |
e1379b07 YS |
854 | sw[6] = (brdcfg[11] & 0x20) | |
855 | ((brdcfg[5] & 0x02) << 3); | |
1cb19fbb | 856 | sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | |
4457e3e6 | 857 | ((brdcfg[5] & 0x10) << 2); |
1cb19fbb | 858 | sw[8] = ((brdcfg[12] & 0x08) << 4) | |
4457e3e6 SL |
859 | ((brdcfg[12] & 0x03) << 5); |
860 | ||
861 | puts("DIP switch (reverse-engineering)\n"); | |
862 | for (i = 0; i < 9; i++) { | |
863 | printf("SW%d = 0b%s (0x%02x)\n", | |
1cb19fbb | 864 | i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); |
4457e3e6 SL |
865 | } |
866 | } | |
0aadf4aa | 867 | |
1cb19fbb YS |
868 | static int do_vdd_adjust(cmd_tbl_t *cmdtp, |
869 | int flag, int argc, | |
870 | char * const argv[]) | |
0aadf4aa YS |
871 | { |
872 | ulong override; | |
873 | ||
874 | if (argc < 2) | |
875 | return CMD_RET_USAGE; | |
876 | if (!strict_strtoul(argv[1], 10, &override)) | |
877 | adjust_vdd(override); /* the value is checked by callee */ | |
878 | else | |
879 | return CMD_RET_USAGE; | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | U_BOOT_CMD( | |
885 | vdd_override, 2, 0, do_vdd_adjust, | |
886 | "Override VDD", | |
887 | "- override with the voltage specified in mV, eg. 1050" | |
888 | ); |