[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana_spl.c

/*
 * Copyright (C) 2014 Gateworks Corporation
 * Author: Tim Harvey <tharvey@gateworks.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <environment.h>
#include <i2c.h>
#include <spl.h>

#include "gsc.h"
#include "common.h"

DECLARE_GLOBAL_DATA_PTR;

#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
#define GSC_EEPROM_DDR_SIZE	0x2B	/* enum (512,1024,2048) MB */
#define GSC_EEPROM_DDR_WIDTH	0x2D	/* enum (32,64) bit */

/* configure MX6Q/DUAL mmdc DDR io registers */
struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	.dram_sdclk_0 = 0x00020030,
	.dram_sdclk_1 = 0x00020030,
	.dram_cas = 0x00020030,
	.dram_ras = 0x00020030,
	.dram_reset = 0x00020030,
	/* SDCKE[0:1]: 100k pull-up */
	.dram_sdcke0 = 0x00003000,
	.dram_sdcke1 = 0x00003000,
	/* SDBA2: pull-up disabled */
	.dram_sdba2 = 0x00000000,
	/* SDODT[0:1]: 100k pull-up, 40 ohm */
	.dram_sdodt0 = 0x00003030,
	.dram_sdodt1 = 0x00003030,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.dram_sdqs0 = 0x00000030,
	.dram_sdqs1 = 0x00000030,
	.dram_sdqs2 = 0x00000030,
	.dram_sdqs3 = 0x00000030,
	.dram_sdqs4 = 0x00000030,
	.dram_sdqs5 = 0x00000030,
	.dram_sdqs6 = 0x00000030,
	.dram_sdqs7 = 0x00000030,

	/* DQM[0:7]: Differential input, 40 ohm */
	.dram_dqm0 = 0x00020030,
	.dram_dqm1 = 0x00020030,
	.dram_dqm2 = 0x00020030,
	.dram_dqm3 = 0x00020030,
	.dram_dqm4 = 0x00020030,
	.dram_dqm5 = 0x00020030,
	.dram_dqm6 = 0x00020030,
	.dram_dqm7 = 0x00020030,
};

/* configure MX6Q/DUAL mmdc GRP io registers */
struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	/* DDR3 */
	.grp_ddr_type = 0x000c0000,
	.grp_ddrmode_ctl = 0x00020000,
	/* disable DDR pullups */
	.grp_ddrpke = 0x00000000,
	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
	.grp_addds = 0x00000030,
	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
	.grp_ctlds = 0x00000030,
	/* DATA[00:63]: Differential input, 40 ohm */
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_b4ds = 0x00000030,
	.grp_b5ds = 0x00000030,
	.grp_b6ds = 0x00000030,
	.grp_b7ds = 0x00000030,
};

/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	.dram_sdclk_0 = 0x00020030,
	.dram_sdclk_1 = 0x00020030,
	.dram_cas = 0x00020030,
	.dram_ras = 0x00020030,
	.dram_reset = 0x00020030,
	/* SDCKE[0:1]: 100k pull-up */
	.dram_sdcke0 = 0x00003000,
	.dram_sdcke1 = 0x00003000,
	/* SDBA2: pull-up disabled */
	.dram_sdba2 = 0x00000000,
	/* SDODT[0:1]: 100k pull-up, 40 ohm */
	.dram_sdodt0 = 0x00003030,
	.dram_sdodt1 = 0x00003030,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.dram_sdqs0 = 0x00000030,
	.dram_sdqs1 = 0x00000030,
	.dram_sdqs2 = 0x00000030,
	.dram_sdqs3 = 0x00000030,
	.dram_sdqs4 = 0x00000030,
	.dram_sdqs5 = 0x00000030,
	.dram_sdqs6 = 0x00000030,
	.dram_sdqs7 = 0x00000030,

	/* DQM[0:7]: Differential input, 40 ohm */
	.dram_dqm0 = 0x00020030,
	.dram_dqm1 = 0x00020030,
	.dram_dqm2 = 0x00020030,
	.dram_dqm3 = 0x00020030,
	.dram_dqm4 = 0x00020030,
	.dram_dqm5 = 0x00020030,
	.dram_dqm6 = 0x00020030,
	.dram_dqm7 = 0x00020030,
};

/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
	/* DDR3 */
	.grp_ddr_type = 0x000c0000,
	/* SDQS[0:7]: Differential input, 40 ohm */
	.grp_ddrmode_ctl = 0x00020000,
	/* disable DDR pullups */
	.grp_ddrpke = 0x00000000,
	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
	.grp_addds = 0x00000030,
	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
	.grp_ctlds = 0x00000030,
	/* DATA[00:63]: Differential input, 40 ohm */
	.grp_ddrmode = 0x00020000,
	.grp_b0ds = 0x00000030,
	.grp_b1ds = 0x00000030,
	.grp_b2ds = 0x00000030,
	.grp_b3ds = 0x00000030,
	.grp_b4ds = 0x00000030,
	.grp_b5ds = 0x00000030,
	.grp_b6ds = 0x00000030,
	.grp_b7ds = 0x00000030,
};

/* MT41K64M16JT-125 (1Gb density) */
static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
	.mem_speed = 1600,
	.density = 1,
	.width = 16,
	.banks = 8,
	.rowaddr = 13,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/* MT41K128M16JT-125 (2Gb density) */
static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
	.mem_speed = 1600,
	.density = 2,
	.width = 16,
	.banks = 8,
	.rowaddr = 14,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/* MT41K256M16HA-125 (4Gb density) */
static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
	.mem_speed = 1600,
	.density = 4,
	.width = 16,
	.banks = 8,
	.rowaddr = 15,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/* MT41K512M16HA-125 (8Gb density) */
static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
	.mem_speed = 1600,
	.density = 8,
	.width = 16,
	.banks = 8,
	.rowaddr = 16,
	.coladdr = 10,
	.pagesz = 2,
	.trcd = 1375,
	.trcmin = 4875,
	.trasmin = 3500,
};

/*
 * calibration - these are the various CPU/DDR3 combinations we support
 */
static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x004C004E,
	.p0_mpwldectrl1 = 0x00440044,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x42440247,
	.p0_mpdgctrl1 = 0x02310232,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x45424746,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x33382C31,
};

static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x001B0016,
	.p0_mpwldectrl1 = 0x000C000E,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x4324033A,
	.p0_mpdgctrl1 = 0x00000000,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x40403438,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x40403D36,
};

static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00420043,
	.p0_mpwldectrl1 = 0x0016001A,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x4238023B,
	.p0_mpdgctrl1 = 0x00000000,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x40404849,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x40402E2F,
};

static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	.p0_mpwldectrl1 = 0x00140026,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	.p0_mpdgctrl1 = 0x433C034D,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
};

static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x003C003C,
	.p0_mpwldectrl1 = 0x001F002A,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x42410244,
	.p0_mpdgctrl1 = 0x4234023A,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x484A4C4B,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x33342B32,
};

static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x00190017,
	.p0_mpwldectrl1 = 0x00140026,
	.p1_mpwldectrl0 = 0x0021001C,
	.p1_mpwldectrl1 = 0x0011001D,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43380347,
	.p0_mpdgctrl1 = 0x433C034D,
	.p1_mpdgctrl0 = 0x032C0324,
	.p1_mpdgctrl1 = 0x03310232,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3C313539,
	.p1_mprddlctl = 0x37343141,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x36393C39,
	.p1_mpwrdlctl = 0x42344438,
};

static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x003C003C,
	.p0_mpwldectrl1 = 0x001F002A,
	.p1_mpwldectrl0 = 0x00330038,
	.p1_mpwldectrl1 = 0x0022003F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x42410244,
	.p0_mpdgctrl1 = 0x4234023A,
	.p1_mpdgctrl0 = 0x022D022D,
	.p1_mpdgctrl1 = 0x021C0228,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x484A4C4B,
	.p1_mprddlctl = 0x4B4D4E4B,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x33342B32,
	.p1_mpwrdlctl = 0x3933332B,
};

static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x001E001A,
	.p0_mpwldectrl1 = 0x0026001F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43370349,
	.p0_mpdgctrl1 = 0x032D0327,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x3D303639,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x32363934,
};

static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0X00480047,
	.p0_mpwldectrl1 = 0X003D003F,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0X423E0241,
	.p0_mpdgctrl1 = 0X022B022C,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0X49454A4A,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0X2E372C32,
};

static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0X00220021,
	.p0_mpwldectrl1 = 0X00200030,
	.p1_mpwldectrl0 = 0X002D0027,
	.p1_mpwldectrl1 = 0X00150026,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43330342,
	.p0_mpdgctrl1 = 0x0339034A,
	.p1_mpdgctrl0 = 0x032F0325,
	.p1_mpdgctrl1 = 0x032F022E,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0X3A2E3437,
	.p1_mprddlctl = 0X35312F3F,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0X33363B37,
	.p1_mpwrdlctl = 0X40304239,
};

static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
	/* write leveling calibration determine */
	.p0_mpwldectrl0 = 0x002A0025,
	.p0_mpwldectrl1 = 0x003A002A,
	/* Read DQS Gating calibration */
	.p0_mpdgctrl0 = 0x43430356,
	.p0_mpdgctrl1 = 0x033C0335,
	/* Read Calibration: DQS delay relative to DQ read access */
	.p0_mprddlctl = 0x4B373F42,
	/* Write Calibration: DQ/DM delay relative to DQS write access */
	.p0_mpwrdlctl = 0x303E3C36,
};

static void spl_dram_init(int width, int size_mb, int board_model)
{
	struct mx6_ddr3_cfg *mem = NULL;
	struct mx6_mmdc_calibration *calib = NULL;
	struct mx6_ddr_sysinfo sysinfo = {
		/* width of data bus:0=16,1=32,2=64 */
		.dsize = width/32,
		/* config for full 4GB range so that get_mem_size() works */
		.cs_density = 32, /* 32Gb per CS */
		/* single chip select */
		.ncs = 1,
		.cs1_mirror = 0,
		.rtt_wr = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Wr = RZQ/4 */
#ifdef RTT_NOM_120OHM
		.rtt_nom = 2 /*DDR3_RTT_120_OHM*/,	/* RTT_Nom = RZQ/2 */
#else
		.rtt_nom = 1 /*DDR3_RTT_60_OHM*/,	/* RTT_Nom = RZQ/4 */
#endif
		.walat = 1,	/* Write additional latency */
		.ralat = 5,	/* Read additional latency */
		.mif3_mode = 3,	/* Command prediction working mode */
		.bi_on = 1,	/* Bank interleaving enabled */
		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
		.pd_fast_exit = 1, /* enable precharge power-down fast exit */
		.ddr_type = DDR_TYPE_DDR3,
	};

	/*
	 * MMDC Calibration requires the following data:
	 *   mx6_mmdc_calibration - board-specific calibration (routing delays)
	 *      these calibration values depend on board routing, SoC, and DDR
	 *   mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
	 *   mx6_ddr_cfg - chip specific timing/layout details
	 */
	if (width == 16 && size_mb == 128) {
		mem = &mt41k64m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			;
		else
			calib = &mx6sdl_64x16_mmdc_calib;
		debug("1gB density\n");
	} else if (width == 16 && size_mb == 256) {
		/* 1x 2Gb density chip - same calib as 2x 2Gb */
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x32_mmdc_calib;
		else
			calib = &mx6sdl_128x32_mmdc_calib;
		debug("2gB density\n");
	} else if (width == 16 && size_mb == 512) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x16_mmdc_calib;
		else
			calib = &mx6sdl_256x16_mmdc_calib;
		debug("4gB density\n");
	} else if (width == 32 && size_mb == 256) {
		/* Same calib as width==16, size==128 */
		mem = &mt41k64m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			;
		else
			calib = &mx6sdl_64x16_mmdc_calib;
		debug("1gB density\n");
	} else if (width == 32 && size_mb == 512) {
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x32_mmdc_calib;
		else
			calib = &mx6sdl_128x32_mmdc_calib;
		debug("2gB density\n");
	}  else if (width == 32 && size_mb == 1024) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x32_mmdc_calib;
		else
			calib = &mx6sdl_256x32_mmdc_calib;
		debug("4gB density\n");
	} else if (width == 32 && size_mb == 2048) {
		mem = &mt41k512m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_512x32_mmdc_calib;
		debug("8gB density\n");
	} else if (width == 64 && size_mb == 512) {
		mem = &mt41k64m16jt_125;
		debug("1gB density\n");
	} else if (width == 64 && size_mb == 1024) {
		mem = &mt41k128m16jt_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_128x64_mmdc_calib;
		else
			calib = &mx6sdl_128x64_mmdc_calib;
		debug("2gB density\n");
	} else if (width == 64 && size_mb == 2048) {
		mem = &mt41k256m16ha_125;
		if (is_cpu_type(MXC_CPU_MX6Q))
			calib = &mx6dq_256x64_mmdc_calib;
		debug("4gB density\n");
	}

	if (!(mem && calib)) {
		puts("Error: Invalid Calibration/Board Configuration\n");
		printf("MEM    : %s\n", mem ? "OKAY" : "NULL");
		printf("CALIB  : %s\n", calib ? "OKAY" : "NULL");
		printf("CPUTYPE: %s\n",
		       is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
		printf("SIZE_MB: %d\n", size_mb);
		printf("WIDTH  : %d\n", width);
		hang();
	}

	if (is_cpu_type(MXC_CPU_MX6Q))
		mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
				 &mx6dq_grp_ioregs);
	else
		mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
				  &mx6sdl_grp_ioregs);
	mx6_dram_cfg(&sysinfo, calib, mem);
}

static void ccgr_init(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	writel(0x00C03F3F, &ccm->CCGR0);
	writel(0x0030FC03, &ccm->CCGR1);
	writel(0x0FFFC000, &ccm->CCGR2);
	writel(0x3FF00000, &ccm->CCGR3);
	writel(0xFFFFF300, &ccm->CCGR4);	/* enable NAND/GPMI/BCH clks */
	writel(0x0F0000C3, &ccm->CCGR5);
	writel(0x000003FF, &ccm->CCGR6);
}

static void gpr_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* enable AXI cache for VDOA/VPU/IPU */
	writel(0xF00000CF, &iomux->gpr[4]);
	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	writel(0x007F007F, &iomux->gpr[6]);
	writel(0x007F007F, &iomux->gpr[7]);
}

/*
 * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 * - we have a stack and a place to store GD, both in SRAM
 * - no variable global data is available
 */
void board_init_f(ulong dummy)
{
	struct ventana_board_info ventana_info;
	int board_model;

	/* setup clock gating */
	ccgr_init();

	/* setup AIPS and disable watchdog */
	arch_cpu_init();

	/* setup AXI */
	gpr_init();

	/* iomux and setup of i2c */
	setup_iomux_uart();
	setup_ventana_i2c();

	/* setup GP timer */
	timer_init();

	/* UART clocks enabled and gd valid - init serial console */
	preloader_console_init();

	/* read/validate EEPROM info to determine board model and SDRAM cfg */
	board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);

	/* configure model-specific gpio */
	setup_iomux_gpio(board_model, &ventana_info);

	/* provide some some default: 32bit 128MB */
	if (GW_UNKNOWN == board_model)
		hang();

	/* configure MMDC for SDRAM width/size and per-model calibration */
	spl_dram_init(8 << ventana_info.sdram_width,
		      16 << ventana_info.sdram_size,
		      board_model);

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);
}

/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
/* its our chance to print info about boot device */
void spl_board_init(void)
{
	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
	u32 boot_device = spl_boot_device();

	switch (boot_device) {
	case BOOT_DEVICE_MMC1:
		puts("Booting from MMC\n");
		break;
	case BOOT_DEVICE_NAND:
		puts("Booting from NAND\n");
		break;
	case BOOT_DEVICE_SATA:
		puts("Booting from SATA\n");
		break;
	default:
		puts("Unknown boot device\n");
	}

	/* PMIC init */
	setup_pmic();
}

#ifdef CONFIG_SPL_OS_BOOT
/* return 1 if we wish to boot to uboot vs os (falcon mode) */
int spl_start_uboot(void)
{
	unsigned char ret = 1;

	debug("%s\n", __func__);
#ifdef CONFIG_SPL_ENV_SUPPORT
	env_init();
	env_relocate_spec();
	debug("boot_os=%s\n", getenv("boot_os"));
	if (getenv_yesno("boot_os") == 1)
		ret = 0;
#else
	/* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
	i2c_set_bus_num(0);
	gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
#endif
	if (!ret)
		gsc_boot_wd_disable();

	debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
	return ret;
}
#endif
Commit	Line	Data
0cc11dea TH	1	/*
	2	* Copyright (C) 2014 Gateworks Corporation
	3	* Author: Tim Harvey <tharvey@gateworks.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
0cc11dea	9	#include <asm/io.h>
e25fbe3f	10	#include <asm/arch/crm_regs.h>
0cc11dea TH	11	#include <asm/arch/mx6-ddr.h>
	12	#include <asm/arch/mx6-pins.h>
	13	#include <asm/arch/sys_proto.h>
	14	#include <asm/imx-common/boot_mode.h>
	15	#include <asm/imx-common/iomux-v3.h>
	16	#include <asm/imx-common/mxc_i2c.h>
53940a50	17	#include <environment.h>
3c0fd17f	18	#include <i2c.h>
0cc11dea TH	19	#include <spl.h>
0cc11dea TH	20
2089b7be TH	21	#include "gsc.h"
2089b7be TH	22	#include "common.h"
0cc11dea TH	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
	26	#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
0cc11dea TH	27	#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
0cc11dea TH	28	#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
0cc11dea TH	29
	30	/* configure MX6Q/DUAL mmdc DDR io registers */
	31	struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
	32	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
	33	.dram_sdclk_0 = 0x00020030,
	34	.dram_sdclk_1 = 0x00020030,
	35	.dram_cas = 0x00020030,
	36	.dram_ras = 0x00020030,
	37	.dram_reset = 0x00020030,
	38	/* SDCKE[0:1]: 100k pull-up */
	39	.dram_sdcke0 = 0x00003000,
	40	.dram_sdcke1 = 0x00003000,
	41	/* SDBA2: pull-up disabled */
	42	.dram_sdba2 = 0x00000000,
	43	/* SDODT[0:1]: 100k pull-up, 40 ohm */
	44	.dram_sdodt0 = 0x00003030,
	45	.dram_sdodt1 = 0x00003030,
	46	/* SDQS[0:7]: Differential input, 40 ohm */
	47	.dram_sdqs0 = 0x00000030,
	48	.dram_sdqs1 = 0x00000030,
	49	.dram_sdqs2 = 0x00000030,
	50	.dram_sdqs3 = 0x00000030,
	51	.dram_sdqs4 = 0x00000030,
	52	.dram_sdqs5 = 0x00000030,
	53	.dram_sdqs6 = 0x00000030,
	54	.dram_sdqs7 = 0x00000030,
	55
	56	/* DQM[0:7]: Differential input, 40 ohm */
	57	.dram_dqm0 = 0x00020030,
	58	.dram_dqm1 = 0x00020030,
	59	.dram_dqm2 = 0x00020030,
	60	.dram_dqm3 = 0x00020030,
	61	.dram_dqm4 = 0x00020030,
	62	.dram_dqm5 = 0x00020030,
	63	.dram_dqm6 = 0x00020030,
	64	.dram_dqm7 = 0x00020030,
	65	};
	66
	67	/* configure MX6Q/DUAL mmdc GRP io registers */
	68	struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
	69	/* DDR3 */
	70	.grp_ddr_type = 0x000c0000,
	71	.grp_ddrmode_ctl = 0x00020000,
	72	/* disable DDR pullups */
	73	.grp_ddrpke = 0x00000000,
	74	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
	75	.grp_addds = 0x00000030,
	76	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
	77	.grp_ctlds = 0x00000030,
	78	/* DATA[00:63]: Differential input, 40 ohm */
	79	.grp_ddrmode = 0x00020000,
	80	.grp_b0ds = 0x00000030,
	81	.grp_b1ds = 0x00000030,
	82	.grp_b2ds = 0x00000030,
	83	.grp_b3ds = 0x00000030,
	84	.grp_b4ds = 0x00000030,
	85	.grp_b5ds = 0x00000030,
	86	.grp_b6ds = 0x00000030,
	87	.grp_b7ds = 0x00000030,
	88	};
	89
	90	/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
	91	struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
	92	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
93	.dram_sdclk_0 = 0x00020030,
94	.dram_sdclk_1 = 0x00020030,
95	.dram_cas = 0x00020030,
96	.dram_ras = 0x00020030,
97	.dram_reset = 0x00020030,
98	/* SDCKE[0:1]: 100k pull-up */
99	.dram_sdcke0 = 0x00003000,
100	.dram_sdcke1 = 0x00003000,
101	/* SDBA2: pull-up disabled */
102	.dram_sdba2 = 0x00000000,
103	/* SDODT[0:1]: 100k pull-up, 40 ohm */
104	.dram_sdodt0 = 0x00003030,
105	.dram_sdodt1 = 0x00003030,
106	/* SDQS[0:7]: Differential input, 40 ohm */
107	.dram_sdqs0 = 0x00000030,
108	.dram_sdqs1 = 0x00000030,
109	.dram_sdqs2 = 0x00000030,
110	.dram_sdqs3 = 0x00000030,
111	.dram_sdqs4 = 0x00000030,
112	.dram_sdqs5 = 0x00000030,
113	.dram_sdqs6 = 0x00000030,
114	.dram_sdqs7 = 0x00000030,
115
116	/* DQM[0:7]: Differential input, 40 ohm */
117	.dram_dqm0 = 0x00020030,
118	.dram_dqm1 = 0x00020030,
119	.dram_dqm2 = 0x00020030,
120	.dram_dqm3 = 0x00020030,
121	.dram_dqm4 = 0x00020030,
122	.dram_dqm5 = 0x00020030,
123	.dram_dqm6 = 0x00020030,
124	.dram_dqm7 = 0x00020030,
125	};
126
127	/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
128	struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
129	/* DDR3 */
130	.grp_ddr_type = 0x000c0000,
131	/* SDQS[0:7]: Differential input, 40 ohm */
132	.grp_ddrmode_ctl = 0x00020000,
133	/* disable DDR pullups */
134	.grp_ddrpke = 0x00000000,
135	/* ADDR[00:16], SDBA[0:1]: 40 ohm */
136	.grp_addds = 0x00000030,
137	/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
138	.grp_ctlds = 0x00000030,
139	/* DATA[00:63]: Differential input, 40 ohm */
140	.grp_ddrmode = 0x00020000,
141	.grp_b0ds = 0x00000030,
142	.grp_b1ds = 0x00000030,
143	.grp_b2ds = 0x00000030,
144	.grp_b3ds = 0x00000030,
145	.grp_b4ds = 0x00000030,
146	.grp_b5ds = 0x00000030,
147	.grp_b6ds = 0x00000030,
148	.grp_b7ds = 0x00000030,
149	};
150
767d88b0 PS	151	/* MT41K64M16JT-125 (1Gb density) */
	152	static struct mx6_ddr3_cfg mt41k64m16jt_125 = {
	153	.mem_speed = 1600,
	154	.density = 1,
	155	.width = 16,
	156	.banks = 8,
	157	.rowaddr = 13,
	158	.coladdr = 10,
	159	.pagesz = 2,
	160	.trcd = 1375,
	161	.trcmin = 4875,
	162	.trasmin = 3500,
	163	};
	164
b0b83347	165	/* MT41K128M16JT-125 (2Gb density) */
0cc11dea TH	166	static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
	167	.mem_speed = 1600,
	168	.density = 2,
	169	.width = 16,
	170	.banks = 8,
	171	.rowaddr = 14,
	172	.coladdr = 10,
	173	.pagesz = 2,
	174	.trcd = 1375,
	175	.trcmin = 4875,
	176	.trasmin = 3500,
	177	};
	178
b0b83347	179	/* MT41K256M16HA-125 (4Gb density) */
c91e4b8b TH	180	static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
	181	.mem_speed = 1600,
	182	.density = 4,
	183	.width = 16,
	184	.banks = 8,
	185	.rowaddr = 15,
	186	.coladdr = 10,
	187	.pagesz = 2,
	188	.trcd = 1375,
	189	.trcmin = 4875,
	190	.trasmin = 3500,
	191	};
	192
6052b1c6 TH	193	/* MT41K512M16HA-125 (8Gb density) */
	194	static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
	195	.mem_speed = 1600,
	196	.density = 8,
	197	.width = 16,
	198	.banks = 8,
	199	.rowaddr = 16,
	200	.coladdr = 10,
	201	.pagesz = 2,
	202	.trcd = 1375,
	203	.trcmin = 4875,
	204	.trasmin = 3500,
	205	};
	206
c91e4b8b TH	207	/*
	208	* calibration - these are the various CPU/DDR3 combinations we support
	209	*/
767d88b0 PS	210	static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
	211	/* write leveling calibration determine */
	212	.p0_mpwldectrl0 = 0x004C004E,
	213	.p0_mpwldectrl1 = 0x00440044,
	214	/* Read DQS Gating calibration */
	215	.p0_mpdgctrl0 = 0x42440247,
	216	.p0_mpdgctrl1 = 0x02310232,
	217	/* Read Calibration: DQS delay relative to DQ read access */
	218	.p0_mprddlctl = 0x45424746,
	219	/* Write Calibration: DQ/DM delay relative to DQS write access */
	220	.p0_mpwrdlctl = 0x33382C31,
	221	};
c91e4b8b	222
75f21e31 TH	223	static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
75f21e31 TH	224	/* write leveling calibration determine */
06edcb9d TH	225	.p0_mpwldectrl0 = 0x001B0016,
06edcb9d TH	226	.p0_mpwldectrl1 = 0x000C000E,
75f21e31	227	/* Read DQS Gating calibration */
06edcb9d TH	228	.p0_mpdgctrl0 = 0x4324033A,
06edcb9d TH	229	.p0_mpdgctrl1 = 0x00000000,
75f21e31	230	/* Read Calibration: DQS delay relative to DQ read access */
06edcb9d	231	.p0_mprddlctl = 0x40403438,
75f21e31	232	/* Write Calibration: DQ/DM delay relative to DQS write access */
06edcb9d	233	.p0_mpwrdlctl = 0x40403D36,
75f21e31 TH	234	};
75f21e31 TH	235
75f21e31 TH	236	static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = {
75f21e31 TH	237	/* write leveling calibration determine */
06edcb9d TH	238	.p0_mpwldectrl0 = 0x00420043,
06edcb9d TH	239	.p0_mpwldectrl1 = 0x0016001A,
75f21e31	240	/* Read DQS Gating calibration */
06edcb9d TH	241	.p0_mpdgctrl0 = 0x4238023B,
06edcb9d TH	242	.p0_mpdgctrl1 = 0x00000000,
75f21e31	243	/* Read Calibration: DQS delay relative to DQ read access */
06edcb9d	244	.p0_mprddlctl = 0x40404849,
75f21e31	245	/* Write Calibration: DQ/DM delay relative to DQS write access */
06edcb9d	246	.p0_mpwrdlctl = 0x40402E2F,
75f21e31 TH	247	};
75f21e31 TH	248
c91e4b8b	249	static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = {
0cc11dea	250	/* write leveling calibration determine */
c91e4b8b TH	251	.p0_mpwldectrl0 = 0x00190017,
c91e4b8b TH	252	.p0_mpwldectrl1 = 0x00140026,
0cc11dea	253	/* Read DQS Gating calibration */
c91e4b8b TH	254	.p0_mpdgctrl0 = 0x43380347,
c91e4b8b TH	255	.p0_mpdgctrl1 = 0x433C034D,
0cc11dea TH	256	/* Read Calibration: DQS delay relative to DQ read access */
0cc11dea TH	257	.p0_mprddlctl = 0x3C313539,
0cc11dea	258	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	259	.p0_mpwrdlctl = 0x36393C39,
	260	};
	261
	262	static struct mx6_mmdc_calibration mx6sdl_128x32_mmdc_calib = {
	263	/* write leveling calibration determine */
	264	.p0_mpwldectrl0 = 0x003C003C,
	265	.p0_mpwldectrl1 = 0x001F002A,
	266	/* Read DQS Gating calibration */
	267	.p0_mpdgctrl0 = 0x42410244,
	268	.p0_mpdgctrl1 = 0x4234023A,
	269	/* Read Calibration: DQS delay relative to DQ read access */
	270	.p0_mprddlctl = 0x484A4C4B,
	271	/* Write Calibration: DQ/DM delay relative to DQS write access */
	272	.p0_mpwrdlctl = 0x33342B32,
0cc11dea TH	273	};
0cc11dea TH	274
c91e4b8b	275	static struct mx6_mmdc_calibration mx6dq_128x64_mmdc_calib = {
0cc11dea	276	/* write leveling calibration determine */
c91e4b8b TH	277	.p0_mpwldectrl0 = 0x00190017,
	278	.p0_mpwldectrl1 = 0x00140026,
	279	.p1_mpwldectrl0 = 0x0021001C,
	280	.p1_mpwldectrl1 = 0x0011001D,
0cc11dea	281	/* Read DQS Gating calibration */
c91e4b8b TH	282	.p0_mpdgctrl0 = 0x43380347,
	283	.p0_mpdgctrl1 = 0x433C034D,
	284	.p1_mpdgctrl0 = 0x032C0324,
	285	.p1_mpdgctrl1 = 0x03310232,
0cc11dea	286	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b TH	287	.p0_mprddlctl = 0x3C313539,
c91e4b8b TH	288	.p1_mprddlctl = 0x37343141,
0cc11dea	289	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	290	.p0_mpwrdlctl = 0x36393C39,
c91e4b8b TH	291	.p1_mpwrdlctl = 0x42344438,
0cc11dea	292	};
c91e4b8b TH	293
c91e4b8b TH	294	static struct mx6_mmdc_calibration mx6sdl_128x64_mmdc_calib = {
0cc11dea TH	295	/* write leveling calibration determine */
0cc11dea TH	296	.p0_mpwldectrl0 = 0x003C003C,
c91e4b8b TH	297	.p0_mpwldectrl1 = 0x001F002A,
c91e4b8b TH	298	.p1_mpwldectrl0 = 0x00330038,
0cc11dea TH	299	.p1_mpwldectrl1 = 0x0022003F,
	300	/* Read DQS Gating calibration */
	301	.p0_mpdgctrl0 = 0x42410244,
c91e4b8b TH	302	.p0_mpdgctrl1 = 0x4234023A,
c91e4b8b TH	303	.p1_mpdgctrl0 = 0x022D022D,
0cc11dea TH	304	.p1_mpdgctrl1 = 0x021C0228,
	305	/* Read Calibration: DQS delay relative to DQ read access */
	306	.p0_mprddlctl = 0x484A4C4B,
	307	.p1_mprddlctl = 0x4B4D4E4B,
	308	/* Write Calibration: DQ/DM delay relative to DQS write access */
	309	.p0_mpwrdlctl = 0x33342B32,
	310	.p1_mpwrdlctl = 0x3933332B,
	311	};
	312
c91e4b8b	313	static struct mx6_mmdc_calibration mx6dq_256x32_mmdc_calib = {
0cc11dea	314	/* write leveling calibration determine */
c91e4b8b TH	315	.p0_mpwldectrl0 = 0x001E001A,
c91e4b8b TH	316	.p0_mpwldectrl1 = 0x0026001F,
0cc11dea	317	/* Read DQS Gating calibration */
c91e4b8b TH	318	.p0_mpdgctrl0 = 0x43370349,
c91e4b8b TH	319	.p0_mpdgctrl1 = 0x032D0327,
0cc11dea	320	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b	321	.p0_mprddlctl = 0x3D303639,
0cc11dea	322	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b	323	.p0_mpwrdlctl = 0x32363934,
0cc11dea TH	324	};
0cc11dea TH	325
b0b83347 TH	326	static struct mx6_mmdc_calibration mx6sdl_256x32_mmdc_calib = {
	327	/* write leveling calibration determine */
	328	.p0_mpwldectrl0 = 0X00480047,
	329	.p0_mpwldectrl1 = 0X003D003F,
	330	/* Read DQS Gating calibration */
	331	.p0_mpdgctrl0 = 0X423E0241,
	332	.p0_mpdgctrl1 = 0X022B022C,
	333	/* Read Calibration: DQS delay relative to DQ read access */
	334	.p0_mprddlctl = 0X49454A4A,
	335	/* Write Calibration: DQ/DM delay relative to DQS write access */
	336	.p0_mpwrdlctl = 0X2E372C32,
	337	};
	338
c91e4b8b	339	static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
0cc11dea	340	/* write leveling calibration determine */
c91e4b8b TH	341	.p0_mpwldectrl0 = 0X00220021,
	342	.p0_mpwldectrl1 = 0X00200030,
	343	.p1_mpwldectrl0 = 0X002D0027,
	344	.p1_mpwldectrl1 = 0X00150026,
0cc11dea	345	/* Read DQS Gating calibration */
c91e4b8b TH	346	.p0_mpdgctrl0 = 0x43330342,
	347	.p0_mpdgctrl1 = 0x0339034A,
	348	.p1_mpdgctrl0 = 0x032F0325,
	349	.p1_mpdgctrl1 = 0x032F022E,
0cc11dea	350	/* Read Calibration: DQS delay relative to DQ read access */
c91e4b8b TH	351	.p0_mprddlctl = 0X3A2E3437,
c91e4b8b TH	352	.p1_mprddlctl = 0X35312F3F,
0cc11dea	353	/* Write Calibration: DQ/DM delay relative to DQS write access */
c91e4b8b TH	354	.p0_mpwrdlctl = 0X33363B37,
c91e4b8b TH	355	.p1_mpwrdlctl = 0X40304239,
0cc11dea TH	356	};
0cc11dea TH	357
6052b1c6 TH	358	static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
	359	/* write leveling calibration determine */
	360	.p0_mpwldectrl0 = 0x002A0025,
	361	.p0_mpwldectrl1 = 0x003A002A,
	362	/* Read DQS Gating calibration */
	363	.p0_mpdgctrl0 = 0x43430356,
	364	.p0_mpdgctrl1 = 0x033C0335,
	365	/* Read Calibration: DQS delay relative to DQ read access */
	366	.p0_mprddlctl = 0x4B373F42,
	367	/* Write Calibration: DQ/DM delay relative to DQS write access */
	368	.p0_mpwrdlctl = 0x303E3C36,
	369	};
	370
c91e4b8b	371	static void spl_dram_init(int width, int size_mb, int board_model)
0cc11dea	372	{
c91e4b8b TH	373	struct mx6_ddr3_cfg *mem = NULL;
c91e4b8b TH	374	struct mx6_mmdc_calibration *calib = NULL;
0cc11dea TH	375	struct mx6_ddr_sysinfo sysinfo = {
	376	/* width of data bus:0=16,1=32,2=64 */
	377	.dsize = width/32,
	378	/* config for full 4GB range so that get_mem_size() works */
	379	.cs_density = 32, /* 32Gb per CS */
	380	/* single chip select */
	381	.ncs = 1,
	382	.cs1_mirror = 0,
	383	.rtt_wr = 1 /DDR3_RTT_60_OHM/, /* RTT_Wr = RZQ/4 */
	384	#ifdef RTT_NOM_120OHM
	385	.rtt_nom = 2 /DDR3_RTT_120_OHM/, /* RTT_Nom = RZQ/2 */
	386	#else
	387	.rtt_nom = 1 /DDR3_RTT_60_OHM/, /* RTT_Nom = RZQ/4 */
	388	#endif
	389	.walat = 1, /* Write additional latency */
	390	.ralat = 5, /* Read additional latency */
	391	.mif3_mode = 3, /* Command prediction working mode */
	392	.bi_on = 1, /* Bank interleaving enabled */
	393	.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	394	.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
29f0d6b1	395	.pd_fast_exit = 1, /* enable precharge power-down fast exit */
f2ff8343	396	.ddr_type = DDR_TYPE_DDR3,
0cc11dea TH	397	};
	398
	399	/*
	400	* MMDC Calibration requires the following data:
	401	* mx6_mmdc_calibration - board-specific calibration (routing delays)
c91e4b8b	402	* these calibration values depend on board routing, SoC, and DDR
0cc11dea TH	403	* mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
	404	* mx6_ddr_cfg - chip specific timing/layout details
	405	*/
767d88b0 PS	406	if (width == 16 && size_mb == 128) {
	407	mem = &mt41k64m16jt_125;
	408	if (is_cpu_type(MXC_CPU_MX6Q))
	409	;
	410	else
	411	calib = &mx6sdl_64x16_mmdc_calib;
	412	debug("1gB density\n");
	413	} else if (width == 16 && size_mb == 256) {
7f14c31b	414	/* 1x 2Gb density chip - same calib as 2x 2Gb */
75f21e31 TH	415	mem = &mt41k128m16jt_125;
75f21e31 TH	416	if (is_cpu_type(MXC_CPU_MX6Q))
7f14c31b	417	calib = &mx6dq_128x32_mmdc_calib;
75f21e31	418	else
7f14c31b	419	calib = &mx6sdl_128x32_mmdc_calib;
75f21e31 TH	420	debug("2gB density\n");
	421	} else if (width == 16 && size_mb == 512) {
	422	mem = &mt41k256m16ha_125;
	423	if (is_cpu_type(MXC_CPU_MX6Q))
	424	calib = &mx6dq_256x16_mmdc_calib;
	425	else
	426	calib = &mx6sdl_256x16_mmdc_calib;
	427	debug("4gB density\n");
767d88b0 PS	428	} else if (width == 32 && size_mb == 256) {
	429	/* Same calib as width==16, size==128 */
	430	mem = &mt41k64m16jt_125;
	431	if (is_cpu_type(MXC_CPU_MX6Q))
	432	;
	433	else
	434	calib = &mx6sdl_64x16_mmdc_calib;
	435	debug("1gB density\n");
75f21e31	436	} else if (width == 32 && size_mb == 512) {
c91e4b8b	437	mem = &mt41k128m16jt_125;
0cc11dea	438	if (is_cpu_type(MXC_CPU_MX6Q))
c91e4b8b	439	calib = &mx6dq_128x32_mmdc_calib;
0cc11dea	440	else
c91e4b8b TH	441	calib = &mx6sdl_128x32_mmdc_calib;
c91e4b8b TH	442	debug("2gB density\n");
767d88b0 PS	443	} else if (width == 32 && size_mb == 1024) {
	444	mem = &mt41k256m16ha_125;
	445	if (is_cpu_type(MXC_CPU_MX6Q))
	446	calib = &mx6dq_256x32_mmdc_calib;
	447	else
	448	calib = &mx6sdl_256x32_mmdc_calib;
	449	debug("4gB density\n");
6052b1c6 TH	450	} else if (width == 32 && size_mb == 2048) {
	451	mem = &mt41k512m16ha_125;
	452	if (is_cpu_type(MXC_CPU_MX6Q))
	453	calib = &mx6dq_512x32_mmdc_calib;
	454	debug("8gB density\n");
767d88b0 PS	455	} else if (width == 64 && size_mb == 512) {
	456	mem = &mt41k64m16jt_125;
	457	debug("1gB density\n");
c91e4b8b TH	458	} else if (width == 64 && size_mb == 1024) {
c91e4b8b TH	459	mem = &mt41k128m16jt_125;
0cc11dea	460	if (is_cpu_type(MXC_CPU_MX6Q))
c91e4b8b	461	calib = &mx6dq_128x64_mmdc_calib;
0cc11dea	462	else
c91e4b8b TH	463	calib = &mx6sdl_128x64_mmdc_calib;
c91e4b8b TH	464	debug("2gB density\n");
c91e4b8b TH	465	} else if (width == 64 && size_mb == 2048) {
	466	mem = &mt41k256m16ha_125;
	467	if (is_cpu_type(MXC_CPU_MX6Q))
	468	calib = &mx6dq_256x64_mmdc_calib;
	469	debug("4gB density\n");
	470	}
	471
9e2b0c2d PS	472	if (!(mem && calib)) {
	473	puts("Error: Invalid Calibration/Board Configuration\n");
	474	printf("MEM : %s\n", mem ? "OKAY" : "NULL");
	475	printf("CALIB : %s\n", calib ? "OKAY" : "NULL");
	476	printf("CPUTYPE: %s\n",
	477	is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL");
	478	printf("SIZE_MB: %d\n", size_mb);
	479	printf("WIDTH : %d\n", width);
c91e4b8b	480	hang();
0cc11dea TH	481	}
	482
	483	if (is_cpu_type(MXC_CPU_MX6Q))
	484	mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
	485	&mx6dq_grp_ioregs);
	486	else
	487	mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
	488	&mx6sdl_grp_ioregs);
	489	mx6_dram_cfg(&sysinfo, calib, mem);
	490	}
	491
e25fbe3f FE	492	static void ccgr_init(void)
	493	{
	494	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	495
	496	writel(0x00C03F3F, &ccm->CCGR0);
	497	writel(0x0030FC03, &ccm->CCGR1);
	498	writel(0x0FFFC000, &ccm->CCGR2);
	499	writel(0x3FF00000, &ccm->CCGR3);
576cd6b3	500	writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
e25fbe3f FE	501	writel(0x0F0000C3, &ccm->CCGR5);
	502	writel(0x000003FF, &ccm->CCGR6);
	503	}
	504
	505	static void gpr_init(void)
	506	{
	507	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	508
	509	/* enable AXI cache for VDOA/VPU/IPU */
	510	writel(0xF00000CF, &iomux->gpr[4]);
	511	/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	512	writel(0x007F007F, &iomux->gpr[6]);
	513	writel(0x007F007F, &iomux->gpr[7]);
	514	}
	515
0cc11dea TH	516	/*
	517	* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
	518	* - we have a stack and a place to store GD, both in SRAM
	519	* - no variable global data is available
	520	*/
	521	void board_init_f(ulong dummy)
	522	{
	523	struct ventana_board_info ventana_info;
	524	int board_model;
	525
d783c274 TH	526	/* setup clock gating */
	527	ccgr_init();
	528
0cc11dea TH	529	/* setup AIPS and disable watchdog */
	530	arch_cpu_init();
	531
d783c274	532	/* setup AXI */
e25fbe3f FE	533	gpr_init();
e25fbe3f FE	534
0cc11dea	535	/* iomux and setup of i2c */
2089b7be TH	536	setup_iomux_uart();
2089b7be TH	537	setup_ventana_i2c();
0cc11dea TH	538
	539	/* setup GP timer */
	540	timer_init();
	541
	542	/* UART clocks enabled and gd valid - init serial console */
	543	preloader_console_init();
	544
	545	/* read/validate EEPROM info to determine board model and SDRAM cfg */
2089b7be	546	board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
0cc11dea	547
c4b44d76 TH	548	/* configure model-specific gpio */
	549	setup_iomux_gpio(board_model, &ventana_info);
	550
0cc11dea	551	/* provide some some default: 32bit 128MB */
fdead4be TH	552	if (GW_UNKNOWN == board_model)
fdead4be TH	553	hang();
0cc11dea TH	554
	555	/* configure MMDC for SDRAM width/size and per-model calibration */
	556	spl_dram_init(8 << ventana_info.sdram_width,
	557	16 << ventana_info.sdram_size,
	558	board_model);
	559
	560	/* Clear the BSS. */
	561	memset(__bss_start, 0, __bss_end - __bss_start);
0cc11dea TH	562	}
0cc11dea TH	563
06c3564d TH	564	/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
	565	/* its our chance to print info about boot device */
	566	void spl_board_init(void)
	567	{
	568	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
	569	u32 boot_device = spl_boot_device();
	570
	571	switch (boot_device) {
	572	case BOOT_DEVICE_MMC1:
	573	puts("Booting from MMC\n");
	574	break;
	575	case BOOT_DEVICE_NAND:
	576	puts("Booting from NAND\n");
	577	break;
	578	case BOOT_DEVICE_SATA:
	579	puts("Booting from SATA\n");
	580	break;
	581	default:
	582	puts("Unknown boot device\n");
	583	}
e06a0362 TH	584
	585	/* PMIC init */
	586	setup_pmic();
06c3564d TH	587	}
06c3564d TH	588
53940a50 TH	589	#ifdef CONFIG_SPL_OS_BOOT
	590	/* return 1 if we wish to boot to uboot vs os (falcon mode) */
	591	int spl_start_uboot(void)
	592	{
3c0fd17f	593	unsigned char ret = 1;
53940a50 TH	594
	595	debug("%s\n", __func__);
	596	#ifdef CONFIG_SPL_ENV_SUPPORT
	597	env_init();
	598	env_relocate_spec();
	599	debug("boot_os=%s\n", getenv("boot_os"));
	600	if (getenv_yesno("boot_os") == 1)
	601	ret = 0;
3c0fd17f TH	602	#else
	603	/* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
	604	i2c_set_bus_num(0);
	605	gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
53940a50	606	#endif
1b99103f TH	607	if (!ret)
	608	gsc_boot_wd_disable();
	609
53940a50 TH	610	debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
	611	return ret;
	612	}
	613	#endif