[people/ms/u-boot.git] / board / nc650 / nc650.c

/*
 * (C) Copyright 2006 Detlev Zundel, dzu@denx.de
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <config.h>
#include <mpc8xx.h>

/*
 *  Memory Controller Using
 *
 *  CS0 - Flash memory            (0x40000000)
 *  CS3 - SDRAM                   (0x00000000}
 */

/* ------------------------------------------------------------------------- */

#define _not_used_	0xffffffff

const uint sdram_table[] = {
	/* single read. (offset 0 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	0x1ff77c47,

	/* MRS initialization (offset 5) */

	0x1ff77c34, 0xefeabc34, 0x1fb57c35,

	/* burst read. (offset 8 in upm RAM) */
	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* single write. (offset 18 in upm RAM) */
	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* burst write. (offset 20 in upm RAM) */
	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* refresh. (offset 30 in upm RAM) */
	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
	_not_used_, _not_used_, _not_used_, _not_used_,

	/* exception. (offset 3c in upm RAM) */
	0x7ffffc07, _not_used_, _not_used_, _not_used_
};

const uint nand_flash_table[] = {
	/* single read. (offset 0 in upm RAM) */
	0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
	0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,

	/* burst read. (offset 8 in upm RAM) */
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,

	/* single write. (offset 18 in upm RAM) */
	0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
	0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,

	/* burst write. (offset 20 in upm RAM) */
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,

	/* refresh. (offset 30 in upm RAM) */
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,

	/* exception. (offset 3c in upm RAM) */
	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
};

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 */

int checkboard (void)
{
#if !defined(CONFIG_CP850)
	puts ("Board: NC650");
#else
	puts ("Board: CP850");
#endif
#if defined(CONFIG_IDS852_REV1)
	puts (" with IDS852 rev 1 module\n");
#elif defined(CONFIG_IDS852_REV2)
	puts (" with IDS852 rev 2 module\n");
#endif
	return 0;
}

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size8, size9;
	long int size_b0 = 0;
	unsigned long reg;

	upmconfig (UPMA, (uint *) sdram_table,
			   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;

	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller bank 1 to the SDRAM bank at
	 * preliminary address - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;

	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 0 */
	udelay (200);
	memctl->memc_mcr = 0x80006230;	/* SDRAM bank 0 - execute twice */
	udelay (200);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	udelay (1000);

	if (size8 < size9) {
		size_b0 = size9;
	} else {
		size_b0 = size8;
		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
		udelay (500);
	}

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks.
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if ((size_b0 < 0x02000000)) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
		udelay (1000);
	}

	/*
	 * Final mapping
	 */

	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

	/* adjust refresh rate depending on SDRAM type, one bank */
	reg = memctl->memc_mptpr;
	reg >>= 1;					/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
	memctl->memc_mptpr = reg;

	udelay (10000);

	/* Configure UPMB for NAND flash access */
	upmconfig (UPMB, (uint *) nand_flash_table,
			   sizeof (nand_flash_table) / sizeof (uint));

	memctl->memc_mbmr = CONFIG_SYS_MBMR_NAND;

	return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size(base, maxsize));
}


#if defined(CONFIG_CP850)

#define DPRAM_VARNAME           "KP850DIP"
#define PARAM_ADDR              0x7C0
#define NAME_ADDR               0x7F8
#define BOARD_NAME              "KP01"
#define DEFAULT_LB              "241111"

int misc_init_r(void)
{
	int             iCompatMode = 0;
	char            *pParam = NULL;
	char            *envlb;

	/*
	   First byte in CPLD read address space signals compatibility mode
	   0 - cp850
	   1 - kp852
	*/
	pParam = (char*)(CONFIG_SYS_CPLD_BASE);
	if( *pParam != 0)
		iCompatMode = 1;

	if ( iCompatMode != 0) {
		/*
		   In KP852 compatibility mode we have to write to
		   DPRAM as early as possible the binary coded
		   line config and board name.
		   The line config is derived from the environment
		   variable DPRAM_VARNAME by converting from ASCII
		   to binary per character.
		*/
		if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
			setenv( DPRAM_VARNAME, DEFAULT_LB);
			envlb = DEFAULT_LB;
		}

		/* Status string */
		printf("Mode:  KP852(LB=%s)\n", envlb);

		/* copy appl init */
		pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
		while (*envlb) {
			*(pParam++) = *(envlb++) - '0';
		}
		*pParam = '\0';

		/* copy board id */
		pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
		strcpy( pParam, BOARD_NAME);
	} else {
		puts("Mode:  CP850\n");
	}

	return 0;
}
#endif
Commit	Line	Data
7ca202f5	1	/*
a367d426	2	* (C) Copyright 2006 Detlev Zundel, dzu@denx.de
7ca202f5 WD	3	* (C) Copyright 2001
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <config.h>
	27	#include <mpc8xx.h>
	28
	29	/*
	30	* Memory Controller Using
	31	*
	32	* CS0 - Flash memory (0x40000000)
	33	* CS3 - SDRAM (0x00000000}
	34	*/
	35
	36	/* ------------------------------------------------------------------------- */
	37
	38	#define _not_used_ 0xffffffff
	39
	40	const uint sdram_table[] = {
	41	/* single read. (offset 0 in upm RAM) */
	42	0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
	43	0x1ff77c47,
	44
	45	/* MRS initialization (offset 5) */
	46
	47	0x1ff77c34, 0xefeabc34, 0x1fb57c35,
	48
	49	/* burst read. (offset 8 in upm RAM) */
	50	0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
	51	0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
	52	_not_used_, _not_used_, _not_used_, _not_used_,
	53	_not_used_, _not_used_, _not_used_, _not_used_,
	54
	55	/* single write. (offset 18 in upm RAM) */
	56	0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
	57	_not_used_, _not_used_, _not_used_, _not_used_,
	58
	59	/* burst write. (offset 20 in upm RAM) */
	60	0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
	61	0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
	62	_not_used_, _not_used_, _not_used_, _not_used_,
	63	_not_used_, _not_used_, _not_used_, _not_used_,
	64
	65	/* refresh. (offset 30 in upm RAM) */
	66	0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
67	0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
68	_not_used_, _not_used_, _not_used_, _not_used_,
69
70	/* exception. (offset 3c in upm RAM) */
71	0x7ffffc07, _not_used_, _not_used_, _not_used_
72	};
73
c3fafecf WD	74	const uint nand_flash_table[] = {
	75	/* single read. (offset 0 in upm RAM) */
	76	0x0ff3fc04, 0x0ff3fc04, 0x0ff3fc04, 0x0ffffc04,
	77	0xfffffc00, 0xfffffc05, 0xfffffc05, 0xfffffc05,
	78
	79	/* burst read. (offset 8 in upm RAM) */
	80	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	81	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	82	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	83	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	84
	85	/* single write. (offset 18 in upm RAM) */
	86	0x00fffc04, 0x00fffc04, 0x00fffc04, 0x0ffffc04,
	87	0x0ffffc84, 0x0ffffc84, 0xfffffc00, 0xfffffc05,
	88
	89	/* burst write. (offset 20 in upm RAM) */
	90	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	91	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	92	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	93	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	94
	95	/* refresh. (offset 30 in upm RAM) */
	96	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	97	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	98	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05,
	99
	100	/* exception. (offset 3c in upm RAM) */
	101	0xffffcc05, 0xffffcc05, 0xffffcc05, 0xffffcc05
	102	};
	103
7ca202f5 WD	104	/* ------------------------------------------------------------------------- */
	105
	106	/*
	107	* Check Board Identity:
	108	*/
	109
	110	int checkboard (void)
	111	{
a367d426	112	#if !defined(CONFIG_CP850)
	113	puts ("Board: NC650");
	114	#else
	115	puts ("Board: CP850");
	116	#endif
	117	#if defined(CONFIG_IDS852_REV1)
	118	puts (" with IDS852 rev 1 module\n");
	119	#elif defined(CONFIG_IDS852_REV2)
	120	puts (" with IDS852 rev 2 module\n");
	121	#endif
7ca202f5 WD	122	return 0;
	123	}
	124
	125	/* ------------------------------------------------------------------------- */
	126
	127	static long int dram_size (long int, long int *, long int);
	128
	129	/* ------------------------------------------------------------------------- */
	130
9973e3c6	131	phys_size_t initdram (int board_type)
7ca202f5	132	{
6d0f6bcf	133	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
7ca202f5 WD	134	volatile memctl8xx_t *memctl = &immap->im_memctl;
	135	long int size8, size9;
	136	long int size_b0 = 0;
	137	unsigned long reg;
	138
	139	upmconfig (UPMA, (uint *) sdram_table,
	140	sizeof (sdram_table) / sizeof (uint));
	141
	142	/*
	143	* Preliminary prescaler for refresh (depends on number of
	144	* banks): This value is selected for four cycles every 62.4 us
	145	* with two SDRAM banks or four cycles every 31.2 us with one
	146	* bank. It will be adjusted after memory sizing.
	147	*/
6d0f6bcf	148	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
7ca202f5 WD	149
	150	memctl->memc_mar = 0x00000088;
	151
	152	/*
	153	* Map controller bank 1 to the SDRAM bank at
	154	* preliminary address - these have to be modified after the
	155	* SDRAM size has been determined.
	156	*/
6d0f6bcf JCPV	157	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
6d0f6bcf JCPV	158	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
7ca202f5	159
6d0f6bcf	160	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
7ca202f5 WD	161
	162	udelay (200);
	163
	164	/* perform SDRAM initializsation sequence */
	165
	166	memctl->memc_mcr = 0x80006105; /* SDRAM bank 0 */
	167	udelay (200);
	168	memctl->memc_mcr = 0x80006230; /* SDRAM bank 0 - execute twice */
	169	udelay (200);
	170
	171	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	172
	173	udelay (1000);
	174
	175	/*
	176	* Check Bank 0 Memory Size for re-configuration
	177	*
	178	* try 8 column mode
	179	*/
6d0f6bcf	180	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
7ca202f5 WD	181
	182	udelay (1000);
	183
	184	/*
	185	* try 9 column mode
	186	*/
6d0f6bcf	187	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
7ca202f5 WD	188
	189	udelay (1000);
	190
	191	if (size8 < size9) {
	192	size_b0 = size9;
	193	} else {
	194	size_b0 = size8;
6d0f6bcf	195	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
7ca202f5 WD	196	udelay (500);
	197	}
	198
	199	/*
	200	* Adjust refresh rate depending on SDRAM type, both banks.
	201	* For types > 128 MBit leave it at the current (fast) rate
	202	*/
	203	if ((size_b0 < 0x02000000)) {
	204	/* reduce to 15.6 us (62.4 us / quad) */
6d0f6bcf	205	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
7ca202f5 WD	206	udelay (1000);
	207	}
	208
	209	/*
	210	* Final mapping
	211	*/
	212
6d0f6bcf JCPV	213	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) \| CONFIG_SYS_OR_TIMING_SDRAM;
6d0f6bcf JCPV	214	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
7ca202f5 WD	215
	216	/* adjust refresh rate depending on SDRAM type, one bank */
	217	reg = memctl->memc_mptpr;
6d0f6bcf	218	reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
7ca202f5 WD	219	memctl->memc_mptpr = reg;
	220
	221	udelay (10000);
	222
c3fafecf WD	223	/* Configure UPMB for NAND flash access */
	224	upmconfig (UPMB, (uint *) nand_flash_table,
	225	sizeof (nand_flash_table) / sizeof (uint));
	226
6d0f6bcf	227	memctl->memc_mbmr = CONFIG_SYS_MBMR_NAND;
c3fafecf	228
7ca202f5 WD	229	return (size_b0);
	230	}
	231
	232	/* ------------------------------------------------------------------------- */
	233
	234	/*
	235	* Check memory range for valid RAM. A simple memory test determines
	236	* the actually available RAM size between addresses `base' and
	237	* `base + maxsize'. Some (not all) hardware errors are detected:
	238	* - short between address lines
	239	* - short between data lines
	240	*/
	241
8b74bf31	242	static long int dram_size (long int mamr_value, long int *base, long int maxsize)
7ca202f5	243	{
6d0f6bcf	244	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
7ca202f5 WD	245	volatile memctl8xx_t *memctl = &immap->im_memctl;
	246
	247	memctl->memc_mamr = mamr_value;
	248
	249	return (get_ram_size(base, maxsize));
	250	}
4cfaf55e	251
8b74bf31	252
a367d426	253	#if defined(CONFIG_CP850)
	254
	255	#define DPRAM_VARNAME "KP850DIP"
	256	#define PARAM_ADDR 0x7C0
	257	#define NAME_ADDR 0x7F8
	258	#define BOARD_NAME "KP01"
	259	#define DEFAULT_LB "241111"
4cfaf55e	260
a367d426	261	int misc_init_r(void)
	262	{
	263	int iCompatMode = 0;
	264	char *pParam = NULL;
	265	char *envlb;
610cf367 WD	266
610cf367 WD	267	/*
a367d426	268	First byte in CPLD read address space signals compatibility mode
	269	0 - cp850
	270	1 - kp852
	271	*/
6d0f6bcf	272	pParam = (char*)(CONFIG_SYS_CPLD_BASE);
a367d426	273	if( *pParam != 0)
a367d426	274	iCompatMode = 1;
610cf367	275
a367d426	276	if ( iCompatMode != 0) {
610cf367	277	/*
a367d426	278	In KP852 compatibility mode we have to write to
	279	DPRAM as early as possible the binary coded
	280	line config and board name.
	281	The line config is derived from the environment
	282	variable DPRAM_VARNAME by converting from ASCII
	283	to binary per character.
	284	*/
	285	if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) {
	286	setenv( DPRAM_VARNAME, DEFAULT_LB);
	287	envlb = DEFAULT_LB;
	288	}
610cf367	289
a367d426	290	/* Status string */
	291	printf("Mode: KP852(LB=%s)\n", envlb);
	292
	293	/* copy appl init */
	294	pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR);
	295	while (*envlb) {
	296	(pParam++) = (envlb++) - '0';
	297	}
	298	*pParam = '\0';
	299
	300	/* copy board id */
	301	pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR);
	302	strcpy( pParam, BOARD_NAME);
	303	} else {
	304	puts("Mode: CP850\n");
	305	}
610cf367	306
a367d426	307	return 0;
4cfaf55e WD	308	}
4cfaf55e WD	309	#endif