[people/ms/u-boot.git] / board / siemens / pcu_e / pcu_e.c

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <i2c.h>
#include <command.h>

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);
static void puma_status (void);
static void puma_set_mode (int mode);
static int puma_init_done (void);
static void puma_load (ulong addr, ulong len);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

/*
 * 50 MHz SDRAM access using UPM A
 */
const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
	0x1ffddc47,		/* last */
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
	0x1ffddc35, 0xefceac34, 0x1f3d5c35,	/* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
	0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47,	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,

	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47,	/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
	0xf0affc00, 0xe1beec04, 0x1ffddc47,	/* last */
	_NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	0xfffffc84, 0xfffffc07,	/* last */
	_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7ffffc07,		/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */

/*
 * PUMA access using UPM B
 */
const uint puma_table[] = {
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_,
	/*
	 * Precharge and MRS
	 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x0ffff804, 0x0ffff400, 0x3ffffc47,	/* last */
	_NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7ffffc07,		/* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_,
};

/* ------------------------------------------------------------------------- */


/*
 * Check Board Identity:
 *
 */

int checkboard (void)
{
	puts ("Board: Siemens PCU E\n");
	return (0);
}

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;
	long int size_b0, reg;
	int i;

	/*
	 * Configure UPMA for SDRAM
	 */
	upmconfig (UPMA, (uint *) sdram_table,
		   sizeof (sdram_table) / sizeof (uint));

	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

	/* burst length=4, burst type=sequential, CAS latency=2 */
	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller bank 2 to the SDRAM bank at preliminary address.
	 */
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
	memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
#else  /* XXX */
	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
#endif /* XXX */

	/* initialize memory address register */
	memctl->memc_mamr = CONFIG_SYS_MAMR;	/* refresh not enabled yet */

	/* mode initialization (offset 5) */
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	udelay (200);		/* 0x8000A105 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
#else  /* XXX */
	udelay (200);		/* 0x80004105 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
#endif /* XXX */

	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	udelay (1);		/* 0x8000A830 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
#else  /* XXX */
	udelay (1);		/* 0x80004830 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
#endif /* XXX */

#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	udelay (1);		/* 0x8000A106 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
#else  /* XXX */
	udelay (1);		/* 0x80004106 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
#endif /* XXX */

	reg = memctl->memc_mamr;
	reg &= ~MAMR_TLFA_MSK;	/* switch timer loop ... */
	reg |= MAMR_TLFA_4X;	/* ... to 4x */
	reg |= MAMR_PTAE;	/* enable refresh */
	memctl->memc_mamr = reg;

	udelay (200);

	/* Need at least 10 DRAM accesses to stabilize */
	for (i = 0; i < 10; ++i) {
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
		volatile unsigned long *addr =
			(volatile unsigned long *) SDRAM_BASE5_PRELIM;
#else  /* XXX */
		volatile unsigned long *addr =
			(volatile unsigned long *) SDRAM_BASE2_PRELIM;
#endif /* XXX */
		unsigned long val;

		val = *(addr + i);
		*(addr + i) = val;
	}

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 */
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
#else  /* XXX */
	size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */

	memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE;

	/*
	 * Final mapping:
	 */

#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
	memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
#else  /* XXX */
	memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
#endif /* XXX */
	udelay (1000);

	/*
	 * Configure UPMB for PUMA
	 */
	upmconfig (UPMB, (uint *) puma_table,
		   sizeof (puma_table) / sizeof (uint));

	return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int dram_size (long int mamr_value, long int *base,
			   long int maxsize)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size (base, maxsize));
}

/* ------------------------------------------------------------------------- */

#if PCU_E_WITH_SWAPPED_CS	/* XXX */
#define	ETH_CFG_BITS	(CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2  | CONFIG_SYS_PB_ETH_CFG3 )
#else  /* XXX */
#define	ETH_CFG_BITS	(CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \
			 CONFIG_SYS_PB_ETH_CFG2  | CONFIG_SYS_PB_ETH_CFG3 )
#endif /* XXX */

#define ETH_ALL_BITS	(ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET)

void reset_phy (void)
{
	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	ulong value;

	/* Configure all needed port pins for GPIO */
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
	immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
# else
	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* Set low */
# endif
	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* GPIO */
	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* active output */
	immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS;	/* output */
#endif /* XXX */
	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS);	/* GPIO */
	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS);	/* active output */

	value = immr->im_cpm.cp_pbdat;

	/* Assert Powerdown and Reset signals */
	value |= CONFIG_SYS_PB_ETH_POWERDOWN;
	value &= ~(CONFIG_SYS_PB_ETH_RESET);

	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if !PCU_E_WITH_SWAPPED_CS
# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
	value |= CONFIG_SYS_PB_ETH_MDDIS;
# else
	value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
# endif
#endif
#ifdef CONFIG_SYS_ETH_CFG1_VALUE
	value |= CONFIG_SYS_PB_ETH_CFG1;
#else
	value &= ~(CONFIG_SYS_PB_ETH_CFG1);
#endif
#ifdef CONFIG_SYS_ETH_CFG2_VALUE
	value |= CONFIG_SYS_PB_ETH_CFG2;
#else
	value &= ~(CONFIG_SYS_PB_ETH_CFG2);
#endif
#ifdef CONFIG_SYS_ETH_CFG3_VALUE
	value |= CONFIG_SYS_PB_ETH_CFG3;
#else
	value &= ~(CONFIG_SYS_PB_ETH_CFG3);
#endif

	/* Drive output signals to initial state */
	immr->im_cpm.cp_pbdat = value;
	immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
	udelay (10000);

	/* De-assert Ethernet Powerdown */
	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* Enable PHY power */
	udelay (10000);

	/* de-assert RESET signal of PHY */
	immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET;
	udelay (1000);
}

/*-----------------------------------------------------------------------
 * Board Special Commands: access functions for "PUMA" FPGA
 */
#if defined(CONFIG_CMD_BSP)

#define	PUMA_READ_MODE	0
#define PUMA_LOAD_MODE	1

int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	ulong addr, len;

	switch (argc) {
	case 2:		/* PUMA reset */
		if (strncmp (argv[1], "stat", 4) == 0) {	/* Reset */
			puma_status ();
			return 0;
		}
		break;
	case 4:		/* PUMA load addr len */
		if (strcmp (argv[1], "load") != 0)
			break;

		addr = simple_strtoul (argv[2], NULL, 16);
		len = simple_strtoul (argv[3], NULL, 16);

		printf ("PUMA load: addr %08lX len %ld (0x%lX):  ",
			addr, len, len);
		puma_load (addr, len);

		return 0;
	default:
		break;
	}
	cmd_usage(cmdtp);
	return 1;
}

U_BOOT_CMD (puma, 4, 1, do_puma,
	    "puma    - access PUMA FPGA\n",
	    "status - print PUMA status\n"
	    "puma load addr len - load PUMA configuration data\n");

#endif

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static void puma_set_mode (int mode)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	/* disable PUMA in memory controller */
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	memctl->memc_br3 = 0;
#else  /* XXX */
	memctl->memc_br4 = 0;
#endif /* XXX */

	switch (mode) {
	case PUMA_READ_MODE:
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
		memctl->memc_or3 = PUMA_CONF_OR_READ;
		memctl->memc_br3 = PUMA_CONF_BR_READ;
#else  /* XXX */
		memctl->memc_or4 = PUMA_CONF_OR_READ;
		memctl->memc_br4 = PUMA_CONF_BR_READ;
#endif /* XXX */
		break;
	case PUMA_LOAD_MODE:
#if PCU_E_WITH_SWAPPED_CS	/* XXX */
		memctl->memc_or3 = PUMA_CONF_OR_LOAD;
		memctl->memc_br3 = PUMA_CONF_BR_LOAD;
#else  /* XXX */
		memctl->memc_or4 = PUMA_CONF_OR_READ;
		memctl->memc_br4 = PUMA_CONF_BR_READ;
#endif /* XXX */
		break;
	}
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

#define	PUMA_INIT_TIMEOUT	1000	/* max. 1000 ms = 1 second */

static void puma_load (ulong addr, ulong len)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE;	/* XXX ??? */
	uchar *data = (uchar *) addr;
	int i;

	/* align length */
	if (len & 1)
		++len;

	/* Reset FPGA */
	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT);	/* make input */
	immr->im_ioport.iop_pcso  &= ~(CONFIG_SYS_PC_PUMA_INIT);
	immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);

#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* GPIO */
	immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* active output */
	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* Set low */
	immr->im_cpm.cp_pbdir |=   CONFIG_SYS_PB_PUMA_PROG;		/* output */
#else
	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* GPIO */
	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* Set low */
	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* active output */
	immr->im_ioport.iop_padir |=   CONFIG_SYS_PA_PUMA_PROG;	/* output */
#endif /* XXX */
	udelay (100);

#if PCU_E_WITH_SWAPPED_CS	/* XXX */
	immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG;	/* release reset */
#else
	immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG;	/* release reset */
#endif /* XXX */

	/* wait until INIT indicates completion of reset */
	for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
		udelay (1000);
		if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
			break;
	}
	if (i == PUMA_INIT_TIMEOUT) {
		printf ("*** PUMA init timeout ***\n");
		return;
	}

	puma_set_mode (PUMA_LOAD_MODE);

	while (len--)
		*fpga_addr = *data++;

	puma_set_mode (PUMA_READ_MODE);

	puma_status ();
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static void puma_status (void)
{
	/* Check state */
	printf ("PUMA initialization is %scomplete\n",
		puma_init_done ()? "" : "NOT ");
}

/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */

static int puma_init_done (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	/* make sure pin is GPIO input */
	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
	immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);

	return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
}

/* ------------------------------------------------------------------------- */

int misc_init_r (void)
{
	ulong addr = 0;
	ulong len = 0;
	char *s;

	printf ("PUMA:  ");
	if (puma_init_done ()) {
		printf ("initialized\n");
		return 0;
	}

	if ((s = getenv ("puma_addr")) != NULL)
		addr = simple_strtoul (s, NULL, 16);

	if ((s = getenv ("puma_len")) != NULL)
		len = simple_strtoul (s, NULL, 16);

	if ((!addr) || (!len)) {
		printf ("net list undefined\n");
		return 0;
	}

	printf ("loading... ");

	puma_load (addr, len);
	return (0);
}

/* ------------------------------------------------------------------------- */
Commit	Line	Data
f8cac651 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc8xx.h>
	26	#include <commproc.h>
	27	#include <i2c.h>
	28	#include <command.h>
f8cac651 WD	29
	30	/* ------------------------------------------------------------------------- */
	31
	32	static long int dram_size (long int, long int *, long int);
	33	static void puma_status (void);
	34	static void puma_set_mode (int mode);
c83bf6a2	35	static int puma_init_done (void);
f8cac651 WD	36	static void puma_load (ulong addr, ulong len);
	37
	38	/* ------------------------------------------------------------------------- */
	39
	40	#define _NOT_USED_ 0xFFFFFFFF
	41
	42	/*
	43	* 50 MHz SDRAM access using UPM A
	44	*/
c83bf6a2	45	const uint sdram_table[] = {
f8cac651 WD	46	/*
	47	* Single Read. (Offset 0 in UPM RAM)
	48	*/
	49	0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
c83bf6a2	50	0x1ffddc47, /* last */
f8cac651 WD	51	/*
	52	* SDRAM Initialization (offset 5 in UPM RAM)
	53	*
8bde7f77 WD	54	* This is no UPM entry point. The following definition uses
	55	* the remaining space to establish an initialization
	56	* sequence, which is executed by a RUN command.
f8cac651 WD	57	*
f8cac651 WD	58	*/
c83bf6a2	59	0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
f8cac651 WD	60	/*
	61	* Burst Read. (Offset 8 in UPM RAM)
	62	*/
	63	0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
c83bf6a2	64	0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
f8cac651 WD	65	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	66	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	67
	68	/*
	69	* Single Write. (Offset 18 in UPM RAM)
	70	*/
c83bf6a2	71	0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
f8cac651 WD	72	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	73	/*
	74	* Burst Write. (Offset 20 in UPM RAM)
	75	*/
	76	0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
c83bf6a2 WD	77	0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
c83bf6a2 WD	78	_NOT_USED_,
f8cac651 WD	79	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	80	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	81	/*
	82	* Refresh (Offset 30 in UPM RAM)
	83	*/
	84	0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
c83bf6a2 WD	85	0xfffffc84, 0xfffffc07, /* last */
c83bf6a2 WD	86	_NOT_USED_, _NOT_USED_,
f8cac651 WD	87	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	88	/*
	89	* Exception. (Offset 3c in UPM RAM)
	90	*/
c83bf6a2 WD	91	0x7ffffc07, /* last */
c83bf6a2 WD	92	_NOT_USED_, _NOT_USED_, _NOT_USED_,
f8cac651 WD	93	};
	94
	95	/* ------------------------------------------------------------------------- */
	96
	97	/*
	98	* PUMA access using UPM B
	99	*/
c83bf6a2	100	const uint puma_table[] = {
f8cac651 WD	101	/*
	102	* Single Read. (Offset 0 in UPM RAM)
	103	*/
	104	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	105	_NOT_USED_,
	106	/*
	107	* Precharge and MRS
	108	*/
c83bf6a2	109	_NOT_USED_, _NOT_USED_, _NOT_USED_,
f8cac651 WD	110	/*
	111	* Burst Read. (Offset 8 in UPM RAM)
	112	*/
	113	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	114	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	115	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	116	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	117	/*
	118	* Single Write. (Offset 18 in UPM RAM)
	119	*/
c83bf6a2 WD	120	0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
c83bf6a2 WD	121	_NOT_USED_,
f8cac651 WD	122	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	123	/*
	124	* Burst Write. (Offset 20 in UPM RAM)
	125	*/
	126	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	127	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	128	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	129	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	130	/*
	131	* Refresh (Offset 30 in UPM RAM)
	132	*/
	133	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	134	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	135	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	136	/*
	137	* Exception. (Offset 3c in UPM RAM)
	138	*/
c83bf6a2 WD	139	0x7ffffc07, /* last */
c83bf6a2 WD	140	_NOT_USED_, _NOT_USED_, _NOT_USED_,
f8cac651 WD	141	};
	142
	143	/* ------------------------------------------------------------------------- */
	144
	145
	146	/*
	147	* Check Board Identity:
	148	*
	149	*/
	150
	151	int checkboard (void)
	152	{
	153	puts ("Board: Siemens PCU E\n");
	154	return (0);
	155	}
	156
	157	/* ------------------------------------------------------------------------- */
	158
9973e3c6	159	phys_size_t initdram (int board_type)
f8cac651	160	{
6d0f6bcf	161	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2 WD	162	volatile memctl8xx_t *memctl = &immr->im_memctl;
	163	long int size_b0, reg;
	164	int i;
f8cac651	165
c83bf6a2 WD	166	/*
	167	* Configure UPMA for SDRAM
	168	*/
	169	upmconfig (UPMA, (uint *) sdram_table,
	170	sizeof (sdram_table) / sizeof (uint));
f8cac651	171
6d0f6bcf	172	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
f8cac651	173
c83bf6a2 WD	174	/* burst length=4, burst type=sequential, CAS latency=2 */
c83bf6a2 WD	175	memctl->memc_mar = 0x00000088;
f8cac651	176
c83bf6a2 WD	177	/*
	178	* Map controller bank 2 to the SDRAM bank at preliminary address.
	179	*/
f8cac651	180	#if PCU_E_WITH_SWAPPED_CS /* XXX */
6d0f6bcf JCPV	181	memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
6d0f6bcf JCPV	182	memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
c83bf6a2	183	#else /* XXX */
6d0f6bcf JCPV	184	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
6d0f6bcf JCPV	185	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
c83bf6a2	186	#endif /* XXX */
f8cac651	187
c83bf6a2	188	/* initialize memory address register */
6d0f6bcf	189	memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */
f8cac651	190
c83bf6a2	191	/* mode initialization (offset 5) */
f8cac651	192	#if PCU_E_WITH_SWAPPED_CS /* XXX */
c83bf6a2 WD	193	udelay (200); /* 0x8000A105 */
	194	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS5 \| MCR_MLCF (1) \| MCR_MAD (0x05);
	195	#else /* XXX */
	196	udelay (200); /* 0x80004105 */
	197	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS2 \| MCR_MLCF (1) \| MCR_MAD (0x05);
	198	#endif /* XXX */
	199
	200	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
f8cac651	201	#if PCU_E_WITH_SWAPPED_CS /* XXX */
c83bf6a2 WD	202	udelay (1); /* 0x8000A830 */
	203	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS5 \| MCR_MLCF (8) \| MCR_MAD (0x30);
	204	#else /* XXX */
	205	udelay (1); /* 0x80004830 */
	206	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS2 \| MCR_MLCF (8) \| MCR_MAD (0x30);
	207	#endif /* XXX */
f8cac651 WD	208
f8cac651 WD	209	#if PCU_E_WITH_SWAPPED_CS /* XXX */
c83bf6a2 WD	210	udelay (1); /* 0x8000A106 */
	211	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS5 \| MCR_MLCF (1) \| MCR_MAD (0x06);
	212	#else /* XXX */
	213	udelay (1); /* 0x80004106 */
	214	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS2 \| MCR_MLCF (1) \| MCR_MAD (0x06);
	215	#endif /* XXX */
	216
	217	reg = memctl->memc_mamr;
	218	reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
	219	reg \|= MAMR_TLFA_4X; /* ... to 4x */
	220	reg \|= MAMR_PTAE; /* enable refresh */
	221	memctl->memc_mamr = reg;
	222
	223	udelay (200);
	224
	225	/* Need at least 10 DRAM accesses to stabilize */
	226	for (i = 0; i < 10; ++i) {
f8cac651	227	#if PCU_E_WITH_SWAPPED_CS /* XXX */
c83bf6a2 WD	228	volatile unsigned long *addr =
	229	(volatile unsigned long *) SDRAM_BASE5_PRELIM;
	230	#else /* XXX */
	231	volatile unsigned long *addr =
	232	(volatile unsigned long *) SDRAM_BASE2_PRELIM;
	233	#endif /* XXX */
	234	unsigned long val;
	235
	236	val = *(addr + i);
	237	*(addr + i) = val;
	238	}
	239
	240	/*
	241	* Check Bank 0 Memory Size for re-configuration
	242	*/
f8cac651	243	#if PCU_E_WITH_SWAPPED_CS /* XXX */
6d0f6bcf	244	size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
c83bf6a2	245	#else /* XXX */
6d0f6bcf	246	size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
c83bf6a2	247	#endif /* XXX */
f8cac651	248
6d0f6bcf	249	memctl->memc_mamr = CONFIG_SYS_MAMR \| MAMR_PTAE;
f8cac651	250
c83bf6a2 WD	251	/*
	252	* Final mapping:
	253	*/
f8cac651 WD	254
f8cac651 WD	255	#if PCU_E_WITH_SWAPPED_CS /* XXX */
c83bf6a2	256	memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) \| SDRAM_TIMING;
6d0f6bcf	257	memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
c83bf6a2 WD	258	#else /* XXX */
c83bf6a2 WD	259	memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) \| SDRAM_TIMING;
6d0f6bcf	260	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
c83bf6a2 WD	261	#endif /* XXX */
	262	udelay (1000);
	263
	264	/*
	265	* Configure UPMB for PUMA
	266	*/
	267	upmconfig (UPMB, (uint *) puma_table,
	268	sizeof (puma_table) / sizeof (uint));
	269
	270	return (size_b0);
f8cac651 WD	271	}
	272
	273	/* ------------------------------------------------------------------------- */
	274
	275	/*
	276	* Check memory range for valid RAM. A simple memory test determines
	277	* the actually available RAM size between addresses `base' and
	278	* `base + maxsize'. Some (not all) hardware errors are detected:
	279	* - short between address lines
	280	* - short between data lines
	281	*/
	282
c83bf6a2 WD	283	static long int dram_size (long int mamr_value, long int *base,
c83bf6a2 WD	284	long int maxsize)
f8cac651	285	{
6d0f6bcf	286	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2	287	volatile memctl8xx_t *memctl = &immr->im_memctl;
f8cac651	288
c83bf6a2	289	memctl->memc_mamr = mamr_value;
f8cac651	290
c83bf6a2	291	return (get_ram_size (base, maxsize));
f8cac651 WD	292	}
	293
	294	/* ------------------------------------------------------------------------- */
	295
c83bf6a2	296	#if PCU_E_WITH_SWAPPED_CS /* XXX */
6d0f6bcf	297	#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 \| CONFIG_SYS_PB_ETH_CFG2 \| CONFIG_SYS_PB_ETH_CFG3 )
c83bf6a2	298	#else /* XXX */
6d0f6bcf JCPV	299	#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS \| CONFIG_SYS_PB_ETH_CFG1 \| \
6d0f6bcf JCPV	300	CONFIG_SYS_PB_ETH_CFG2 \| CONFIG_SYS_PB_ETH_CFG3 )
f8cac651 WD	301	#endif /* XXX */
f8cac651 WD	302
6d0f6bcf	303	#define ETH_ALL_BITS (ETH_CFG_BITS \| CONFIG_SYS_PB_ETH_POWERDOWN \| CONFIG_SYS_PB_ETH_RESET)
f8cac651	304
c83bf6a2	305	void reset_phy (void)
f8cac651	306	{
6d0f6bcf	307	immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
f8cac651 WD	308	ulong value;
	309
	310	/* Configure all needed port pins for GPIO */
c83bf6a2	311	#if PCU_E_WITH_SWAPPED_CS /* XXX */
6d0f6bcf JCPV	312	# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
6d0f6bcf JCPV	313	immr->im_ioport.iop_padat \|= CONFIG_SYS_PA_ETH_MDDIS;
f8cac651	314	# else
6d0f6bcf	315	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */
f8cac651	316	# endif
6d0f6bcf JCPV	317	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */
	318	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */
	319	immr->im_ioport.iop_padir \|= CONFIG_SYS_PA_ETH_MDDIS; /* output */
f8cac651 WD	320	#endif /* XXX */
	321	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
	322	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
	323
c83bf6a2	324	value = immr->im_cpm.cp_pbdat;
f8cac651 WD	325
f8cac651 WD	326	/* Assert Powerdown and Reset signals */
6d0f6bcf JCPV	327	value \|= CONFIG_SYS_PB_ETH_POWERDOWN;
6d0f6bcf JCPV	328	value &= ~(CONFIG_SYS_PB_ETH_RESET);
f8cac651 WD	329
	330	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
	331	#if !PCU_E_WITH_SWAPPED_CS
6d0f6bcf JCPV	332	# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
6d0f6bcf JCPV	333	value \|= CONFIG_SYS_PB_ETH_MDDIS;
f8cac651	334	# else
6d0f6bcf	335	value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
f8cac651 WD	336	# endif
f8cac651 WD	337	#endif
6d0f6bcf JCPV	338	#ifdef CONFIG_SYS_ETH_CFG1_VALUE
6d0f6bcf JCPV	339	value \|= CONFIG_SYS_PB_ETH_CFG1;
f8cac651	340	#else
6d0f6bcf	341	value &= ~(CONFIG_SYS_PB_ETH_CFG1);
f8cac651	342	#endif
6d0f6bcf JCPV	343	#ifdef CONFIG_SYS_ETH_CFG2_VALUE
6d0f6bcf JCPV	344	value \|= CONFIG_SYS_PB_ETH_CFG2;
f8cac651	345	#else
6d0f6bcf	346	value &= ~(CONFIG_SYS_PB_ETH_CFG2);
f8cac651	347	#endif
6d0f6bcf JCPV	348	#ifdef CONFIG_SYS_ETH_CFG3_VALUE
6d0f6bcf JCPV	349	value \|= CONFIG_SYS_PB_ETH_CFG3;
f8cac651	350	#else
6d0f6bcf	351	value &= ~(CONFIG_SYS_PB_ETH_CFG3);
f8cac651 WD	352	#endif
	353
	354	/* Drive output signals to initial state */
c83bf6a2	355	immr->im_cpm.cp_pbdat = value;
f8cac651 WD	356	immr->im_cpm.cp_pbdir \|= ETH_ALL_BITS;
	357	udelay (10000);
	358
	359	/* De-assert Ethernet Powerdown */
6d0f6bcf	360	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
f8cac651 WD	361	udelay (10000);
	362
	363	/* de-assert RESET signal of PHY */
6d0f6bcf	364	immr->im_cpm.cp_pbdat \|= CONFIG_SYS_PB_ETH_RESET;
f8cac651 WD	365	udelay (1000);
	366	}
	367
	368	/*-----------------------------------------------------------------------
	369	* Board Special Commands: access functions for "PUMA" FPGA
	370	*/
ab3abcba	371	#if defined(CONFIG_CMD_BSP)
f8cac651 WD	372
	373	#define PUMA_READ_MODE 0
	374	#define PUMA_LOAD_MODE 1
	375
c83bf6a2	376	int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
f8cac651 WD	377	{
	378	ulong addr, len;
	379
	380	switch (argc) {
c83bf6a2 WD	381	case 2: /* PUMA reset */
c83bf6a2 WD	382	if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
f8cac651 WD	383	puma_status ();
	384	return 0;
	385	}
	386	break;
c83bf6a2 WD	387	case 4: /* PUMA load addr len */
c83bf6a2 WD	388	if (strcmp (argv[1], "load") != 0)
f8cac651 WD	389	break;
f8cac651 WD	390
c83bf6a2 WD	391	addr = simple_strtoul (argv[2], NULL, 16);
c83bf6a2 WD	392	len = simple_strtoul (argv[3], NULL, 16);
f8cac651 WD	393
	394	printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
	395	addr, len, len);
	396	puma_load (addr, len);
	397
	398	return 0;
	399	default:
	400	break;
	401	}
62c3ae7c	402	cmd_usage(cmdtp);
f8cac651 WD	403	return 1;
	404	}
	405
c83bf6a2 WD	406	U_BOOT_CMD (puma, 4, 1, do_puma,
	407	"puma - access PUMA FPGA\n",
	408	"status - print PUMA status\n"
	409	"puma load addr len - load PUMA configuration data\n");
	410
d39b5741	411	#endif
f8cac651 WD	412
	413	/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
	414
	415	static void puma_set_mode (int mode)
	416	{
6d0f6bcf	417	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
f8cac651 WD	418	volatile memctl8xx_t *memctl = &immr->im_memctl;
	419
	420	/* disable PUMA in memory controller */
	421	#if PCU_E_WITH_SWAPPED_CS /* XXX */
c83bf6a2 WD	422	memctl->memc_br3 = 0;
	423	#else /* XXX */
	424	memctl->memc_br4 = 0;
	425	#endif /* XXX */
f8cac651 WD	426
	427	switch (mode) {
	428	case PUMA_READ_MODE:
	429	#if PCU_E_WITH_SWAPPED_CS /* XXX */
	430	memctl->memc_or3 = PUMA_CONF_OR_READ;
	431	memctl->memc_br3 = PUMA_CONF_BR_READ;
c83bf6a2	432	#else /* XXX */
f8cac651 WD	433	memctl->memc_or4 = PUMA_CONF_OR_READ;
f8cac651 WD	434	memctl->memc_br4 = PUMA_CONF_BR_READ;
c83bf6a2	435	#endif /* XXX */
f8cac651 WD	436	break;
	437	case PUMA_LOAD_MODE:
	438	#if PCU_E_WITH_SWAPPED_CS /* XXX */
	439	memctl->memc_or3 = PUMA_CONF_OR_LOAD;
	440	memctl->memc_br3 = PUMA_CONF_BR_LOAD;
c83bf6a2	441	#else /* XXX */
f8cac651 WD	442	memctl->memc_or4 = PUMA_CONF_OR_READ;
f8cac651 WD	443	memctl->memc_br4 = PUMA_CONF_BR_READ;
c83bf6a2	444	#endif /* XXX */
f8cac651 WD	445	break;
	446	}
	447	}
	448
	449	/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
	450
	451	#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
	452
	453	static void puma_load (ulong addr, ulong len)
	454	{
6d0f6bcf	455	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2 WD	456	volatile uchar fpga_addr = (volatile uchar ) PUMA_CONF_BASE; /* XXX ??? */
c83bf6a2 WD	457	uchar data = (uchar ) addr;
f8cac651 WD	458	int i;
	459
	460	/* align length */
	461	if (len & 1)
	462	++len;
	463
	464	/* Reset FPGA */
6d0f6bcf JCPV	465	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */
	466	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT);
	467	immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);
f8cac651	468
c83bf6a2	469	#if PCU_E_WITH_SWAPPED_CS /* XXX */
6d0f6bcf JCPV	470	immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */
	471	immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */
	472	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */
	473	immr->im_cpm.cp_pbdir \|= CONFIG_SYS_PB_PUMA_PROG; /* output */
f8cac651	474	#else
6d0f6bcf JCPV	475	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */
	476	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */
	477	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */
	478	immr->im_ioport.iop_padir \|= CONFIG_SYS_PA_PUMA_PROG; /* output */
f8cac651 WD	479	#endif /* XXX */
	480	udelay (100);
	481
c83bf6a2	482	#if PCU_E_WITH_SWAPPED_CS /* XXX */
6d0f6bcf	483	immr->im_cpm.cp_pbdat \|= CONFIG_SYS_PB_PUMA_PROG; /* release reset */
f8cac651	484	#else
6d0f6bcf	485	immr->im_ioport.iop_padat \|= CONFIG_SYS_PA_PUMA_PROG; /* release reset */
f8cac651 WD	486	#endif /* XXX */
	487
	488	/* wait until INIT indicates completion of reset */
c83bf6a2	489	for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
f8cac651	490	udelay (1000);
6d0f6bcf	491	if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
f8cac651 WD	492	break;
	493	}
	494	if (i == PUMA_INIT_TIMEOUT) {
	495	printf ("* PUMA init timeout *\n");
	496	return;
	497	}
	498
	499	puma_set_mode (PUMA_LOAD_MODE);
	500
	501	while (len--)
	502	fpga_addr = data++;
	503
	504	puma_set_mode (PUMA_READ_MODE);
	505
	506	puma_status ();
	507	}
	508
	509	/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
	510
	511	static void puma_status (void)
	512	{
	513	/* Check state */
	514	printf ("PUMA initialization is %scomplete\n",
c83bf6a2	515	puma_init_done ()? "" : "NOT ");
f8cac651 WD	516	}
	517
	518	/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
	519
	520	static int puma_init_done (void)
	521	{
6d0f6bcf	522	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
f8cac651 WD	523
f8cac651 WD	524	/* make sure pin is GPIO input */
6d0f6bcf JCPV	525	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
	526	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
	527	immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);
f8cac651	528
6d0f6bcf	529	return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
f8cac651 WD	530	}
	531
	532	/* ------------------------------------------------------------------------- */
	533
	534	int misc_init_r (void)
	535	{
	536	ulong addr = 0;
c83bf6a2	537	ulong len = 0;
f8cac651 WD	538	char *s;
	539
	540	printf ("PUMA: ");
c83bf6a2	541	if (puma_init_done ()) {
f8cac651 WD	542	printf ("initialized\n");
	543	return 0;
	544	}
	545
c83bf6a2 WD	546	if ((s = getenv ("puma_addr")) != NULL)
c83bf6a2 WD	547	addr = simple_strtoul (s, NULL, 16);
f8cac651	548
c83bf6a2 WD	549	if ((s = getenv ("puma_len")) != NULL)
c83bf6a2 WD	550	len = simple_strtoul (s, NULL, 16);
f8cac651 WD	551
	552	if ((!addr) \|\| (!len)) {
	553	printf ("net list undefined\n");
	554	return 0;
	555	}
	556
	557	printf ("loading... ");
	558
	559	puma_load (addr, len);
	560	return (0);
	561	}
	562
	563	/* ------------------------------------------------------------------------- */