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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
a4d88920 SDPP |
3 | config IDENT_STRING |
4 | default " Allwinner Technology" | |
5 | ||
53b5bf3c SG |
6 | config SPL_GPIO_SUPPORT |
7 | default y | |
8 | ||
77d2f7f5 SG |
9 | config SPL_LIBCOMMON_SUPPORT |
10 | default y | |
11 | ||
1646eba8 SG |
12 | config SPL_LIBDISK_SUPPORT |
13 | default y | |
14 | ||
cc4288ef SG |
15 | config SPL_LIBGENERIC_SUPPORT |
16 | default y | |
17 | ||
1fdf7c64 SG |
18 | config SPL_MMC_SUPPORT |
19 | default y | |
20 | ||
2253797d SG |
21 | config SPL_POWER_SUPPORT |
22 | default y | |
23 | ||
e00f76ce SG |
24 | config SPL_SERIAL_SUPPORT |
25 | default y | |
26 | ||
44d8ae5b HG |
27 | # Note only one of these may be selected at a time! But hidden choices are |
28 | # not supported by Kconfig | |
29 | config SUNXI_GEN_SUN4I | |
30 | bool | |
31 | ---help--- | |
32 | Select this for sunxi SoCs which have resets and clocks set up | |
33 | as the original A10 (mach-sun4i). | |
34 | ||
35 | config SUNXI_GEN_SUN6I | |
36 | bool | |
37 | ---help--- | |
38 | Select this for sunxi SoCs which have sun6i like periphery, like | |
39 | separate ahb reset control registers, custom pmic bus, new style | |
40 | watchdog, etc. | |
41 | ||
42 | ||
2c7e3b90 IC |
43 | choice |
44 | prompt "Sunxi SoC Variant" | |
3da9536e | 45 | optional |
2c7e3b90 | 46 | |
c3be2793 | 47 | config MACH_SUN4I |
2c7e3b90 IC |
48 | bool "sun4i (Allwinner A10)" |
49 | select CPU_V7 | |
44d8ae5b | 50 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
51 | select SUPPORT_SPL |
52 | ||
c3be2793 | 53 | config MACH_SUN5I |
2c7e3b90 IC |
54 | bool "sun5i (Allwinner A13)" |
55 | select CPU_V7 | |
44d8ae5b | 56 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
57 | select SUPPORT_SPL |
58 | ||
c3be2793 | 59 | config MACH_SUN6I |
2c7e3b90 IC |
60 | bool "sun6i (Allwinner A31)" |
61 | select CPU_V7 | |
cc08ea4c CYT |
62 | select CPU_V7_HAS_NONSEC |
63 | select CPU_V7_HAS_VIRT | |
217f92bb | 64 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 65 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 66 | select SUPPORT_SPL |
cc08ea4c | 67 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 68 | |
c3be2793 | 69 | config MACH_SUN7I |
2c7e3b90 IC |
70 | bool "sun7i (Allwinner A20)" |
71 | select CPU_V7 | |
ea624e19 HG |
72 | select CPU_V7_HAS_NONSEC |
73 | select CPU_V7_HAS_VIRT | |
217f92bb | 74 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 75 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 76 | select SUPPORT_SPL |
b366fb92 | 77 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 78 | |
5e6bacdb | 79 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
80 | bool "sun8i (Allwinner A23)" |
81 | select CPU_V7 | |
014414f5 CYT |
82 | select CPU_V7_HAS_NONSEC |
83 | select CPU_V7_HAS_VIRT | |
217f92bb | 84 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 85 | select SUNXI_GEN_SUN6I |
08fd1479 | 86 | select SUPPORT_SPL |
014414f5 | 87 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 88 | |
8c3dacff VP |
89 | config MACH_SUN8I_A33 |
90 | bool "sun8i (Allwinner A33)" | |
91 | select CPU_V7 | |
014414f5 CYT |
92 | select CPU_V7_HAS_NONSEC |
93 | select CPU_V7_HAS_VIRT | |
217f92bb | 94 | select ARCH_SUPPORT_PSCI |
8c3dacff VP |
95 | select SUNXI_GEN_SUN6I |
96 | select SUPPORT_SPL | |
014414f5 | 97 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
8c3dacff | 98 | |
a81b7995 CYT |
99 | config MACH_SUN8I_A83T |
100 | bool "sun8i (Allwinner A83T)" | |
101 | select CPU_V7 | |
102 | select SUNXI_GEN_SUN6I | |
103 | select SUPPORT_SPL | |
104 | ||
1c27b7dc JK |
105 | config MACH_SUN8I_H3 |
106 | bool "sun8i (Allwinner H3)" | |
107 | select CPU_V7 | |
853f6d1e CYT |
108 | select CPU_V7_HAS_NONSEC |
109 | select CPU_V7_HAS_VIRT | |
217f92bb | 110 | select ARCH_SUPPORT_PSCI |
1c27b7dc | 111 | select SUNXI_GEN_SUN6I |
0404d53f | 112 | select SUPPORT_SPL |
853f6d1e | 113 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
1c27b7dc | 114 | |
1871a8ca HG |
115 | config MACH_SUN9I |
116 | bool "sun9i (Allwinner A80)" | |
117 | select CPU_V7 | |
118 | select SUNXI_GEN_SUN6I | |
119 | ||
a81b7995 CYT |
120 | config MACH_SUN50I |
121 | bool "sun50i (Allwinner A64)" | |
122 | select ARM64 | |
123 | select SUNXI_GEN_SUN6I | |
124 | ||
2c7e3b90 | 125 | endchoice |
8a6564da | 126 | |
5e6bacdb HG |
127 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
128 | config MACH_SUN8I | |
129 | bool | |
762e24a0 | 130 | default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T |
5e6bacdb | 131 | |
f5fd8caf VP |
132 | config DRAM_TYPE |
133 | int "sunxi dram type" | |
134 | depends on MACH_SUN8I_A83T | |
135 | default 3 | |
136 | ---help--- | |
137 | Set the dram type, 3: DDR3, 7: LPDDR3 | |
5e6bacdb | 138 | |
37781a1a | 139 | config DRAM_CLK |
8ffc487c HG |
140 | int "sunxi dram clock speed" |
141 | default 312 if MACH_SUN6I || MACH_SUN8I | |
142 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
37781a1a HG |
143 | ---help--- |
144 | Set the dram clock speed, valid range 240 - 480, must be a multiple | |
e1a0888e | 145 | of 24. |
37781a1a | 146 | |
47e3501a SS |
147 | if MACH_SUN5I || MACH_SUN7I |
148 | config DRAM_MBUS_CLK | |
149 | int "sunxi mbus clock speed" | |
150 | default 300 | |
151 | ---help--- | |
152 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
153 | ||
154 | endif | |
155 | ||
37781a1a | 156 | config DRAM_ZQ |
8ffc487c HG |
157 | int "sunxi dram zq value" |
158 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
159 | default 127 if MACH_SUN7I | |
37781a1a | 160 | ---help--- |
e1a0888e | 161 | Set the dram zq value. |
8ffc487c | 162 | |
8975cdf4 HG |
163 | config DRAM_ODT_EN |
164 | bool "sunxi dram odt enable" | |
165 | default n if !MACH_SUN8I_A23 | |
166 | default y if MACH_SUN8I_A23 | |
167 | ---help--- | |
168 | Select this to enable dram odt (on die termination). | |
169 | ||
8ffc487c HG |
170 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
171 | config DRAM_EMR1 | |
172 | int "sunxi dram emr1 value" | |
173 | default 0 if MACH_SUN4I | |
174 | default 4 if MACH_SUN5I || MACH_SUN7I | |
175 | ---help--- | |
e1a0888e | 176 | Set the dram controller emr1 value. |
d133647a | 177 | |
47e3501a SS |
178 | config DRAM_TPR3 |
179 | hex "sunxi dram tpr3 value" | |
180 | default 0 | |
181 | ---help--- | |
182 | Set the dram controller tpr3 parameter. This parameter configures | |
183 | the delay on the command lane and also phase shifts, which are | |
184 | applied for sampling incoming read data. The default value 0 | |
185 | means that no phase/delay adjustments are necessary. Properly | |
186 | configuring this parameter increases reliability at high DRAM | |
187 | clock speeds. | |
188 | ||
189 | config DRAM_DQS_GATING_DELAY | |
190 | hex "sunxi dram dqs_gating_delay value" | |
191 | default 0 | |
192 | ---help--- | |
193 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
194 | encodes the DQS gating delay for each byte lane. The delay | |
195 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
196 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
197 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
198 | The default value 0 means autodetection. The results of hardware | |
199 | autodetection are not very reliable and depend on the chip | |
200 | temperature (sometimes producing different results on cold start | |
201 | and warm reboot). But the accuracy of hardware autodetection | |
202 | is usually good enough, unless running at really high DRAM | |
203 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
204 | ||
d133647a SS |
205 | choice |
206 | prompt "sunxi dram timings" | |
207 | default DRAM_TIMINGS_VENDOR_MAGIC | |
208 | ---help--- | |
209 | Select the timings of the DDR3 chips. | |
210 | ||
211 | config DRAM_TIMINGS_VENDOR_MAGIC | |
212 | bool "Magic vendor timings from Android" | |
213 | ---help--- | |
214 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
215 | ||
216 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
217 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
218 | ---help--- | |
219 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
220 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
221 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
222 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
223 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
224 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
225 | uses a bit faster timings than DDR3-1333H). | |
226 | ||
227 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
228 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
229 | ---help--- | |
230 | Use the timings of the slowest possible JEDEC speed bin for the | |
231 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
232 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
233 | ||
234 | endchoice | |
235 | ||
37781a1a HG |
236 | endif |
237 | ||
8975cdf4 HG |
238 | if MACH_SUN8I_A23 |
239 | config DRAM_ODT_CORRECTION | |
240 | int "sunxi dram odt correction value" | |
241 | default 0 | |
242 | ---help--- | |
243 | Set the dram odt correction value (range -255 - 255). In allwinner | |
244 | fex files, this option is found in bits 8-15 of the u32 odt_en variable | |
245 | in the [dram] section. When bit 31 of the odt_en variable is set | |
246 | then the correction is negative. Usually the value for this is 0. | |
247 | endif | |
248 | ||
e71b422b | 249 | config SYS_CLK_FREQ |
d96ebc46 | 250 | default 816000000 if MACH_SUN50I |
e71b422b IP |
251 | default 912000000 if MACH_SUN7I |
252 | default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
253 | ||
8a6564da | 254 | config SYS_CONFIG_NAME |
c3be2793 IC |
255 | default "sun4i" if MACH_SUN4I |
256 | default "sun5i" if MACH_SUN5I | |
257 | default "sun6i" if MACH_SUN6I | |
258 | default "sun7i" if MACH_SUN7I | |
259 | default "sun8i" if MACH_SUN8I | |
1871a8ca | 260 | default "sun9i" if MACH_SUN9I |
d96ebc46 | 261 | default "sun50i" if MACH_SUN50I |
dd84058d | 262 | |
dd84058d | 263 | config SYS_BOARD |
dd84058d MY |
264 | default "sunxi" |
265 | ||
266 | config SYS_SOC | |
dd84058d MY |
267 | default "sunxi" |
268 | ||
f0ce28e9 SS |
269 | config UART0_PORT_F |
270 | bool "UART0 on MicroSD breakout board" | |
f0ce28e9 SS |
271 | default n |
272 | ---help--- | |
273 | Repurpose the SD card slot for getting access to the UART0 serial | |
274 | console. Primarily useful only for low level u-boot debugging on | |
275 | tablets, where normal UART0 is difficult to access and requires | |
276 | device disassembly and/or soldering. As the SD card can't be used | |
277 | at the same time, the system can be only booted in the FEL mode. | |
278 | Only enable this if you really know what you are doing. | |
279 | ||
accc9e44 | 280 | config OLD_SUNXI_KERNEL_COMPAT |
ab65006b | 281 | bool "Enable workarounds for booting old kernels" |
accc9e44 HG |
282 | default n |
283 | ---help--- | |
284 | Set this to enable various workarounds for old kernels, this results in | |
285 | sub-optimal settings for newer kernels, only enable if needed. | |
286 | ||
44c79879 MR |
287 | config MMC |
288 | depends on !UART0_PORT_F | |
289 | default y if ARCH_SUNXI | |
290 | ||
cd82113a HG |
291 | config MMC0_CD_PIN |
292 | string "Card detect pin for mmc0" | |
acdab175 | 293 | default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I |
cd82113a HG |
294 | default "" |
295 | ---help--- | |
296 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
297 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
298 | PH1 for pin 1 of port H. | |
299 | ||
300 | config MMC1_CD_PIN | |
301 | string "Card detect pin for mmc1" | |
302 | default "" | |
303 | ---help--- | |
304 | See MMC0_CD_PIN help text. | |
305 | ||
306 | config MMC2_CD_PIN | |
307 | string "Card detect pin for mmc2" | |
308 | default "" | |
309 | ---help--- | |
310 | See MMC0_CD_PIN help text. | |
311 | ||
312 | config MMC3_CD_PIN | |
313 | string "Card detect pin for mmc3" | |
314 | default "" | |
315 | ---help--- | |
316 | See MMC0_CD_PIN help text. | |
317 | ||
8deacca9 PK |
318 | config MMC1_PINS |
319 | string "Pins for mmc1" | |
320 | default "" | |
321 | ---help--- | |
322 | Set the pins used for mmc1, when applicable. This takes a string in the | |
323 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
324 | ||
325 | config MMC2_PINS | |
326 | string "Pins for mmc2" | |
327 | default "" | |
328 | ---help--- | |
329 | See MMC1_PINS help text. | |
330 | ||
331 | config MMC3_PINS | |
332 | string "Pins for mmc3" | |
333 | default "" | |
334 | ---help--- | |
335 | See MMC1_PINS help text. | |
336 | ||
2ccfac01 HG |
337 | config MMC_SUNXI_SLOT_EXTRA |
338 | int "mmc extra slot number" | |
339 | default -1 | |
340 | ---help--- | |
341 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
342 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
343 | support for this. | |
344 | ||
2c3c3ecb HG |
345 | config INITIAL_USB_SCAN_DELAY |
346 | int "delay initial usb scan by x ms to allow builtin devices to init" | |
347 | default 0 | |
348 | ---help--- | |
349 | Some boards have on board usb devices which need longer than the | |
350 | USB spec's 1 second to connect from board powerup. Set this config | |
351 | option to a non 0 value to add an extra delay before the first usb | |
352 | bus scan. | |
353 | ||
4458b7a6 HG |
354 | config USB0_VBUS_PIN |
355 | string "Vbus enable pin for usb0 (otg)" | |
356 | default "" | |
357 | ---help--- | |
358 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
359 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
360 | ||
52defe8f HG |
361 | config USB0_VBUS_DET |
362 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
363 | default "" |
364 | ---help--- | |
365 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
366 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
367 | ||
48c06c98 HG |
368 | config USB0_ID_DET |
369 | string "ID detect pin for usb0 (otg)" | |
370 | default "" | |
371 | ---help--- | |
372 | Set the ID detect pin for usb0 (otg). This takes a string in the | |
373 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
374 | ||
115200ce HG |
375 | config USB1_VBUS_PIN |
376 | string "Vbus enable pin for usb1 (ehci0)" | |
377 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 378 | default "PH27" if MACH_SUN6I |
115200ce HG |
379 | ---help--- |
380 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
381 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
382 | PH1 for pin 1 of port H. | |
383 | ||
384 | config USB2_VBUS_PIN | |
385 | string "Vbus enable pin for usb2 (ehci1)" | |
386 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 387 | default "PH24" if MACH_SUN6I |
115200ce HG |
388 | ---help--- |
389 | See USB1_VBUS_PIN help text. | |
390 | ||
60fa6301 HG |
391 | config USB3_VBUS_PIN |
392 | string "Vbus enable pin for usb3 (ehci2)" | |
393 | default "" | |
394 | ---help--- | |
395 | See USB1_VBUS_PIN help text. | |
396 | ||
6c739c5d PK |
397 | config I2C0_ENABLE |
398 | bool "Enable I2C/TWI controller 0" | |
399 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
400 | default n if MACH_SUN6I || MACH_SUN8I | |
0878a8a7 | 401 | select CMD_I2C |
6c739c5d PK |
402 | ---help--- |
403 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
404 | its clock and setting up the bus. This is especially useful on devices | |
405 | with slaves connected to the bus or with pins exposed through e.g. an | |
406 | expansion port/header. | |
407 | ||
408 | config I2C1_ENABLE | |
409 | bool "Enable I2C/TWI controller 1" | |
410 | default n | |
0878a8a7 | 411 | select CMD_I2C |
6c739c5d PK |
412 | ---help--- |
413 | See I2C0_ENABLE help text. | |
414 | ||
415 | config I2C2_ENABLE | |
416 | bool "Enable I2C/TWI controller 2" | |
417 | default n | |
0878a8a7 | 418 | select CMD_I2C |
6c739c5d PK |
419 | ---help--- |
420 | See I2C0_ENABLE help text. | |
421 | ||
422 | if MACH_SUN6I || MACH_SUN7I | |
423 | config I2C3_ENABLE | |
424 | bool "Enable I2C/TWI controller 3" | |
425 | default n | |
0878a8a7 | 426 | select CMD_I2C |
6c739c5d PK |
427 | ---help--- |
428 | See I2C0_ENABLE help text. | |
429 | endif | |
430 | ||
0d8382ae | 431 | if SUNXI_GEN_SUN6I |
9d082687 JW |
432 | config R_I2C_ENABLE |
433 | bool "Enable the PRCM I2C/TWI controller" | |
0d8382ae JW |
434 | # This is used for the pmic on H3 |
435 | default y if SY8106A_POWER | |
0878a8a7 | 436 | select CMD_I2C |
9d082687 JW |
437 | ---help--- |
438 | Set this to y to enable the I2C controller which is part of the PRCM. | |
0d8382ae | 439 | endif |
9d082687 | 440 | |
6c739c5d PK |
441 | if MACH_SUN7I |
442 | config I2C4_ENABLE | |
443 | bool "Enable I2C/TWI controller 4" | |
444 | default n | |
0878a8a7 | 445 | select CMD_I2C |
6c739c5d PK |
446 | ---help--- |
447 | See I2C0_ENABLE help text. | |
448 | endif | |
449 | ||
2fcf033d | 450 | config AXP_GPIO |
ab65006b | 451 | bool "Enable support for gpio-s on axp PMICs" |
2fcf033d HG |
452 | default n |
453 | ---help--- | |
454 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
455 | ||
7f2c521f | 456 | config VIDEO |
ab65006b | 457 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
fa855d3d | 458 | depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I |
7f2c521f LV |
459 | default y |
460 | ---help--- | |
2dae800f HG |
461 | Say Y here to add support for using a cfb console on the HDMI, LCD |
462 | or VGA output found on most sunxi devices. See doc/README.video for | |
463 | info on how to select the video output and mode. | |
464 | ||
2fbf091a | 465 | config VIDEO_HDMI |
ab65006b | 466 | bool "HDMI output support" |
2fbf091a HG |
467 | depends on VIDEO && !MACH_SUN8I |
468 | default y | |
469 | ---help--- | |
470 | Say Y here to add support for outputting video over HDMI. | |
471 | ||
d9786d23 | 472 | config VIDEO_VGA |
ab65006b | 473 | bool "VGA output support" |
d9786d23 HG |
474 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
475 | default n | |
476 | ---help--- | |
477 | Say Y here to add support for outputting video over VGA. | |
478 | ||
e2bbdfb1 | 479 | config VIDEO_VGA_VIA_LCD |
ab65006b | 480 | bool "VGA via LCD controller support" |
2583d5b1 | 481 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
482 | default n |
483 | ---help--- | |
484 | Say Y here to add support for external DACs connected to the parallel | |
485 | LCD interface driving a VGA connector, such as found on the | |
486 | Olimex A13 boards. | |
487 | ||
fb75d972 | 488 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
ab65006b | 489 | bool "Force sync active high for VGA via LCD controller support" |
fb75d972 HG |
490 | depends on VIDEO_VGA_VIA_LCD |
491 | default n | |
492 | ---help--- | |
493 | Say Y here if you've a board which uses opendrain drivers for the vga | |
494 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
495 | positive edges for a stable video output, so on boards with opendrain | |
496 | drivers the sync signals must always be active high. | |
497 | ||
507e27df CYT |
498 | config VIDEO_VGA_EXTERNAL_DAC_EN |
499 | string "LCD panel power enable pin" | |
500 | depends on VIDEO_VGA_VIA_LCD | |
501 | default "" | |
502 | ---help--- | |
503 | Set the enable pin for the external VGA DAC. This takes a string in the | |
504 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
505 | ||
39920c81 | 506 | config VIDEO_COMPOSITE |
ab65006b | 507 | bool "Composite video output support" |
39920c81 HG |
508 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
509 | default n | |
510 | ---help--- | |
511 | Say Y here to add support for outputting composite video. | |
512 | ||
2dae800f HG |
513 | config VIDEO_LCD_MODE |
514 | string "LCD panel timing details" | |
515 | depends on VIDEO | |
516 | default "" | |
517 | ---help--- | |
518 | LCD panel timing details string, leave empty if there is no LCD panel. | |
519 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
520 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
8addd3ed | 521 | Also see: http://linux-sunxi.org/LCD |
2dae800f | 522 | |
6515032e HG |
523 | config VIDEO_LCD_DCLK_PHASE |
524 | int "LCD panel display clock phase" | |
525 | depends on VIDEO | |
526 | default 1 | |
527 | ---help--- | |
528 | Select LCD panel display clock phase shift, range 0-3. | |
529 | ||
2dae800f HG |
530 | config VIDEO_LCD_POWER |
531 | string "LCD panel power enable pin" | |
532 | depends on VIDEO | |
533 | default "" | |
534 | ---help--- | |
535 | Set the power enable pin for the LCD panel. This takes a string in the | |
536 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
537 | ||
242e3d89 HG |
538 | config VIDEO_LCD_RESET |
539 | string "LCD panel reset pin" | |
540 | depends on VIDEO | |
541 | default "" | |
542 | ---help--- | |
543 | Set the reset pin for the LCD panel. This takes a string in the format | |
544 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
545 | ||
2dae800f HG |
546 | config VIDEO_LCD_BL_EN |
547 | string "LCD panel backlight enable pin" | |
548 | depends on VIDEO | |
549 | default "" | |
550 | ---help--- | |
551 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
552 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
553 | port H. | |
554 | ||
555 | config VIDEO_LCD_BL_PWM | |
556 | string "LCD panel backlight pwm pin" | |
557 | depends on VIDEO | |
558 | default "" | |
559 | ---help--- | |
560 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
561 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 562 | |
a7403ae8 HG |
563 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
564 | bool "LCD panel backlight pwm is inverted" | |
565 | depends on VIDEO | |
566 | default y | |
567 | ---help--- | |
568 | Set this if the backlight pwm output is active low. | |
569 | ||
55410089 HG |
570 | config VIDEO_LCD_PANEL_I2C |
571 | bool "LCD panel needs to be configured via i2c" | |
572 | depends on VIDEO | |
1fc42018 | 573 | default n |
0878a8a7 | 574 | select CMD_I2C |
55410089 HG |
575 | ---help--- |
576 | Say y here if the LCD panel needs to be configured via i2c. This | |
577 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
578 | ||
579 | config VIDEO_LCD_PANEL_I2C_SDA | |
580 | string "LCD panel i2c interface SDA pin" | |
581 | depends on VIDEO_LCD_PANEL_I2C | |
582 | default "PG12" | |
583 | ---help--- | |
584 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
585 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
586 | ||
587 | config VIDEO_LCD_PANEL_I2C_SCL | |
588 | string "LCD panel i2c interface SCL pin" | |
589 | depends on VIDEO_LCD_PANEL_I2C | |
590 | default "PG10" | |
591 | ---help--- | |
592 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
593 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
594 | ||
213480e1 HG |
595 | |
596 | # Note only one of these may be selected at a time! But hidden choices are | |
597 | # not supported by Kconfig | |
598 | config VIDEO_LCD_IF_PARALLEL | |
599 | bool | |
600 | ||
601 | config VIDEO_LCD_IF_LVDS | |
602 | bool | |
603 | ||
604 | ||
605 | choice | |
606 | prompt "LCD panel support" | |
607 | depends on VIDEO | |
608 | ---help--- | |
609 | Select which type of LCD panel to support. | |
610 | ||
611 | config VIDEO_LCD_PANEL_PARALLEL | |
612 | bool "Generic parallel interface LCD panel" | |
613 | select VIDEO_LCD_IF_PARALLEL | |
614 | ||
615 | config VIDEO_LCD_PANEL_LVDS | |
616 | bool "Generic lvds interface LCD panel" | |
617 | select VIDEO_LCD_IF_LVDS | |
618 | ||
97ece830 SS |
619 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
620 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
621 | select VIDEO_LCD_SSD2828 | |
622 | select VIDEO_LCD_IF_PARALLEL | |
623 | ---help--- | |
c1cfd519 HG |
624 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
625 | ||
626 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 | |
627 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" | |
628 | select VIDEO_LCD_ANX9804 | |
629 | select VIDEO_LCD_IF_PARALLEL | |
630 | select VIDEO_LCD_PANEL_I2C | |
631 | ---help--- | |
632 | Select this for eDP LCD panels with 4 lanes running at 1.62G, | |
633 | connected via an ANX9804 bridge chip. | |
97ece830 | 634 | |
27515b20 HG |
635 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
636 | bool "Hitachi tx18d42vm LCD panel" | |
637 | select VIDEO_LCD_HITACHI_TX18D42VM | |
638 | select VIDEO_LCD_IF_LVDS | |
639 | ---help--- | |
640 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
641 | ||
aad2ac24 HG |
642 | config VIDEO_LCD_TL059WV5C0 |
643 | bool "tl059wv5c0 LCD panel" | |
644 | select VIDEO_LCD_PANEL_I2C | |
645 | select VIDEO_LCD_IF_PARALLEL | |
646 | ---help--- | |
647 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
648 | Aigo M60/M608/M606 tablets. | |
649 | ||
213480e1 HG |
650 | endchoice |
651 | ||
652 | ||
c13f60d9 HG |
653 | config GMAC_TX_DELAY |
654 | int "GMAC Transmit Clock Delay Chain" | |
655 | default 0 | |
656 | ---help--- | |
657 | Set the GMAC Transmit Clock Delay Chain value. | |
658 | ||
ff42d107 | 659 | config SPL_STACK_R_ADDR |
d96ebc46 | 660 | default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I |
ff42d107 HG |
661 | default 0x2fe00000 if MACH_SUN9I |
662 | ||
dd84058d | 663 | endif |