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Commit | Line | Data |
---|---|---|
2c7e3b90 IC |
1 | if ARCH_SUNXI |
2 | ||
a4d88920 SDPP |
3 | config IDENT_STRING |
4 | default " Allwinner Technology" | |
5 | ||
0dcf18c6 | 6 | # FIXME: Should not redefine these Kconfig symbols |
8f925584 SG |
7 | config PRE_CONSOLE_BUFFER |
8 | default y | |
9 | ||
53b5bf3c SG |
10 | config SPL_GPIO_SUPPORT |
11 | default y | |
12 | ||
77d2f7f5 SG |
13 | config SPL_LIBCOMMON_SUPPORT |
14 | default y | |
15 | ||
1646eba8 SG |
16 | config SPL_LIBDISK_SUPPORT |
17 | default y | |
18 | ||
cc4288ef SG |
19 | config SPL_LIBGENERIC_SUPPORT |
20 | default y | |
21 | ||
1fdf7c64 | 22 | config SPL_MMC_SUPPORT |
0dcf18c6 | 23 | depends on SPL && GENERIC_MMC |
1fdf7c64 SG |
24 | default y |
25 | ||
2253797d SG |
26 | config SPL_POWER_SUPPORT |
27 | default y | |
28 | ||
e00f76ce SG |
29 | config SPL_SERIAL_SUPPORT |
30 | default y | |
31 | ||
bc613d85 AP |
32 | config SUNXI_HIGH_SRAM |
33 | bool | |
34 | default n | |
35 | ---help--- | |
36 | Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, | |
37 | with the first SRAM region being located at address 0. | |
38 | Some newer SoCs map the boot ROM at address 0 instead and move the | |
39 | SRAM to 64KB, just behind the mask ROM. | |
40 | Chips using the latter setup are supposed to select this option to | |
41 | adjust the addresses accordingly. | |
42 | ||
44d8ae5b HG |
43 | # Note only one of these may be selected at a time! But hidden choices are |
44 | # not supported by Kconfig | |
45 | config SUNXI_GEN_SUN4I | |
46 | bool | |
47 | ---help--- | |
48 | Select this for sunxi SoCs which have resets and clocks set up | |
49 | as the original A10 (mach-sun4i). | |
50 | ||
51 | config SUNXI_GEN_SUN6I | |
52 | bool | |
53 | ---help--- | |
54 | Select this for sunxi SoCs which have sun6i like periphery, like | |
55 | separate ahb reset control registers, custom pmic bus, new style | |
56 | watchdog, etc. | |
57 | ||
58 | ||
7b82a229 AP |
59 | config MACH_SUNXI_H3_H5 |
60 | bool | |
61 | select SUNXI_GEN_SUN6I | |
62 | select SUPPORT_SPL | |
63 | ||
2c7e3b90 IC |
64 | choice |
65 | prompt "Sunxi SoC Variant" | |
3da9536e | 66 | optional |
2c7e3b90 | 67 | |
c3be2793 | 68 | config MACH_SUN4I |
2c7e3b90 IC |
69 | bool "sun4i (Allwinner A10)" |
70 | select CPU_V7 | |
85db5831 | 71 | select ARM_CORTEX_CPU_IS_UP |
44d8ae5b | 72 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
73 | select SUPPORT_SPL |
74 | ||
c3be2793 | 75 | config MACH_SUN5I |
2c7e3b90 IC |
76 | bool "sun5i (Allwinner A13)" |
77 | select CPU_V7 | |
85db5831 | 78 | select ARM_CORTEX_CPU_IS_UP |
44d8ae5b | 79 | select SUNXI_GEN_SUN4I |
2c7e3b90 IC |
80 | select SUPPORT_SPL |
81 | ||
c3be2793 | 82 | config MACH_SUN6I |
2c7e3b90 IC |
83 | bool "sun6i (Allwinner A31)" |
84 | select CPU_V7 | |
cc08ea4c CYT |
85 | select CPU_V7_HAS_NONSEC |
86 | select CPU_V7_HAS_VIRT | |
217f92bb | 87 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 88 | select SUNXI_GEN_SUN6I |
8c2c9cfa | 89 | select SUPPORT_SPL |
cc08ea4c | 90 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 91 | |
c3be2793 | 92 | config MACH_SUN7I |
2c7e3b90 IC |
93 | bool "sun7i (Allwinner A20)" |
94 | select CPU_V7 | |
ea624e19 HG |
95 | select CPU_V7_HAS_NONSEC |
96 | select CPU_V7_HAS_VIRT | |
217f92bb | 97 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 98 | select SUNXI_GEN_SUN4I |
2c7e3b90 | 99 | select SUPPORT_SPL |
b366fb92 | 100 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 101 | |
5e6bacdb | 102 | config MACH_SUN8I_A23 |
2c7e3b90 IC |
103 | bool "sun8i (Allwinner A23)" |
104 | select CPU_V7 | |
014414f5 CYT |
105 | select CPU_V7_HAS_NONSEC |
106 | select CPU_V7_HAS_VIRT | |
217f92bb | 107 | select ARCH_SUPPORT_PSCI |
44d8ae5b | 108 | select SUNXI_GEN_SUN6I |
08fd1479 | 109 | select SUPPORT_SPL |
014414f5 | 110 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
2c7e3b90 | 111 | |
8c3dacff VP |
112 | config MACH_SUN8I_A33 |
113 | bool "sun8i (Allwinner A33)" | |
114 | select CPU_V7 | |
014414f5 CYT |
115 | select CPU_V7_HAS_NONSEC |
116 | select CPU_V7_HAS_VIRT | |
217f92bb | 117 | select ARCH_SUPPORT_PSCI |
8c3dacff VP |
118 | select SUNXI_GEN_SUN6I |
119 | select SUPPORT_SPL | |
014414f5 | 120 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
8c3dacff | 121 | |
a81b7995 CYT |
122 | config MACH_SUN8I_A83T |
123 | bool "sun8i (Allwinner A83T)" | |
124 | select CPU_V7 | |
125 | select SUNXI_GEN_SUN6I | |
126 | select SUPPORT_SPL | |
127 | ||
1c27b7dc JK |
128 | config MACH_SUN8I_H3 |
129 | bool "sun8i (Allwinner H3)" | |
130 | select CPU_V7 | |
853f6d1e CYT |
131 | select CPU_V7_HAS_NONSEC |
132 | select CPU_V7_HAS_VIRT | |
217f92bb | 133 | select ARCH_SUPPORT_PSCI |
7b82a229 | 134 | select MACH_SUNXI_H3_H5 |
853f6d1e | 135 | select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT |
1c27b7dc | 136 | |
1871a8ca HG |
137 | config MACH_SUN9I |
138 | bool "sun9i (Allwinner A80)" | |
139 | select CPU_V7 | |
bc613d85 | 140 | select SUNXI_HIGH_SRAM |
1871a8ca | 141 | select SUNXI_GEN_SUN6I |
a98c296a | 142 | select SUPPORT_SPL |
1871a8ca | 143 | |
a81b7995 CYT |
144 | config MACH_SUN50I |
145 | bool "sun50i (Allwinner A64)" | |
146 | select ARM64 | |
147 | select SUNXI_GEN_SUN6I | |
bc613d85 | 148 | select SUNXI_HIGH_SRAM |
eb77f5c9 | 149 | select SUPPORT_SPL |
a81b7995 | 150 | |
997bde60 AP |
151 | config MACH_SUN50I_H5 |
152 | bool "sun50i (Allwinner H5)" | |
153 | select ARM64 | |
154 | select MACH_SUNXI_H3_H5 | |
155 | select SUNXI_HIGH_SRAM | |
156 | ||
2c7e3b90 | 157 | endchoice |
8a6564da | 158 | |
5e6bacdb HG |
159 | # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" |
160 | config MACH_SUN8I | |
161 | bool | |
7b82a229 | 162 | default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUNXI_H3_H5 || MACH_SUN8I_A83T |
5e6bacdb | 163 | |
b5402d13 AP |
164 | config RESERVE_ALLWINNER_BOOT0_HEADER |
165 | bool "reserve space for Allwinner boot0 header" | |
166 | select ENABLE_ARM_SOC_BOOT0_HOOK | |
167 | ---help--- | |
168 | Prepend a 1536 byte (empty) header to the U-Boot image file, to be | |
169 | filled with magic values post build. The Allwinner provided boot0 | |
170 | blob relies on this information to load and execute U-Boot. | |
171 | Only needed on 64-bit Allwinner boards so far when using boot0. | |
172 | ||
83843c9b AP |
173 | config ARM_BOOT_HOOK_RMR |
174 | bool | |
175 | depends on ARM64 | |
176 | default y | |
177 | select ENABLE_ARM_SOC_BOOT0_HOOK | |
178 | ---help--- | |
179 | Insert some ARM32 code at the very beginning of the U-Boot binary | |
180 | which uses an RMR register write to bring the core into AArch64 mode. | |
181 | The very first instruction acts as a switch, since it's carefully | |
182 | chosen to be a NOP in one mode and a branch in the other, so the | |
183 | code would only be executed if not already in AArch64. | |
184 | This allows both the SPL and the U-Boot proper to be entered in | |
185 | either mode and switch to AArch64 if needed. | |
186 | ||
f5fd8caf VP |
187 | config DRAM_TYPE |
188 | int "sunxi dram type" | |
189 | depends on MACH_SUN8I_A83T | |
190 | default 3 | |
191 | ---help--- | |
192 | Set the dram type, 3: DDR3, 7: LPDDR3 | |
5e6bacdb | 193 | |
37781a1a | 194 | config DRAM_CLK |
8ffc487c | 195 | int "sunxi dram clock speed" |
297bb9e0 | 196 | default 792 if MACH_SUN9I |
8ffc487c HG |
197 | default 312 if MACH_SUN6I || MACH_SUN8I |
198 | default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
52e3182b | 199 | default 672 if MACH_SUN50I |
37781a1a | 200 | ---help--- |
297bb9e0 PT |
201 | Set the dram clock speed, valid range 240 - 480 (prior to sun9i), |
202 | must be a multiple of 24. For the sun9i (A80), the tested values | |
203 | (for DDR3-1600) are 312 to 792. | |
37781a1a | 204 | |
47e3501a SS |
205 | if MACH_SUN5I || MACH_SUN7I |
206 | config DRAM_MBUS_CLK | |
207 | int "sunxi mbus clock speed" | |
208 | default 300 | |
209 | ---help--- | |
210 | Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. | |
211 | ||
212 | endif | |
213 | ||
37781a1a | 214 | config DRAM_ZQ |
8ffc487c HG |
215 | int "sunxi dram zq value" |
216 | default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I | |
217 | default 127 if MACH_SUN7I | |
58b628ed | 218 | default 4145117 if MACH_SUN9I |
52e3182b | 219 | default 3881915 if MACH_SUN50I |
37781a1a | 220 | ---help--- |
e1a0888e | 221 | Set the dram zq value. |
8ffc487c | 222 | |
8975cdf4 HG |
223 | config DRAM_ODT_EN |
224 | bool "sunxi dram odt enable" | |
225 | default n if !MACH_SUN8I_A23 | |
226 | default y if MACH_SUN8I_A23 | |
eb77f5c9 | 227 | default y if MACH_SUN50I |
8975cdf4 HG |
228 | ---help--- |
229 | Select this to enable dram odt (on die termination). | |
230 | ||
8ffc487c HG |
231 | if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I |
232 | config DRAM_EMR1 | |
233 | int "sunxi dram emr1 value" | |
234 | default 0 if MACH_SUN4I | |
235 | default 4 if MACH_SUN5I || MACH_SUN7I | |
236 | ---help--- | |
e1a0888e | 237 | Set the dram controller emr1 value. |
d133647a | 238 | |
47e3501a SS |
239 | config DRAM_TPR3 |
240 | hex "sunxi dram tpr3 value" | |
241 | default 0 | |
242 | ---help--- | |
243 | Set the dram controller tpr3 parameter. This parameter configures | |
244 | the delay on the command lane and also phase shifts, which are | |
245 | applied for sampling incoming read data. The default value 0 | |
246 | means that no phase/delay adjustments are necessary. Properly | |
247 | configuring this parameter increases reliability at high DRAM | |
248 | clock speeds. | |
249 | ||
250 | config DRAM_DQS_GATING_DELAY | |
251 | hex "sunxi dram dqs_gating_delay value" | |
252 | default 0 | |
253 | ---help--- | |
254 | Set the dram controller dqs_gating_delay parmeter. Each byte | |
255 | encodes the DQS gating delay for each byte lane. The delay | |
256 | granularity is 1/4 cycle. For example, the value 0x05060606 | |
257 | means that the delay is 5 quarter-cycles for one lane (1.25 | |
258 | cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. | |
259 | The default value 0 means autodetection. The results of hardware | |
260 | autodetection are not very reliable and depend on the chip | |
261 | temperature (sometimes producing different results on cold start | |
262 | and warm reboot). But the accuracy of hardware autodetection | |
263 | is usually good enough, unless running at really high DRAM | |
264 | clocks speeds (up to 600MHz). If unsure, keep as 0. | |
265 | ||
d133647a SS |
266 | choice |
267 | prompt "sunxi dram timings" | |
268 | default DRAM_TIMINGS_VENDOR_MAGIC | |
269 | ---help--- | |
270 | Select the timings of the DDR3 chips. | |
271 | ||
272 | config DRAM_TIMINGS_VENDOR_MAGIC | |
273 | bool "Magic vendor timings from Android" | |
274 | ---help--- | |
275 | The same DRAM timings as in the Allwinner boot0 bootloader. | |
276 | ||
277 | config DRAM_TIMINGS_DDR3_1066F_1333H | |
278 | bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" | |
279 | ---help--- | |
280 | Use the timings of the standard JEDEC DDR3-1066F speed bin for | |
281 | DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin | |
282 | for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips | |
283 | used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 | |
284 | or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm | |
285 | that down binning to DDR3-1066F is supported (because DDR3-1066F | |
286 | uses a bit faster timings than DDR3-1333H). | |
287 | ||
288 | config DRAM_TIMINGS_DDR3_800E_1066G_1333J | |
289 | bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" | |
290 | ---help--- | |
291 | Use the timings of the slowest possible JEDEC speed bin for the | |
292 | selected DRAM_CLK. Depending on the DRAM_CLK value, it may be | |
293 | DDR3-800E, DDR3-1066G or DDR3-1333J. | |
294 | ||
295 | endchoice | |
296 | ||
37781a1a HG |
297 | endif |
298 | ||
8975cdf4 HG |
299 | if MACH_SUN8I_A23 |
300 | config DRAM_ODT_CORRECTION | |
301 | int "sunxi dram odt correction value" | |
302 | default 0 | |
303 | ---help--- | |
304 | Set the dram odt correction value (range -255 - 255). In allwinner | |
305 | fex files, this option is found in bits 8-15 of the u32 odt_en variable | |
306 | in the [dram] section. When bit 31 of the odt_en variable is set | |
307 | then the correction is negative. Usually the value for this is 0. | |
308 | endif | |
309 | ||
e71b422b | 310 | config SYS_CLK_FREQ |
d96ebc46 | 311 | default 816000000 if MACH_SUN50I |
e71b422b | 312 | default 912000000 if MACH_SUN7I |
c53344ad | 313 | default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I || MACH_SUN9I |
e71b422b | 314 | |
8a6564da | 315 | config SYS_CONFIG_NAME |
c3be2793 IC |
316 | default "sun4i" if MACH_SUN4I |
317 | default "sun5i" if MACH_SUN5I | |
318 | default "sun6i" if MACH_SUN6I | |
319 | default "sun7i" if MACH_SUN7I | |
320 | default "sun8i" if MACH_SUN8I | |
1871a8ca | 321 | default "sun9i" if MACH_SUN9I |
d96ebc46 | 322 | default "sun50i" if MACH_SUN50I |
dd84058d | 323 | |
dd84058d | 324 | config SYS_BOARD |
dd84058d MY |
325 | default "sunxi" |
326 | ||
327 | config SYS_SOC | |
dd84058d MY |
328 | default "sunxi" |
329 | ||
f0ce28e9 SS |
330 | config UART0_PORT_F |
331 | bool "UART0 on MicroSD breakout board" | |
f0ce28e9 SS |
332 | default n |
333 | ---help--- | |
334 | Repurpose the SD card slot for getting access to the UART0 serial | |
335 | console. Primarily useful only for low level u-boot debugging on | |
336 | tablets, where normal UART0 is difficult to access and requires | |
337 | device disassembly and/or soldering. As the SD card can't be used | |
338 | at the same time, the system can be only booted in the FEL mode. | |
339 | Only enable this if you really know what you are doing. | |
340 | ||
accc9e44 | 341 | config OLD_SUNXI_KERNEL_COMPAT |
ab65006b | 342 | bool "Enable workarounds for booting old kernels" |
accc9e44 HG |
343 | default n |
344 | ---help--- | |
345 | Set this to enable various workarounds for old kernels, this results in | |
346 | sub-optimal settings for newer kernels, only enable if needed. | |
347 | ||
f5fd7886 MJ |
348 | config MACPWR |
349 | string "MAC power pin" | |
350 | default "" | |
351 | help | |
352 | Set the pin used to power the MAC. This takes a string in the format | |
353 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
354 | ||
cd82113a HG |
355 | config MMC0_CD_PIN |
356 | string "Card detect pin for mmc0" | |
7b82a229 | 357 | default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I |
cd82113a HG |
358 | default "" |
359 | ---help--- | |
360 | Set the card detect pin for mmc0, leave empty to not use cd. This | |
361 | takes a string in the format understood by sunxi_name_to_gpio, e.g. | |
362 | PH1 for pin 1 of port H. | |
363 | ||
364 | config MMC1_CD_PIN | |
365 | string "Card detect pin for mmc1" | |
366 | default "" | |
367 | ---help--- | |
368 | See MMC0_CD_PIN help text. | |
369 | ||
370 | config MMC2_CD_PIN | |
371 | string "Card detect pin for mmc2" | |
372 | default "" | |
373 | ---help--- | |
374 | See MMC0_CD_PIN help text. | |
375 | ||
376 | config MMC3_CD_PIN | |
377 | string "Card detect pin for mmc3" | |
378 | default "" | |
379 | ---help--- | |
380 | See MMC0_CD_PIN help text. | |
381 | ||
8deacca9 PK |
382 | config MMC1_PINS |
383 | string "Pins for mmc1" | |
384 | default "" | |
385 | ---help--- | |
386 | Set the pins used for mmc1, when applicable. This takes a string in the | |
387 | format understood by sunxi_name_to_gpio_bank, e.g. PH for port H. | |
388 | ||
389 | config MMC2_PINS | |
390 | string "Pins for mmc2" | |
391 | default "" | |
392 | ---help--- | |
393 | See MMC1_PINS help text. | |
394 | ||
395 | config MMC3_PINS | |
396 | string "Pins for mmc3" | |
397 | default "" | |
398 | ---help--- | |
399 | See MMC1_PINS help text. | |
400 | ||
2ccfac01 HG |
401 | config MMC_SUNXI_SLOT_EXTRA |
402 | int "mmc extra slot number" | |
403 | default -1 | |
404 | ---help--- | |
405 | sunxi builds always enable mmc0, some boards also have a second sdcard | |
406 | slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable | |
407 | support for this. | |
408 | ||
2c3c3ecb HG |
409 | config INITIAL_USB_SCAN_DELAY |
410 | int "delay initial usb scan by x ms to allow builtin devices to init" | |
411 | default 0 | |
412 | ---help--- | |
413 | Some boards have on board usb devices which need longer than the | |
414 | USB spec's 1 second to connect from board powerup. Set this config | |
415 | option to a non 0 value to add an extra delay before the first usb | |
416 | bus scan. | |
417 | ||
4458b7a6 HG |
418 | config USB0_VBUS_PIN |
419 | string "Vbus enable pin for usb0 (otg)" | |
420 | default "" | |
421 | ---help--- | |
422 | Set the Vbus enable pin for usb0 (otg). This takes a string in the | |
423 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
424 | ||
52defe8f HG |
425 | config USB0_VBUS_DET |
426 | string "Vbus detect pin for usb0 (otg)" | |
52defe8f HG |
427 | default "" |
428 | ---help--- | |
429 | Set the Vbus detect pin for usb0 (otg). This takes a string in the | |
430 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
431 | ||
48c06c98 HG |
432 | config USB0_ID_DET |
433 | string "ID detect pin for usb0 (otg)" | |
434 | default "" | |
435 | ---help--- | |
436 | Set the ID detect pin for usb0 (otg). This takes a string in the | |
437 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
438 | ||
115200ce HG |
439 | config USB1_VBUS_PIN |
440 | string "Vbus enable pin for usb1 (ehci0)" | |
441 | default "PH6" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 442 | default "PH27" if MACH_SUN6I |
115200ce HG |
443 | ---help--- |
444 | Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes | |
445 | a string in the format understood by sunxi_name_to_gpio, e.g. | |
446 | PH1 for pin 1 of port H. | |
447 | ||
448 | config USB2_VBUS_PIN | |
449 | string "Vbus enable pin for usb2 (ehci1)" | |
450 | default "PH3" if MACH_SUN4I || MACH_SUN7I | |
76946dfe | 451 | default "PH24" if MACH_SUN6I |
115200ce HG |
452 | ---help--- |
453 | See USB1_VBUS_PIN help text. | |
454 | ||
60fa6301 HG |
455 | config USB3_VBUS_PIN |
456 | string "Vbus enable pin for usb3 (ehci2)" | |
457 | default "" | |
458 | ---help--- | |
459 | See USB1_VBUS_PIN help text. | |
460 | ||
6c739c5d PK |
461 | config I2C0_ENABLE |
462 | bool "Enable I2C/TWI controller 0" | |
463 | default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I | |
464 | default n if MACH_SUN6I || MACH_SUN8I | |
0878a8a7 | 465 | select CMD_I2C |
6c739c5d PK |
466 | ---help--- |
467 | This allows enabling I2C/TWI controller 0 by muxing its pins, enabling | |
468 | its clock and setting up the bus. This is especially useful on devices | |
469 | with slaves connected to the bus or with pins exposed through e.g. an | |
470 | expansion port/header. | |
471 | ||
472 | config I2C1_ENABLE | |
473 | bool "Enable I2C/TWI controller 1" | |
474 | default n | |
0878a8a7 | 475 | select CMD_I2C |
6c739c5d PK |
476 | ---help--- |
477 | See I2C0_ENABLE help text. | |
478 | ||
479 | config I2C2_ENABLE | |
480 | bool "Enable I2C/TWI controller 2" | |
481 | default n | |
0878a8a7 | 482 | select CMD_I2C |
6c739c5d PK |
483 | ---help--- |
484 | See I2C0_ENABLE help text. | |
485 | ||
486 | if MACH_SUN6I || MACH_SUN7I | |
487 | config I2C3_ENABLE | |
488 | bool "Enable I2C/TWI controller 3" | |
489 | default n | |
0878a8a7 | 490 | select CMD_I2C |
6c739c5d PK |
491 | ---help--- |
492 | See I2C0_ENABLE help text. | |
493 | endif | |
494 | ||
0d8382ae | 495 | if SUNXI_GEN_SUN6I |
9d082687 JW |
496 | config R_I2C_ENABLE |
497 | bool "Enable the PRCM I2C/TWI controller" | |
0d8382ae JW |
498 | # This is used for the pmic on H3 |
499 | default y if SY8106A_POWER | |
0878a8a7 | 500 | select CMD_I2C |
9d082687 JW |
501 | ---help--- |
502 | Set this to y to enable the I2C controller which is part of the PRCM. | |
0d8382ae | 503 | endif |
9d082687 | 504 | |
6c739c5d PK |
505 | if MACH_SUN7I |
506 | config I2C4_ENABLE | |
507 | bool "Enable I2C/TWI controller 4" | |
508 | default n | |
0878a8a7 | 509 | select CMD_I2C |
6c739c5d PK |
510 | ---help--- |
511 | See I2C0_ENABLE help text. | |
512 | endif | |
513 | ||
2fcf033d | 514 | config AXP_GPIO |
ab65006b | 515 | bool "Enable support for gpio-s on axp PMICs" |
2fcf033d HG |
516 | default n |
517 | ---help--- | |
518 | Say Y here to enable support for the gpio pins of the axp PMIC ICs. | |
519 | ||
7f2c521f | 520 | config VIDEO |
ab65006b | 521 | bool "Enable graphical uboot console on HDMI, LCD or VGA" |
7b82a229 | 522 | depends on !MACH_SUN8I_A83T && !MACH_SUNXI_H3_H5 && !MACH_SUN9I && !MACH_SUN50I |
7f2c521f LV |
523 | default y |
524 | ---help--- | |
2dae800f HG |
525 | Say Y here to add support for using a cfb console on the HDMI, LCD |
526 | or VGA output found on most sunxi devices. See doc/README.video for | |
527 | info on how to select the video output and mode. | |
528 | ||
2fbf091a | 529 | config VIDEO_HDMI |
ab65006b | 530 | bool "HDMI output support" |
2fbf091a HG |
531 | depends on VIDEO && !MACH_SUN8I |
532 | default y | |
533 | ---help--- | |
534 | Say Y here to add support for outputting video over HDMI. | |
535 | ||
d9786d23 | 536 | config VIDEO_VGA |
ab65006b | 537 | bool "VGA output support" |
d9786d23 HG |
538 | depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) |
539 | default n | |
540 | ---help--- | |
541 | Say Y here to add support for outputting video over VGA. | |
542 | ||
e2bbdfb1 | 543 | config VIDEO_VGA_VIA_LCD |
ab65006b | 544 | bool "VGA via LCD controller support" |
2583d5b1 | 545 | depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) |
e2bbdfb1 HG |
546 | default n |
547 | ---help--- | |
548 | Say Y here to add support for external DACs connected to the parallel | |
549 | LCD interface driving a VGA connector, such as found on the | |
550 | Olimex A13 boards. | |
551 | ||
fb75d972 | 552 | config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH |
ab65006b | 553 | bool "Force sync active high for VGA via LCD controller support" |
fb75d972 HG |
554 | depends on VIDEO_VGA_VIA_LCD |
555 | default n | |
556 | ---help--- | |
557 | Say Y here if you've a board which uses opendrain drivers for the vga | |
558 | hsync and vsync signals. Opendrain drivers cannot generate steep enough | |
559 | positive edges for a stable video output, so on boards with opendrain | |
560 | drivers the sync signals must always be active high. | |
561 | ||
507e27df CYT |
562 | config VIDEO_VGA_EXTERNAL_DAC_EN |
563 | string "LCD panel power enable pin" | |
564 | depends on VIDEO_VGA_VIA_LCD | |
565 | default "" | |
566 | ---help--- | |
567 | Set the enable pin for the external VGA DAC. This takes a string in the | |
568 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
569 | ||
39920c81 | 570 | config VIDEO_COMPOSITE |
ab65006b | 571 | bool "Composite video output support" |
39920c81 HG |
572 | depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) |
573 | default n | |
574 | ---help--- | |
575 | Say Y here to add support for outputting composite video. | |
576 | ||
2dae800f HG |
577 | config VIDEO_LCD_MODE |
578 | string "LCD panel timing details" | |
579 | depends on VIDEO | |
580 | default "" | |
581 | ---help--- | |
582 | LCD panel timing details string, leave empty if there is no LCD panel. | |
583 | This is in drivers/video/videomodes.c: video_get_params() format, e.g. | |
584 | x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 | |
8addd3ed | 585 | Also see: http://linux-sunxi.org/LCD |
2dae800f | 586 | |
6515032e HG |
587 | config VIDEO_LCD_DCLK_PHASE |
588 | int "LCD panel display clock phase" | |
589 | depends on VIDEO | |
590 | default 1 | |
591 | ---help--- | |
592 | Select LCD panel display clock phase shift, range 0-3. | |
593 | ||
2dae800f HG |
594 | config VIDEO_LCD_POWER |
595 | string "LCD panel power enable pin" | |
596 | depends on VIDEO | |
597 | default "" | |
598 | ---help--- | |
599 | Set the power enable pin for the LCD panel. This takes a string in the | |
600 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
601 | ||
242e3d89 HG |
602 | config VIDEO_LCD_RESET |
603 | string "LCD panel reset pin" | |
604 | depends on VIDEO | |
605 | default "" | |
606 | ---help--- | |
607 | Set the reset pin for the LCD panel. This takes a string in the format | |
608 | understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
609 | ||
2dae800f HG |
610 | config VIDEO_LCD_BL_EN |
611 | string "LCD panel backlight enable pin" | |
612 | depends on VIDEO | |
613 | default "" | |
614 | ---help--- | |
615 | Set the backlight enable pin for the LCD panel. This takes a string in the | |
616 | the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
617 | port H. | |
618 | ||
619 | config VIDEO_LCD_BL_PWM | |
620 | string "LCD panel backlight pwm pin" | |
621 | depends on VIDEO | |
622 | default "" | |
623 | ---help--- | |
624 | Set the backlight pwm pin for the LCD panel. This takes a string in the | |
625 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
7f2c521f | 626 | |
a7403ae8 HG |
627 | config VIDEO_LCD_BL_PWM_ACTIVE_LOW |
628 | bool "LCD panel backlight pwm is inverted" | |
629 | depends on VIDEO | |
630 | default y | |
631 | ---help--- | |
632 | Set this if the backlight pwm output is active low. | |
633 | ||
55410089 HG |
634 | config VIDEO_LCD_PANEL_I2C |
635 | bool "LCD panel needs to be configured via i2c" | |
636 | depends on VIDEO | |
1fc42018 | 637 | default n |
0878a8a7 | 638 | select CMD_I2C |
55410089 HG |
639 | ---help--- |
640 | Say y here if the LCD panel needs to be configured via i2c. This | |
641 | will add a bitbang i2c controller using gpios to talk to the LCD. | |
642 | ||
643 | config VIDEO_LCD_PANEL_I2C_SDA | |
644 | string "LCD panel i2c interface SDA pin" | |
645 | depends on VIDEO_LCD_PANEL_I2C | |
646 | default "PG12" | |
647 | ---help--- | |
648 | Set the SDA pin for the LCD i2c interface. This takes a string in the | |
649 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
650 | ||
651 | config VIDEO_LCD_PANEL_I2C_SCL | |
652 | string "LCD panel i2c interface SCL pin" | |
653 | depends on VIDEO_LCD_PANEL_I2C | |
654 | default "PG10" | |
655 | ---help--- | |
656 | Set the SCL pin for the LCD i2c interface. This takes a string in the | |
657 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. | |
658 | ||
213480e1 HG |
659 | |
660 | # Note only one of these may be selected at a time! But hidden choices are | |
661 | # not supported by Kconfig | |
662 | config VIDEO_LCD_IF_PARALLEL | |
663 | bool | |
664 | ||
665 | config VIDEO_LCD_IF_LVDS | |
666 | bool | |
667 | ||
668 | ||
669 | choice | |
670 | prompt "LCD panel support" | |
671 | depends on VIDEO | |
672 | ---help--- | |
673 | Select which type of LCD panel to support. | |
674 | ||
675 | config VIDEO_LCD_PANEL_PARALLEL | |
676 | bool "Generic parallel interface LCD panel" | |
677 | select VIDEO_LCD_IF_PARALLEL | |
678 | ||
679 | config VIDEO_LCD_PANEL_LVDS | |
680 | bool "Generic lvds interface LCD panel" | |
681 | select VIDEO_LCD_IF_LVDS | |
682 | ||
97ece830 SS |
683 | config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 |
684 | bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" | |
685 | select VIDEO_LCD_SSD2828 | |
686 | select VIDEO_LCD_IF_PARALLEL | |
687 | ---help--- | |
c1cfd519 HG |
688 | 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 |
689 | ||
690 | config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 | |
691 | bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" | |
692 | select VIDEO_LCD_ANX9804 | |
693 | select VIDEO_LCD_IF_PARALLEL | |
694 | select VIDEO_LCD_PANEL_I2C | |
695 | ---help--- | |
696 | Select this for eDP LCD panels with 4 lanes running at 1.62G, | |
697 | connected via an ANX9804 bridge chip. | |
97ece830 | 698 | |
27515b20 HG |
699 | config VIDEO_LCD_PANEL_HITACHI_TX18D42VM |
700 | bool "Hitachi tx18d42vm LCD panel" | |
701 | select VIDEO_LCD_HITACHI_TX18D42VM | |
702 | select VIDEO_LCD_IF_LVDS | |
703 | ---help--- | |
704 | 7.85" 1024x768 Hitachi tx18d42vm LCD panel support | |
705 | ||
aad2ac24 HG |
706 | config VIDEO_LCD_TL059WV5C0 |
707 | bool "tl059wv5c0 LCD panel" | |
708 | select VIDEO_LCD_PANEL_I2C | |
709 | select VIDEO_LCD_IF_PARALLEL | |
710 | ---help--- | |
711 | 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and | |
712 | Aigo M60/M608/M606 tablets. | |
713 | ||
213480e1 HG |
714 | endchoice |
715 | ||
d7b560e6 MJ |
716 | config SATAPWR |
717 | string "SATA power pin" | |
718 | default "" | |
719 | help | |
720 | Set the pins used to power the SATA. This takes a string in the | |
721 | format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of | |
722 | port H. | |
213480e1 | 723 | |
c13f60d9 HG |
724 | config GMAC_TX_DELAY |
725 | int "GMAC Transmit Clock Delay Chain" | |
726 | default 0 | |
727 | ---help--- | |
728 | Set the GMAC Transmit Clock Delay Chain value. | |
729 | ||
ff42d107 | 730 | config SPL_STACK_R_ADDR |
d96ebc46 | 731 | default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I |
ff42d107 HG |
732 | default 0x2fe00000 if MACH_SUN9I |
733 | ||
dd84058d | 734 | endif |