[people/ms/u-boot.git] / board / ti / am335x / board.c

/*
 * board.c
 *
 * Board functions for TI AM335X based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
#ifdef CONFIG_SPL_BUILD
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
#endif

/* MII mode defines */
#define MII_MODE_ENABLE		0x0
#define RGMII_MODE_ENABLE	0x3A

/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN		7

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

static struct am335x_baseboard_id __attribute__((section (".data"))) header;

static inline int board_is_bone(void)
{
	return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
}

static inline int board_is_bone_lt(void)
{
	return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
}

static inline int board_is_evm_sk(void)
{
	return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
}

static inline int board_is_idk(void)
{
	return !strncmp(header.config, "SKU#02", 6);
}

static int __maybe_unused board_is_gp_evm(void)
{
	return !strncmp("A33515BB", header.name, 8);
}

int board_is_evm_15_or_later(void)
{
	return (!strncmp("A33515BB", header.name, 8) &&
		strncmp("1.5", header.version, 3) <= 0);
}

/*
 * Read header information from EEPROM into global structure.
 */
static int read_eeprom(void)
{
	/* Check if baseboard eeprom is available */
	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
		puts("Could not probe the EEPROM; something fundamentally "
			"wrong on the I2C bus.\n");
		return -ENODEV;
	}

	/* read the eeprom using i2c */
	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
							sizeof(header))) {
		puts("Could not read the EEPROM; something fundamentally"
			" wrong on the I2C bus.\n");
		return -EIO;
	}

	if (header.magic != 0xEE3355AA) {
		/*
		 * read the eeprom using i2c again,
		 * but use only a 1 byte address
		 */
		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
					(uchar *)&header, sizeof(header))) {
			puts("Could not read the EEPROM; something "
				"fundamentally wrong on the I2C bus.\n");
			return -EIO;
		}

		if (header.magic != 0xEE3355AA) {
			printf("Incorrect magic number (0x%x) in EEPROM\n",
					header.magic);
			return -EINVAL;
		}
	}

	return 0;
}

/* UART Defines */
#ifdef CONFIG_SPL_BUILD
#define UART_RESET		(0x1 << 1)
#define UART_CLK_RUNNING_MASK	0x1
#define UART_SMART_IDLE_EN	(0x1 << 0x3)

static void rtc32k_enable(void)
{
	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;

	/*
	 * Unlock the RTC's registers.  For more details please see the
	 * RTC_SS section of the TRM.  In order to unlock we need to
	 * write these specific values (keys) in this order.
	 */
	writel(0x83e70b13, &rtc->kick0r);
	writel(0x95a4f1e0, &rtc->kick1r);

	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
	writel((1 << 3) | (1 << 6), &rtc->osc);
}

static const struct ddr_data ddr2_data = {
	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
			  (MT47H128M16RT25E_RD_DQS<<20) |
			  (MT47H128M16RT25E_RD_DQS<<10) |
			  (MT47H128M16RT25E_RD_DQS<<0)),
	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
			  (MT47H128M16RT25E_WR_DQS<<20) |
			  (MT47H128M16RT25E_WR_DQS<<10) |
			  (MT47H128M16RT25E_WR_DQS<<0)),
	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
			 (MT47H128M16RT25E_PHY_WRLVL<<20) |
			 (MT47H128M16RT25E_PHY_WRLVL<<10) |
			 (MT47H128M16RT25E_PHY_WRLVL<<0)),
	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
			 (MT47H128M16RT25E_PHY_GATELVL<<20) |
			 (MT47H128M16RT25E_PHY_GATELVL<<10) |
			 (MT47H128M16RT25E_PHY_GATELVL<<0)),
	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
			  (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct cmd_control ddr2_cmd_ctrl_data = {
	.cmd0csratio = MT47H128M16RT25E_RATIO,
	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,

	.cmd1csratio = MT47H128M16RT25E_RATIO,
	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,

	.cmd2csratio = MT47H128M16RT25E_RATIO,
	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};

static const struct emif_regs ddr2_emif_reg_data = {
	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};

static const struct ddr_data ddr3_data = {
	.datardsratio0 = MT41J128MJT125_RD_DQS,
	.datawdsratio0 = MT41J128MJT125_WR_DQS,
	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct ddr_data ddr3_evm_data = {
	.datardsratio0 = MT41J512M8RH125_RD_DQS,
	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
	.datadldiff0 = PHY_DLL_LOCK_DIFF,
};

static const struct cmd_control ddr3_cmd_ctrl_data = {
	.cmd0csratio = MT41J128MJT125_RATIO,
	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,

	.cmd1csratio = MT41J128MJT125_RATIO,
	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,

	.cmd2csratio = MT41J128MJT125_RATIO,
	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};

static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
	.cmd0csratio = MT41J512M8RH125_RATIO,
	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,

	.cmd1csratio = MT41J512M8RH125_RATIO,
	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,

	.cmd2csratio = MT41J512M8RH125_RATIO,
	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};

static struct emif_regs ddr3_emif_reg_data = {
	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
	.zq_config = MT41J128MJT125_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};

static struct emif_regs ddr3_evm_emif_reg_data = {
	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
	.zq_config = MT41J512M8RH125_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
				PHY_EN_DYN_PWRDN,
};
#endif

/*
 * early system init of muxing and clocks.
 */
void s_init(void)
{
	/* WDT1 is already running when the bootloader gets control
	 * Disable it to avoid "random" resets
	 */
	writel(0xAAAA, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;
	writel(0x5555, &wdtimer->wdtwspr);
	while (readl(&wdtimer->wdtwwps) != 0x0)
		;

#ifdef CONFIG_SPL_BUILD
	/* Setup the PLLs and the clocks for the peripherals */
	pll_init();

	/* Enable RTC32K clock */
	rtc32k_enable();

	/* UART softreset */
	u32 regVal;

#ifdef CONFIG_SERIAL1
	enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
	enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
	enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
	enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
	enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
	enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */

	regVal = readl(&uart_base->uartsyscfg);
	regVal |= UART_RESET;
	writel(regVal, &uart_base->uartsyscfg);
	while ((readl(&uart_base->uartsyssts) &
		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
		;

	/* Disable smart idle */
	regVal = readl(&uart_base->uartsyscfg);
	regVal |= UART_SMART_IDLE_EN;
	writel(regVal, &uart_base->uartsyscfg);

	gd = &gdata;

	preloader_console_init();

	/* Initalize the board header */
	enable_i2c0_pin_mux();
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	if (read_eeprom() < 0)
		puts("Could not get board ID.\n");

	enable_board_pin_mux(&header);
	if (board_is_evm_sk()) {
		/*
		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
		 * This is safe enough to do on older revs.
		 */
		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	}

	if (board_is_evm_sk() || board_is_bone_lt())
		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
	else if (board_is_evm_15_or_later())
		config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
	else
		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
#endif
}

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	if (read_eeprom() < 0)
		puts("Could not get board ID.\n");

	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;

	gpmc_init();

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	char safe_string[HDR_NAME_LEN + 1];

	/* Now set variables based on the header. */
	strncpy(safe_string, (char *)header.name, sizeof(header.name));
	safe_string[sizeof(header.name)] = 0;
	setenv("board_name", safe_string);

	strncpy(safe_string, (char *)header.version, sizeof(header.version));
	safe_string[sizeof(header.version)] = 0;
	setenv("board_rev", safe_string);
#endif

	return 0;
}
#endif

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
	/* VTP can be added here */

	return;
}

static struct cpsw_slave_data cpsw_slaves[] = {
	{
		.slave_reg_ofs	= 0x208,
		.sliver_reg_ofs	= 0xd80,
		.phy_id		= 0,
	},
	{
		.slave_reg_ofs	= 0x308,
		.sliver_reg_ofs	= 0xdc0,
		.phy_id		= 1,
	},
};

static struct cpsw_platform_data cpsw_data = {
	.mdio_base		= CPSW_MDIO_BASE,
	.cpsw_base		= CPSW_BASE,
	.mdio_div		= 0xff,
	.channels		= 8,
	.cpdma_reg_ofs		= 0x800,
	.slaves			= 1,
	.slave_data		= cpsw_slaves,
	.ale_reg_ofs		= 0xd00,
	.ale_entries		= 1024,
	.host_port_reg_ofs	= 0x108,
	.hw_stats_reg_ofs	= 0x900,
	.mac_control		= (1 << 5),
	.control		= cpsw_control,
	.host_port_num		= 0,
	.version		= CPSW_CTRL_VERSION_2,
};
#endif

#if defined(CONFIG_DRIVER_TI_CPSW) || \
	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
	int rv, n = 0;
	uint8_t mac_addr[6];
	uint32_t mac_hi, mac_lo;

	/* try reading mac address from efuse */
	mac_lo = readl(&cdev->macid0l);
	mac_hi = readl(&cdev->macid0h);
	mac_addr[0] = mac_hi & 0xFF;
	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	mac_addr[4] = mac_lo & 0xFF;
	mac_addr[5] = (mac_lo & 0xFF00) >> 8;

#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	if (!getenv("ethaddr")) {
		printf("<ethaddr> not set. Validating first E-fuse MAC\n");

		if (is_valid_ether_addr(mac_addr))
			eth_setenv_enetaddr("ethaddr", mac_addr);
	}

	if (board_is_bone() || board_is_bone_lt() || board_is_idk()) {
		writel(MII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
				PHY_INTERFACE_MODE_MII;
	} else {
		writel(RGMII_MODE_ENABLE, &cdev->miisel);
		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
				PHY_INTERFACE_MODE_RGMII;
	}

	rv = cpsw_register(&cpsw_data);
	if (rv < 0)
		printf("Error %d registering CPSW switch\n", rv);
	else
		n += rv;

	/*
	 *
	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
	 * operating points.  So we must set the TX clock delay feature
	 * in the AR8051 PHY.  Since we only support a single ethernet
	 * device in U-Boot, we only do this for the first instance.
	 */
#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
#define AR8051_PHY_DEBUG_DATA_REG	0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
#define AR8051_RGMII_TX_CLK_DLY		0x100

	if (board_is_evm_sk() || board_is_gp_evm()) {
		const char *devname;
		devname = miiphy_get_current_dev();

		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
				AR8051_DEBUG_RGMII_CLK_DLY_REG);
		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
				AR8051_RGMII_TX_CLK_DLY);
	}
#endif
#if defined(CONFIG_USB_ETHER) && \
	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
	if (is_valid_ether_addr(mac_addr))
		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);

	rv = usb_eth_initialize(bis);
	if (rv < 0)
		printf("Error %d registering USB_ETHER\n", rv);
	else
		n += rv;
#endif
	return n;
}
#endif
Commit	Line	Data
e363426e PK	1	/*
	2	* board.c
	3	*
	4	* Board functions for TI AM335X based boards
	5	*
	6	* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <common.h>
	20	#include <errno.h>
	21	#include <spl.h>
	22	#include <asm/arch/cpu.h>
	23	#include <asm/arch/hardware.h>
	24	#include <asm/arch/omap.h>
	25	#include <asm/arch/ddr_defs.h>
	26	#include <asm/arch/clock.h>
	27	#include <asm/arch/gpio.h>
	28	#include <asm/arch/mmc_host_def.h>
	29	#include <asm/arch/sys_proto.h>
	30	#include <asm/io.h>
	31	#include <asm/emif.h>
	32	#include <asm/gpio.h>
	33	#include <i2c.h>
	34	#include <miiphy.h>
	35	#include <cpsw.h>
	36	#include "board.h"
	37
	38	DECLARE_GLOBAL_DATA_PTR;
	39
	40	static struct wd_timer wdtimer = (struct wd_timer )WDT_BASE;
	41	#ifdef CONFIG_SPL_BUILD
	42	static struct uart_sys uart_base = (struct uart_sys )DEFAULT_UART_BASE;
	43	#endif
	44
	45	/* MII mode defines */
	46	#define MII_MODE_ENABLE 0x0
cfd4ff6f	47	#define RGMII_MODE_ENABLE 0x3A
e363426e PK	48
	49	/* GPIO that controls power to DDR on EVM-SK */
	50	#define GPIO_DDR_VTT_EN 7
	51
	52	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	53
	54	static struct am335x_baseboard_id __attribute__((section (".data"))) header;
	55
	56	static inline int board_is_bone(void)
	57	{
	58	return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
	59	}
	60
	61	static inline int board_is_bone_lt(void)
	62	{
	63	return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
	64	}
	65
	66	static inline int board_is_evm_sk(void)
	67	{
	68	return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
	69	}
	70
a956bdcb MF	71	static inline int board_is_idk(void)
	72	{
	73	return !strncmp(header.config, "SKU#02", 6);
	74	}
	75
98bc1228	76	static int __maybe_unused board_is_gp_evm(void)
1634e969 TR	77	{
	78	return !strncmp("A33515BB", header.name, 8);
	79	}
	80
13526f71 JL	81	int board_is_evm_15_or_later(void)
	82	{
	83	return (!strncmp("A33515BB", header.name, 8) &&
	84	strncmp("1.5", header.version, 3) <= 0);
	85	}
	86
e363426e PK	87	/*
	88	* Read header information from EEPROM into global structure.
	89	*/
	90	static int read_eeprom(void)
	91	{
	92	/* Check if baseboard eeprom is available */
	93	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
	94	puts("Could not probe the EEPROM; something fundamentally "
	95	"wrong on the I2C bus.\n");
	96	return -ENODEV;
	97	}
	98
	99	/* read the eeprom using i2c */
	100	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
	101	sizeof(header))) {
	102	puts("Could not read the EEPROM; something fundamentally"
	103	" wrong on the I2C bus.\n");
	104	return -EIO;
	105	}
	106
	107	if (header.magic != 0xEE3355AA) {
	108	/*
	109	* read the eeprom using i2c again,
	110	* but use only a 1 byte address
	111	*/
	112	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
	113	(uchar *)&header, sizeof(header))) {
	114	puts("Could not read the EEPROM; something "
	115	"fundamentally wrong on the I2C bus.\n");
	116	return -EIO;
	117	}
	118
	119	if (header.magic != 0xEE3355AA) {
	120	printf("Incorrect magic number (0x%x) in EEPROM\n",
	121	header.magic);
	122	return -EINVAL;
	123	}
	124	}
	125
	126	return 0;
	127	}
	128
	129	/* UART Defines */
	130	#ifdef CONFIG_SPL_BUILD
	131	#define UART_RESET (0x1 << 1)
	132	#define UART_CLK_RUNNING_MASK 0x1
	133	#define UART_SMART_IDLE_EN (0x1 << 0x3)
	134
	135	static void rtc32k_enable(void)
	136	{
81df2bab	137	struct rtc_regs rtc = (struct rtc_regs )RTC_BASE;
e363426e PK	138
	139	/*
	140	* Unlock the RTC's registers. For more details please see the
	141	* RTC_SS section of the TRM. In order to unlock we need to
	142	* write these specific values (keys) in this order.
	143	*/
	144	writel(0x83e70b13, &rtc->kick0r);
	145	writel(0x95a4f1e0, &rtc->kick1r);
	146
	147	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
	148	writel((1 << 3) \| (1 << 6), &rtc->osc);
	149	}
e363426e	150
c00f69db	151	static const struct ddr_data ddr2_data = {
c7d35bef PK	152	.datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) \|
	153	(MT47H128M16RT25E_RD_DQS<<20) \|
	154	(MT47H128M16RT25E_RD_DQS<<10) \|
	155	(MT47H128M16RT25E_RD_DQS<<0)),
	156	.datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) \|
	157	(MT47H128M16RT25E_WR_DQS<<20) \|
	158	(MT47H128M16RT25E_WR_DQS<<10) \|
	159	(MT47H128M16RT25E_WR_DQS<<0)),
	160	.datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) \|
	161	(MT47H128M16RT25E_PHY_WRLVL<<20) \|
	162	(MT47H128M16RT25E_PHY_WRLVL<<10) \|
	163	(MT47H128M16RT25E_PHY_WRLVL<<0)),
	164	.datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) \|
	165	(MT47H128M16RT25E_PHY_GATELVL<<20) \|
	166	(MT47H128M16RT25E_PHY_GATELVL<<10) \|
	167	(MT47H128M16RT25E_PHY_GATELVL<<0)),
	168	.datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) \|
	169	(MT47H128M16RT25E_PHY_FIFO_WE<<20) \|
	170	(MT47H128M16RT25E_PHY_FIFO_WE<<10) \|
	171	(MT47H128M16RT25E_PHY_FIFO_WE<<0)),
	172	.datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) \|
	173	(MT47H128M16RT25E_PHY_WR_DATA<<20) \|
	174	(MT47H128M16RT25E_PHY_WR_DATA<<10) \|
	175	(MT47H128M16RT25E_PHY_WR_DATA<<0)),
	176	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
c00f69db PK	177	.datadldiff0 = PHY_DLL_LOCK_DIFF,
c00f69db PK	178	};
e363426e	179
c00f69db	180	static const struct cmd_control ddr2_cmd_ctrl_data = {
c7d35bef PK	181	.cmd0csratio = MT47H128M16RT25E_RATIO,
	182	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	183	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db	184
c7d35bef PK	185	.cmd1csratio = MT47H128M16RT25E_RATIO,
	186	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	187	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db	188
c7d35bef PK	189	.cmd2csratio = MT47H128M16RT25E_RATIO,
	190	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
	191	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
c00f69db PK	192	};
	193
	194	static const struct emif_regs ddr2_emif_reg_data = {
c7d35bef PK	195	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
	196	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
	197	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
	198	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
	199	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
	200	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
c00f69db PK	201	};
	202
	203	static const struct ddr_data ddr3_data = {
c7d35bef PK	204	.datardsratio0 = MT41J128MJT125_RD_DQS,
	205	.datawdsratio0 = MT41J128MJT125_WR_DQS,
	206	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
	207	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
c00f69db PK	208	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	209	};
	210
13526f71 JL	211	static const struct ddr_data ddr3_evm_data = {
	212	.datardsratio0 = MT41J512M8RH125_RD_DQS,
	213	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
	214	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
	215	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
	216	.datadldiff0 = PHY_DLL_LOCK_DIFF,
	217	};
	218
c00f69db	219	static const struct cmd_control ddr3_cmd_ctrl_data = {
c7d35bef PK	220	.cmd0csratio = MT41J128MJT125_RATIO,
	221	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	222	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db	223
c7d35bef PK	224	.cmd1csratio = MT41J128MJT125_RATIO,
	225	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	226	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db	227
c7d35bef PK	228	.cmd2csratio = MT41J128MJT125_RATIO,
	229	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
	230	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
c00f69db PK	231	};
c00f69db PK	232
13526f71 JL	233	static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
	234	.cmd0csratio = MT41J512M8RH125_RATIO,
	235	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	236	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	237
	238	.cmd1csratio = MT41J512M8RH125_RATIO,
	239	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	240	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	241
	242	.cmd2csratio = MT41J512M8RH125_RATIO,
	243	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
	244	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
	245	};
	246
c00f69db	247	static struct emif_regs ddr3_emif_reg_data = {
c7d35bef PK	248	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
	249	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
	250	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
	251	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
	252	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
	253	.zq_config = MT41J128MJT125_ZQ_CFG,
59dcf970 VH	254	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY \|
59dcf970 VH	255	PHY_EN_DYN_PWRDN,
c00f69db	256	};
13526f71 JL	257
	258	static struct emif_regs ddr3_evm_emif_reg_data = {
	259	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
	260	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
	261	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
	262	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
	263	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
	264	.zq_config = MT41J512M8RH125_ZQ_CFG,
59dcf970 VH	265	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY \|
59dcf970 VH	266	PHY_EN_DYN_PWRDN,
13526f71	267	};
c00f69db	268	#endif
e363426e PK	269
	270	/*
	271	* early system init of muxing and clocks.
	272	*/
	273	void s_init(void)
	274	{
	275	/* WDT1 is already running when the bootloader gets control
	276	* Disable it to avoid "random" resets
	277	*/
	278	writel(0xAAAA, &wdtimer->wdtwspr);
	279	while (readl(&wdtimer->wdtwwps) != 0x0)
	280	;
	281	writel(0x5555, &wdtimer->wdtwspr);
	282	while (readl(&wdtimer->wdtwwps) != 0x0)
	283	;
	284
	285	#ifdef CONFIG_SPL_BUILD
	286	/* Setup the PLLs and the clocks for the peripherals */
	287	pll_init();
	288
	289	/* Enable RTC32K clock */
	290	rtc32k_enable();
	291
	292	/* UART softreset */
	293	u32 regVal;
	294
6422b70b	295	#ifdef CONFIG_SERIAL1
e363426e	296	enable_uart0_pin_mux();
6422b70b AB	297	#endif /* CONFIG_SERIAL1 */
	298	#ifdef CONFIG_SERIAL2
	299	enable_uart1_pin_mux();
	300	#endif /* CONFIG_SERIAL2 */
	301	#ifdef CONFIG_SERIAL3
	302	enable_uart2_pin_mux();
	303	#endif /* CONFIG_SERIAL3 */
	304	#ifdef CONFIG_SERIAL4
	305	enable_uart3_pin_mux();
	306	#endif /* CONFIG_SERIAL4 */
	307	#ifdef CONFIG_SERIAL5
	308	enable_uart4_pin_mux();
	309	#endif /* CONFIG_SERIAL5 */
	310	#ifdef CONFIG_SERIAL6
	311	enable_uart5_pin_mux();
	312	#endif /* CONFIG_SERIAL6 */
e363426e PK	313
	314	regVal = readl(&uart_base->uartsyscfg);
	315	regVal \|= UART_RESET;
	316	writel(regVal, &uart_base->uartsyscfg);
	317	while ((readl(&uart_base->uartsyssts) &
	318	UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
	319	;
	320
	321	/* Disable smart idle */
	322	regVal = readl(&uart_base->uartsyscfg);
	323	regVal \|= UART_SMART_IDLE_EN;
	324	writel(regVal, &uart_base->uartsyscfg);
	325
	326	gd = &gdata;
	327
	328	preloader_console_init();
	329
	330	/* Initalize the board header */
	331	enable_i2c0_pin_mux();
	332	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	333	if (read_eeprom() < 0)
	334	puts("Could not get board ID.\n");
	335
	336	enable_board_pin_mux(&header);
	337	if (board_is_evm_sk()) {
	338	/*
	339	* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
	340	* This is safe enough to do on older revs.
	341	*/
	342	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	343	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
	344	}
	345
c00f69db	346	if (board_is_evm_sk() \|\| board_is_bone_lt())
c7d35bef	347	config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
c00f69db	348	&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
13526f71 JL	349	else if (board_is_evm_15_or_later())
	350	config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
	351	&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
c00f69db	352	else
c7d35bef	353	config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
c00f69db	354	&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
e363426e PK	355	#endif
	356	}
	357
	358	/*
	359	* Basic board specific setup. Pinmux has been handled already.
	360	*/
	361	int board_init(void)
	362	{
	363	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	364	if (read_eeprom() < 0)
	365	puts("Could not get board ID.\n");
	366
	367	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
	368
98b5c269 IY	369	gpmc_init();
98b5c269 IY	370
e363426e PK	371	return 0;
	372	}
	373
044fc14b TR	374	#ifdef CONFIG_BOARD_LATE_INIT
	375	int board_late_init(void)
	376	{
	377	#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	378	char safe_string[HDR_NAME_LEN + 1];
	379
	380	/* Now set variables based on the header. */
	381	strncpy(safe_string, (char *)header.name, sizeof(header.name));
	382	safe_string[sizeof(header.name)] = 0;
	383	setenv("board_name", safe_string);
	384
	385	strncpy(safe_string, (char *)header.version, sizeof(header.version));
	386	safe_string[sizeof(header.version)] = 0;
	387	setenv("board_rev", safe_string);
	388	#endif
	389
	390	return 0;
	391	}
	392	#endif
	393
c0e66793 IY	394	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
c0e66793 IY	395	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
e363426e PK	396	static void cpsw_control(int enabled)
	397	{
	398	/* VTP can be added here */
	399
	400	return;
	401	}
	402
	403	static struct cpsw_slave_data cpsw_slaves[] = {
	404	{
	405	.slave_reg_ofs = 0x208,
	406	.sliver_reg_ofs = 0xd80,
	407	.phy_id = 0,
	408	},
	409	{
	410	.slave_reg_ofs = 0x308,
	411	.sliver_reg_ofs = 0xdc0,
	412	.phy_id = 1,
	413	},
	414	};
	415
	416	static struct cpsw_platform_data cpsw_data = {
81df2bab MP	417	.mdio_base = CPSW_MDIO_BASE,
81df2bab MP	418	.cpsw_base = CPSW_BASE,
e363426e PK	419	.mdio_div = 0xff,
	420	.channels = 8,
	421	.cpdma_reg_ofs = 0x800,
	422	.slaves = 1,
	423	.slave_data = cpsw_slaves,
	424	.ale_reg_ofs = 0xd00,
	425	.ale_entries = 1024,
	426	.host_port_reg_ofs = 0x108,
	427	.hw_stats_reg_ofs = 0x900,
	428	.mac_control = (1 << 5),
	429	.control = cpsw_control,
	430	.host_port_num = 0,
	431	.version = CPSW_CTRL_VERSION_2,
	432	};
d2aa1154	433	#endif
e363426e	434
d2aa1154 IY	435	#if defined(CONFIG_DRIVER_TI_CPSW) \|\| \
d2aa1154 IY	436	(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
e363426e PK	437	int board_eth_init(bd_t *bis)
e363426e PK	438	{
d2aa1154	439	int rv, n = 0;
e363426e PK	440	uint8_t mac_addr[6];
	441	uint32_t mac_hi, mac_lo;
	442
c0e66793 IY	443	/* try reading mac address from efuse */
	444	mac_lo = readl(&cdev->macid0l);
	445	mac_hi = readl(&cdev->macid0h);
	446	mac_addr[0] = mac_hi & 0xFF;
	447	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
	448	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
	449	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
	450	mac_addr[4] = mac_lo & 0xFF;
	451	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
	452
	453	#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) \|\| \
	454	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
	455	if (!getenv("ethaddr")) {
	456	printf("<ethaddr> not set. Validating first E-fuse MAC\n");
e363426e PK	457
	458	if (is_valid_ether_addr(mac_addr))
	459	eth_setenv_enetaddr("ethaddr", mac_addr);
e363426e PK	460	}
e363426e PK	461
a956bdcb	462	if (board_is_bone() \|\| board_is_bone_lt() \|\| board_is_idk()) {
e363426e PK	463	writel(MII_MODE_ENABLE, &cdev->miisel);
	464	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	465	PHY_INTERFACE_MODE_MII;
	466	} else {
	467	writel(RGMII_MODE_ENABLE, &cdev->miisel);
	468	cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
	469	PHY_INTERFACE_MODE_RGMII;
	470	}
	471
d2aa1154 IY	472	rv = cpsw_register(&cpsw_data);
	473	if (rv < 0)
	474	printf("Error %d registering CPSW switch\n", rv);
	475	else
	476	n += rv;
1634e969 TR	477
	478	/*
	479	*
	480	* CPSW RGMII Internal Delay Mode is not supported in all PVT
	481	* operating points. So we must set the TX clock delay feature
	482	* in the AR8051 PHY. Since we only support a single ethernet
	483	* device in U-Boot, we only do this for the first instance.
	484	*/
	485	#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
	486	#define AR8051_PHY_DEBUG_DATA_REG 0x1e
	487	#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
	488	#define AR8051_RGMII_TX_CLK_DLY 0x100
	489
	490	if (board_is_evm_sk() \|\| board_is_gp_evm()) {
	491	const char *devname;
	492	devname = miiphy_get_current_dev();
	493
	494	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
	495	AR8051_DEBUG_RGMII_CLK_DLY_REG);
	496	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
	497	AR8051_RGMII_TX_CLK_DLY);
	498	}
d2aa1154	499	#endif
c0e66793 IY	500	#if defined(CONFIG_USB_ETHER) && \
	501	(!defined(CONFIG_SPL_BUILD) \|\| defined(CONFIG_SPL_USBETH_SUPPORT))
	502	if (is_valid_ether_addr(mac_addr))
	503	eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
	504
d2aa1154 IY	505	rv = usb_eth_initialize(bis);
	506	if (rv < 0)
	507	printf("Error %d registering USB_ETHER\n", rv);
	508	else
	509	n += rv;
	510	#endif
	511	return n;
e363426e PK	512	}
e363426e PK	513	#endif