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bda920c6 VA |
1 | /* |
2 | * K2G EVM : Board initialization | |
3 | * | |
4 | * (C) Copyright 2015 | |
5 | * Texas Instruments Incorporated, <www.ti.com> | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0+ | |
8 | */ | |
9 | #include <common.h> | |
10 | #include <asm/arch/clock.h> | |
91266ccb | 11 | #include <asm/ti-common/keystone_net.h> |
3b68939f RQ |
12 | #include <asm/arch/psc_defs.h> |
13 | #include <asm/arch/mmc_host_def.h> | |
5f48da9a CJF |
14 | #include <fdtdec.h> |
15 | #include <i2c.h> | |
dd78b8cf | 16 | #include "mux-k2g.h" |
752a8311 | 17 | #include "../common/board_detect.h" |
bda920c6 | 18 | |
5f48da9a CJF |
19 | #define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B |
20 | ||
c5f177de LV |
21 | const unsigned int sysclk_array[MAX_SYSCLK] = { |
22 | 19200000, | |
23 | 24000000, | |
24 | 25000000, | |
25 | 26000000, | |
26 | }; | |
27 | ||
ee3c6532 LV |
28 | unsigned int get_external_clk(u32 clk) |
29 | { | |
30 | unsigned int clk_freq; | |
31 | u8 sysclk_index = get_sysclk_index(); | |
32 | ||
33 | switch (clk) { | |
34 | case sys_clk: | |
35 | clk_freq = sysclk_array[sysclk_index]; | |
36 | break; | |
37 | case pa_clk: | |
38 | clk_freq = sysclk_array[sysclk_index]; | |
39 | break; | |
40 | case tetris_clk: | |
41 | clk_freq = sysclk_array[sysclk_index]; | |
42 | break; | |
43 | case ddr3a_clk: | |
44 | clk_freq = sysclk_array[sysclk_index]; | |
45 | break; | |
46 | case uart_clk: | |
47 | clk_freq = sysclk_array[sysclk_index]; | |
48 | break; | |
49 | default: | |
50 | clk_freq = 0; | |
51 | break; | |
52 | } | |
53 | ||
54 | return clk_freq; | |
55 | } | |
e6d71e1c | 56 | |
ef76ebb1 LV |
57 | static int arm_speeds[DEVSPEED_NUMSPDS] = { |
58 | SPD400, | |
59 | SPD600, | |
60 | SPD800, | |
61 | SPD900, | |
62 | SPD1000, | |
63 | SPD900, | |
64 | SPD800, | |
65 | SPD600, | |
66 | SPD400, | |
67 | SPD200, | |
68 | }; | |
69 | ||
70 | static int dev_speeds[DEVSPEED_NUMSPDS] = { | |
71 | SPD600, | |
72 | SPD800, | |
73 | SPD900, | |
74 | SPD1000, | |
75 | SPD900, | |
76 | SPD800, | |
77 | SPD600, | |
78 | SPD400, | |
79 | }; | |
80 | ||
c5f177de LV |
81 | static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = { |
82 | [SYSCLK_19MHz] = { | |
83 | [SPD400] = {MAIN_PLL, 125, 3, 2}, | |
84 | [SPD600] = {MAIN_PLL, 125, 2, 2}, | |
85 | [SPD800] = {MAIN_PLL, 250, 3, 2}, | |
9cb5eaf2 LV |
86 | [SPD900] = {MAIN_PLL, 187, 2, 2}, |
87 | [SPD1000] = {MAIN_PLL, 104, 1, 2}, | |
c5f177de LV |
88 | }, |
89 | [SYSCLK_24MHz] = { | |
90 | [SPD400] = {MAIN_PLL, 100, 3, 2}, | |
91 | [SPD600] = {MAIN_PLL, 300, 6, 2}, | |
92 | [SPD800] = {MAIN_PLL, 200, 3, 2}, | |
9cb5eaf2 LV |
93 | [SPD900] = {MAIN_PLL, 75, 1, 2}, |
94 | [SPD1000] = {MAIN_PLL, 250, 3, 2}, | |
c5f177de LV |
95 | }, |
96 | [SYSCLK_25MHz] = { | |
97 | [SPD400] = {MAIN_PLL, 32, 1, 2}, | |
98 | [SPD600] = {MAIN_PLL, 48, 1, 2}, | |
99 | [SPD800] = {MAIN_PLL, 64, 1, 2}, | |
9cb5eaf2 LV |
100 | [SPD900] = {MAIN_PLL, 72, 1, 2}, |
101 | [SPD1000] = {MAIN_PLL, 80, 1, 2}, | |
c5f177de LV |
102 | }, |
103 | [SYSCLK_26MHz] = { | |
104 | [SPD400] = {MAIN_PLL, 400, 13, 2}, | |
105 | [SPD600] = {MAIN_PLL, 230, 5, 2}, | |
106 | [SPD800] = {MAIN_PLL, 123, 2, 2}, | |
9cb5eaf2 LV |
107 | [SPD900] = {MAIN_PLL, 69, 1, 2}, |
108 | [SPD1000] = {MAIN_PLL, 384, 5, 2}, | |
c5f177de LV |
109 | }, |
110 | }; | |
111 | ||
112 | static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = { | |
113 | [SYSCLK_19MHz] = { | |
114 | [SPD200] = {TETRIS_PLL, 625, 6, 10}, | |
115 | [SPD400] = {TETRIS_PLL, 125, 1, 6}, | |
116 | [SPD600] = {TETRIS_PLL, 125, 1, 4}, | |
117 | [SPD800] = {TETRIS_PLL, 333, 2, 4}, | |
118 | [SPD900] = {TETRIS_PLL, 187, 2, 2}, | |
119 | [SPD1000] = {TETRIS_PLL, 104, 1, 2}, | |
120 | }, | |
121 | [SYSCLK_24MHz] = { | |
122 | [SPD200] = {TETRIS_PLL, 250, 3, 10}, | |
123 | [SPD400] = {TETRIS_PLL, 100, 1, 6}, | |
124 | [SPD600] = {TETRIS_PLL, 100, 1, 4}, | |
125 | [SPD800] = {TETRIS_PLL, 400, 3, 4}, | |
126 | [SPD900] = {TETRIS_PLL, 75, 1, 2}, | |
127 | [SPD1000] = {TETRIS_PLL, 250, 3, 2}, | |
128 | }, | |
129 | [SYSCLK_25MHz] = { | |
130 | [SPD200] = {TETRIS_PLL, 80, 1, 10}, | |
131 | [SPD400] = {TETRIS_PLL, 96, 1, 6}, | |
132 | [SPD600] = {TETRIS_PLL, 96, 1, 4}, | |
133 | [SPD800] = {TETRIS_PLL, 128, 1, 4}, | |
134 | [SPD900] = {TETRIS_PLL, 72, 1, 2}, | |
135 | [SPD1000] = {TETRIS_PLL, 80, 1, 2}, | |
136 | }, | |
137 | [SYSCLK_26MHz] = { | |
138 | [SPD200] = {TETRIS_PLL, 307, 4, 10}, | |
139 | [SPD400] = {TETRIS_PLL, 369, 4, 6}, | |
140 | [SPD600] = {TETRIS_PLL, 369, 4, 4}, | |
141 | [SPD800] = {TETRIS_PLL, 123, 1, 4}, | |
142 | [SPD900] = {TETRIS_PLL, 69, 1, 2}, | |
143 | [SPD1000] = {TETRIS_PLL, 384, 5, 2}, | |
144 | }, | |
ef76ebb1 LV |
145 | }; |
146 | ||
c5f177de LV |
147 | static struct pll_init_data uart_pll_config[MAX_SYSCLK] = { |
148 | [SYSCLK_19MHz] = {UART_PLL, 160, 1, 8}, | |
149 | [SYSCLK_24MHz] = {UART_PLL, 128, 1, 8}, | |
150 | [SYSCLK_25MHz] = {UART_PLL, 768, 5, 10}, | |
151 | [SYSCLK_26MHz] = {UART_PLL, 384, 13, 2}, | |
ef76ebb1 LV |
152 | }; |
153 | ||
c5f177de LV |
154 | static struct pll_init_data nss_pll_config[MAX_SYSCLK] = { |
155 | [SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2}, | |
156 | [SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2}, | |
157 | [SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2}, | |
158 | [SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2}, | |
159 | }; | |
160 | ||
161 | static struct pll_init_data ddr3_pll_config[MAX_SYSCLK] = { | |
162 | [SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16}, | |
163 | [SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16}, | |
164 | [SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16}, | |
165 | [SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16}, | |
166 | }; | |
bda920c6 VA |
167 | |
168 | struct pll_init_data *get_pll_init_data(int pll) | |
169 | { | |
ef76ebb1 | 170 | int speed; |
bda920c6 | 171 | struct pll_init_data *data = NULL; |
c5f177de | 172 | u8 sysclk_index = get_sysclk_index(); |
bda920c6 VA |
173 | |
174 | switch (pll) { | |
175 | case MAIN_PLL: | |
ef76ebb1 | 176 | speed = get_max_dev_speed(dev_speeds); |
c5f177de | 177 | data = &main_pll_config[sysclk_index][speed]; |
bda920c6 VA |
178 | break; |
179 | case TETRIS_PLL: | |
ef76ebb1 | 180 | speed = get_max_arm_speed(arm_speeds); |
c5f177de | 181 | data = &tetris_pll_config[sysclk_index][speed]; |
bda920c6 VA |
182 | break; |
183 | case NSS_PLL: | |
c5f177de | 184 | data = &nss_pll_config[sysclk_index]; |
bda920c6 VA |
185 | break; |
186 | case UART_PLL: | |
c5f177de | 187 | data = &uart_pll_config[sysclk_index]; |
bda920c6 VA |
188 | break; |
189 | case DDR3_PLL: | |
c5f177de | 190 | data = &ddr3_pll_config[sysclk_index]; |
bda920c6 VA |
191 | break; |
192 | default: | |
193 | data = NULL; | |
194 | } | |
195 | ||
196 | return data; | |
197 | } | |
198 | ||
199 | s16 divn_val[16] = { | |
200 | -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 | |
201 | }; | |
202 | ||
4aa2ba3a | 203 | #if defined(CONFIG_MMC) |
3b68939f RQ |
204 | int board_mmc_init(bd_t *bis) |
205 | { | |
206 | if (psc_enable_module(KS2_LPSC_MMC)) { | |
207 | printf("%s module enabled failed\n", __func__); | |
208 | return -1; | |
209 | } | |
210 | ||
211 | omap_mmc_init(0, 0, 0, -1, -1); | |
212 | omap_mmc_init(1, 0, 0, -1, -1); | |
213 | return 0; | |
214 | } | |
215 | #endif | |
216 | ||
7234f215 CJF |
217 | #if defined(CONFIG_FIT_EMBED) |
218 | int board_fit_config_name_match(const char *name) | |
219 | { | |
220 | bool eeprom_read = board_ti_was_eeprom_read(); | |
221 | ||
222 | if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read) | |
223 | return 0; | |
224 | else if (!strcmp(name, "keystone-k2g-evm") && board_ti_is("66AK2GGP")) | |
225 | return 0; | |
226 | else | |
227 | return -1; | |
228 | } | |
229 | #endif | |
230 | ||
5f48da9a CJF |
231 | #if defined(CONFIG_DTB_RESELECT) |
232 | static int k2g_alt_board_detect(void) | |
233 | { | |
234 | int rc; | |
235 | ||
236 | rc = i2c_set_bus_num(1); | |
237 | if (rc) | |
238 | return rc; | |
239 | ||
240 | rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS); | |
241 | if (rc) | |
242 | return rc; | |
243 | ||
244 | ti_i2c_eeprom_am_set("66AK2GGP", "1.0X"); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
e2924e59 LV |
249 | static void k2g_reset_mux_config(void) |
250 | { | |
251 | /* Unlock the reset mux register */ | |
252 | clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); | |
253 | ||
254 | /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */ | |
255 | clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK, | |
256 | RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT); | |
257 | ||
258 | /* lock the reset mux register to prevent any spurious writes. */ | |
259 | setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK); | |
260 | } | |
261 | ||
e820f523 | 262 | int embedded_dtb_select(void) |
bda920c6 | 263 | { |
e820f523 CJF |
264 | int rc; |
265 | rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, | |
266 | CONFIG_EEPROM_CHIP_ADDRESS); | |
267 | if (rc) { | |
268 | rc = k2g_alt_board_detect(); | |
269 | if (rc) { | |
270 | printf("Unable to do board detection\n"); | |
271 | return -1; | |
272 | } | |
273 | } | |
bda920c6 | 274 | |
e820f523 | 275 | fdtdec_setup(); |
dd78b8cf | 276 | |
e2924e59 LV |
277 | k2g_reset_mux_config(); |
278 | ||
83b9bf11 LV |
279 | /* deassert FLASH_HOLD */ |
280 | clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET, | |
281 | BIT(9)); | |
282 | setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET, | |
283 | BIT(9)); | |
284 | ||
bda920c6 VA |
285 | return 0; |
286 | } | |
287 | #endif | |
288 | ||
752a8311 RQ |
289 | #ifdef CONFIG_BOARD_LATE_INIT |
290 | int board_late_init(void) | |
291 | { | |
292 | #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT) | |
293 | int rc; | |
294 | ||
295 | rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, | |
296 | CONFIG_EEPROM_CHIP_ADDRESS); | |
297 | if (rc) | |
298 | printf("ti_i2c_eeprom_init failed %d\n", rc); | |
299 | ||
300 | board_ti_set_ethaddr(1); | |
301 | #endif | |
302 | ||
303 | return 0; | |
304 | } | |
305 | #endif | |
306 | ||
e820f523 CJF |
307 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
308 | int board_early_init_f(void) | |
309 | { | |
310 | init_plls(); | |
311 | ||
312 | k2g_mux_config(); | |
313 | ||
314 | return 0; | |
315 | } | |
316 | #endif | |
317 | ||
bda920c6 VA |
318 | #ifdef CONFIG_SPL_BUILD |
319 | void spl_init_keystone_plls(void) | |
320 | { | |
321 | init_plls(); | |
322 | } | |
323 | #endif | |
91266ccb VA |
324 | |
325 | #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET | |
326 | struct eth_priv_t eth_priv_cfg[] = { | |
327 | { | |
328 | .int_name = "K2G_EMAC", | |
329 | .rx_flow = 0, | |
330 | .phy_addr = 0, | |
331 | .slave_port = 1, | |
332 | .sgmii_link_type = SGMII_LINK_MAC_PHY, | |
333 | .phy_if = PHY_INTERFACE_MODE_RGMII, | |
334 | }, | |
335 | }; | |
336 | ||
337 | int get_num_eth_ports(void) | |
338 | { | |
339 | return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); | |
340 | } | |
341 | #endif |