[people/ms/u-boot.git] / common / cmd_eeprom.c

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 * Support for read and write access to EEPROM like memory devices. This
 * includes regular EEPROM as well as  FRAM (ferroelectic nonvolaile RAM).
 * FRAM devices read and write data at bus speed. In particular, there is no
 * write delay. Also, there is no limit imposed on the number of bytes that can
 * be transferred with a single read or write.
 *
 * Use the following configuration options to ensure no unneeded performance
 * degradation (typical for EEPROM) is incured for FRAM memory:
 *
 * #define CONFIG_SYS_I2C_FRAM
 * #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
 *
 */

#include <common.h>
#include <config.h>
#include <command.h>
#include <i2c.h>

extern void eeprom_init  (void);
extern int  eeprom_read  (unsigned dev_addr, unsigned offset,
			  uchar *buffer, unsigned cnt);
extern int  eeprom_write (unsigned dev_addr, unsigned offset,
			  uchar *buffer, unsigned cnt);
#if defined(CONFIG_SYS_EEPROM_WREN)
extern int eeprom_write_enable (unsigned dev_addr, int state);
#endif


#if defined(CONFIG_SYS_EEPROM_X40430)
	/* Maximum number of times to poll for acknowledge after write */
#define MAX_ACKNOWLEDGE_POLLS	10
#endif

/* ------------------------------------------------------------------------- */

#if defined(CONFIG_CMD_EEPROM)
int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
	const char *const fmt =
		"\nEEPROM @0x%lX %s: addr %08lx  off %04lx  count %ld ... ";

#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
	if (argc == 6) {
		ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
		ulong addr = simple_strtoul (argv[3], NULL, 16);
		ulong off  = simple_strtoul (argv[4], NULL, 16);
		ulong cnt  = simple_strtoul (argv[5], NULL, 16);
#else
	if (argc == 5) {
		ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
		ulong addr = simple_strtoul (argv[2], NULL, 16);
		ulong off  = simple_strtoul (argv[3], NULL, 16);
		ulong cnt  = simple_strtoul (argv[4], NULL, 16);
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */

# if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		eeprom_init ();
# endif /* !CONFIG_SPI */

		if (strcmp (argv[1], "read") == 0) {
			int rcode;

			printf (fmt, dev_addr, argv[1], addr, off, cnt);

			rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);

			puts ("done\n");
			return rcode;
		} else if (strcmp (argv[1], "write") == 0) {
			int rcode;

			printf (fmt, dev_addr, argv[1], addr, off, cnt);

			rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);

			puts ("done\n");
			return rcode;
		}
	}

	return cmd_usage(cmdtp);
}
#endif

/*-----------------------------------------------------------------------
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
 *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
 *   0x00000nxx for EEPROM address selectors and page number at n.
 */

#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) || CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 || CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
#endif
#endif

int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
	unsigned end = offset + cnt;
	unsigned blk_off;
	int rcode = 0;

	/* Read data until done or would cross a page boundary.
	 * We must write the address again when changing pages
	 * because the next page may be in a different device.
	 */
	while (offset < end) {
		unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
		unsigned maxlen;
#endif

#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
		uchar addr[2];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 8;		/* block number */
		addr[1] = blk_off;		/* block offset */
		alen	= 2;
#else
		uchar addr[3];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 16;		/* block number */
		addr[1] = offset >>  8;		/* upper address octet */
		addr[2] = blk_off;		/* lower address octet */
		alen	= 3;
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

		addr[0] |= dev_addr;		/* insert device address */

		len = end - offset;

		/*
		 * For a FRAM device there is no limit on the number of the
		 * bytes that can be ccessed with the single read or write
		 * operation.
		 */
#if !defined(CONFIG_SYS_I2C_FRAM)
		maxlen = 0x100 - blk_off;
		if (maxlen > I2C_RXTX_LEN)
			maxlen = I2C_RXTX_LEN;
		if (len > maxlen)
			len = maxlen;
#endif

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		spi_read (addr, alen, buffer, len);
#else
		if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
			rcode = 1;
#endif
		buffer += len;
		offset += len;
	}

	return rcode;
}

/*-----------------------------------------------------------------------
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
 *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
 *
 * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
 *   0x00000nxx for EEPROM address selectors and page number at n.
 */

int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
{
	unsigned end = offset + cnt;
	unsigned blk_off;
	int rcode = 0;

#if defined(CONFIG_SYS_EEPROM_X40430)
	uchar	contr_r_addr[2];
	uchar	addr_void[2];
	uchar	contr_reg[2];
	uchar	ctrl_reg_v;
	int	i;
#endif

#if defined(CONFIG_SYS_EEPROM_WREN)
	eeprom_write_enable (dev_addr,1);
#endif
	/* Write data until done or would cross a write page boundary.
	 * We must write the address again when changing pages
	 * because the address counter only increments within a page.
	 */

	while (offset < end) {
		unsigned alen, len;
#if !defined(CONFIG_SYS_I2C_FRAM)
		unsigned maxlen;
#endif

#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
		uchar addr[2];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 8;		/* block number */
		addr[1] = blk_off;		/* block offset */
		alen	= 2;
#else
		uchar addr[3];

		blk_off = offset & 0xFF;	/* block offset */

		addr[0] = offset >> 16;		/* block number */
		addr[1] = offset >>  8;		/* upper address octet */
		addr[2] = blk_off;		/* lower address octet */
		alen	= 3;
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

		addr[0] |= dev_addr;		/* insert device address */

		len = end - offset;

		/*
		 * For a FRAM device there is no limit on the number of the
		 * bytes that can be accessed with the single read or write
		 * operation.
		 */
#if !defined(CONFIG_SYS_I2C_FRAM)

#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)

#define	EEPROM_PAGE_SIZE	(1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
#define	EEPROM_PAGE_OFFSET(x)	((x) & (EEPROM_PAGE_SIZE - 1))

		maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
#else
		maxlen = 0x100 - blk_off;
#endif
		if (maxlen > I2C_RXTX_LEN)
			maxlen = I2C_RXTX_LEN;

		if (len > maxlen)
			len = maxlen;
#endif

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
		spi_write (addr, alen, buffer, len);
#else
#if defined(CONFIG_SYS_EEPROM_X40430)
		/* Get the value of the control register.
		 * Set current address (internal pointer in the x40430)
		 * to 0x1ff.
		 */
		contr_r_addr[0] = 9;
		contr_r_addr[1] = 0xff;
		addr_void[0]    = 0;
		addr_void[1]    = addr[1];
#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
		contr_r_addr[0] |= CONFIG_SYS_I2C_EEPROM_ADDR;
		addr_void[0]    |= CONFIG_SYS_I2C_EEPROM_ADDR;
#endif
		contr_reg[0] = 0xff;
		if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
			rcode = 1;
		}
		ctrl_reg_v = contr_reg[0];

		/* Are any of the eeprom blocks write protected?
		 */
		if (ctrl_reg_v & 0x18) {
			ctrl_reg_v &= ~0x18;   /* reset block protect bits  */
			ctrl_reg_v |=  0x02;   /* set write enable latch    */
			ctrl_reg_v &= ~0x04;   /* clear RWEL                */

			/* Set write enable latch.
			 */
			contr_reg[0] = 0x02;
			if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* Set register write enable latch.
			 */
			contr_reg[0] = 0x06;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* Modify ctrl register.
			 */
			contr_reg[0] = ctrl_reg_v;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
				rcode = 1;
			}

			/* The write (above) is an operation on NV memory.
			 * These can take some time (~5ms), and the device
			 * will not respond to further I2C messages till
			 * it's completed the write.
			 * So poll device for an I2C acknowledge.
			 * When we get one we know we can continue with other
			 * operations.
			 */
			contr_reg[0] = 0;
			for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
				if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
					break;	/* got ack */
#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
				udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
			}
			if (i == MAX_ACKNOWLEDGE_POLLS) {
				puts ("EEPROM poll acknowledge failed\n");
				rcode = 1;
			}
		}

		/* Is the write enable latch on?.
		 */
		else if (!(ctrl_reg_v & 0x02)) {
			/* Set write enable latch.
			 */
			contr_reg[0] = 0x02;
			if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
			       rcode = 1;
			}
		}
		/* Write is enabled ... now write eeprom value.
		 */
#endif
		if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
			rcode = 1;

#endif
		buffer += len;
		offset += len;

#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
#endif
	}
#if defined(CONFIG_SYS_EEPROM_WREN)
	eeprom_write_enable (dev_addr,0);
#endif
	return rcode;
}

#if !defined(CONFIG_SPI) || defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
int
eeprom_probe (unsigned dev_addr, unsigned offset)
{
	unsigned char chip;

	/* Probe the chip address
	 */
#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
	chip = offset >> 8;		/* block number */
#else
	chip = offset >> 16;		/* block number */
#endif	/* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */

	chip |= dev_addr;		/* insert device address */

	return (i2c_probe (chip));
}
#endif

/*-----------------------------------------------------------------------
 * Set default values
 */
#ifndef	CONFIG_SYS_I2C_SPEED
#define	CONFIG_SYS_I2C_SPEED	50000
#endif

void eeprom_init  (void)
{

#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
	spi_init_f ();
#endif
#if defined(CONFIG_HARD_I2C) || \
    defined(CONFIG_SOFT_I2C)
	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
}

/*-----------------------------------------------------------------------
 */

/***************************************************/

#if defined(CONFIG_CMD_EEPROM)

#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
U_BOOT_CMD(
	eeprom,	6,	1,	do_eeprom,
	"EEPROM sub-system",
	"read  devaddr addr off cnt\n"
	"eeprom write devaddr addr off cnt\n"
	"       - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
);
#else /* One EEPROM */
U_BOOT_CMD(
	eeprom,	5,	1,	do_eeprom,
	"EEPROM sub-system",
	"read  addr off cnt\n"
	"eeprom write addr off cnt\n"
	"       - read/write `cnt' bytes at EEPROM offset `off'"
);
#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */

#endif
Commit	Line	Data
3863585b WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
d4f5c728	25	/*
	26	* Support for read and write access to EEPROM like memory devices. This
	27	* includes regular EEPROM as well as FRAM (ferroelectic nonvolaile RAM).
	28	* FRAM devices read and write data at bus speed. In particular, there is no
e506a006	29	* write delay. Also, there is no limit imposed on the number of bytes that can
d4f5c728	30	* be transferred with a single read or write.
6617aae9	31	*
d4f5c728	32	* Use the following configuration options to ensure no unneeded performance
d4f5c728	33	* degradation (typical for EEPROM) is incured for FRAM memory:
6617aae9	34	*
6d0f6bcf JCPV	35	* #define CONFIG_SYS_I2C_FRAM
6d0f6bcf JCPV	36	* #undef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
d4f5c728	37	*
	38	*/
	39
3863585b WD	40	#include <common.h>
	41	#include <config.h>
	42	#include <command.h>
	43	#include <i2c.h>
	44
3863585b WD	45	extern void eeprom_init (void);
	46	extern int eeprom_read (unsigned dev_addr, unsigned offset,
	47	uchar *buffer, unsigned cnt);
	48	extern int eeprom_write (unsigned dev_addr, unsigned offset,
	49	uchar *buffer, unsigned cnt);
6d0f6bcf	50	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	51	extern int eeprom_write_enable (unsigned dev_addr, int state);
98f4a3df SR	52	#endif
3863585b WD	53
3863585b WD	54
6d0f6bcf	55	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	56	/* Maximum number of times to poll for acknowledge after write */
	57	#define MAX_ACKNOWLEDGE_POLLS 10
	58	#endif
	59
	60	/* ------------------------------------------------------------------------- */
	61
baa26db4	62	#if defined(CONFIG_CMD_EEPROM)
54841ab5	63	int do_eeprom ( cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
3863585b WD	64	{
	65	const char *const fmt =
	66	"\nEEPROM @0x%lX %s: addr %08lx off %04lx count %ld ... ";
	67
6d0f6bcf	68	#if defined(CONFIG_SYS_I2C_MULTI_EEPROMS)
3863585b WD	69	if (argc == 6) {
	70	ulong dev_addr = simple_strtoul (argv[2], NULL, 16);
	71	ulong addr = simple_strtoul (argv[3], NULL, 16);
	72	ulong off = simple_strtoul (argv[4], NULL, 16);
	73	ulong cnt = simple_strtoul (argv[5], NULL, 16);
	74	#else
	75	if (argc == 5) {
6d0f6bcf	76	ulong dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
3863585b WD	77	ulong addr = simple_strtoul (argv[2], NULL, 16);
	78	ulong off = simple_strtoul (argv[3], NULL, 16);
	79	ulong cnt = simple_strtoul (argv[4], NULL, 16);
6d0f6bcf	80	#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
3863585b	81
548738b4	82	# if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	83	eeprom_init ();
	84	# endif /* !CONFIG_SPI */
	85
	86	if (strcmp (argv[1], "read") == 0) {
	87	int rcode;
	88
	89	printf (fmt, dev_addr, argv[1], addr, off, cnt);
	90
	91	rcode = eeprom_read (dev_addr, off, (uchar *) addr, cnt);
	92
4b9206ed	93	puts ("done\n");
3863585b WD	94	return rcode;
	95	} else if (strcmp (argv[1], "write") == 0) {
	96	int rcode;
	97
	98	printf (fmt, dev_addr, argv[1], addr, off, cnt);
	99
	100	rcode = eeprom_write (dev_addr, off, (uchar *) addr, cnt);
	101
4b9206ed	102	puts ("done\n");
3863585b WD	103	return rcode;
	104	}
	105	}
	106
47e26b1b	107	return cmd_usage(cmdtp);
3863585b	108	}
90253178	109	#endif
3863585b WD	110
	111	/*-----------------------------------------------------------------------
	112	*
6d0f6bcf	113	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
3863585b WD	114	* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
3863585b WD	115	*
6d0f6bcf	116	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
3863585b WD	117	* 0x00000nxx for EEPROM address selectors and page number at n.
	118	*/
	119
548738b4	120	#if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
6d0f6bcf JCPV	121	#if !defined(CONFIG_SYS_I2C_EEPROM_ADDR_LEN) \|\| CONFIG_SYS_I2C_EEPROM_ADDR_LEN < 1 \|\| CONFIG_SYS_I2C_EEPROM_ADDR_LEN > 2
6d0f6bcf JCPV	122	#error CONFIG_SYS_I2C_EEPROM_ADDR_LEN must be 1 or 2
3863585b WD	123	#endif
	124	#endif
	125
	126	int eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
	127	{
	128	unsigned end = offset + cnt;
	129	unsigned blk_off;
	130	int rcode = 0;
	131
	132	/* Read data until done or would cross a page boundary.
	133	* We must write the address again when changing pages
	134	* because the next page may be in a different device.
	135	*/
	136	while (offset < end) {
d4f5c728	137	unsigned alen, len;
6d0f6bcf	138	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	139	unsigned maxlen;
	140	#endif
	141
6d0f6bcf	142	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
3863585b WD	143	uchar addr[2];
	144
	145	blk_off = offset & 0xFF; /* block offset */
	146
	147	addr[0] = offset >> 8; /* block number */
	148	addr[1] = blk_off; /* block offset */
	149	alen = 2;
	150	#else
	151	uchar addr[3];
	152
	153	blk_off = offset & 0xFF; /* block offset */
	154
	155	addr[0] = offset >> 16; /* block number */
	156	addr[1] = offset >> 8; /* upper address octet */
	157	addr[2] = blk_off; /* lower address octet */
	158	alen = 3;
6d0f6bcf	159	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
3863585b WD	160
	161	addr[0] \|= dev_addr; /* insert device address */
	162
d4f5c728	163	len = end - offset;
	164
	165	/*
	166	* For a FRAM device there is no limit on the number of the
	167	* bytes that can be ccessed with the single read or write
	168	* operation.
	169	*/
6d0f6bcf	170	#if !defined(CONFIG_SYS_I2C_FRAM)
3863585b WD	171	maxlen = 0x100 - blk_off;
	172	if (maxlen > I2C_RXTX_LEN)
	173	maxlen = I2C_RXTX_LEN;
3863585b WD	174	if (len > maxlen)
3863585b WD	175	len = maxlen;
d4f5c728	176	#endif
d4f5c728	177
548738b4	178	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	179	spi_read (addr, alen, buffer, len);
	180	#else
	181	if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
	182	rcode = 1;
	183	#endif
	184	buffer += len;
	185	offset += len;
	186	}
d4f5c728	187
3863585b WD	188	return rcode;
	189	}
	190
	191	/*-----------------------------------------------------------------------
	192	*
6d0f6bcf	193	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
3863585b WD	194	* 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
3863585b WD	195	*
6d0f6bcf	196	* for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
3863585b WD	197	* 0x00000nxx for EEPROM address selectors and page number at n.
	198	*/
	199
	200	int eeprom_write (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
	201	{
	202	unsigned end = offset + cnt;
	203	unsigned blk_off;
	204	int rcode = 0;
	205
6d0f6bcf	206	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	207	uchar contr_r_addr[2];
	208	uchar addr_void[2];
	209	uchar contr_reg[2];
	210	uchar ctrl_reg_v;
	211	int i;
	212	#endif
	213
6d0f6bcf	214	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	215	eeprom_write_enable (dev_addr,1);
98f4a3df SR	216	#endif
3863585b WD	217	/* Write data until done or would cross a write page boundary.
	218	* We must write the address again when changing pages
	219	* because the address counter only increments within a page.
	220	*/
	221
	222	while (offset < end) {
d4f5c728	223	unsigned alen, len;
6d0f6bcf	224	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	225	unsigned maxlen;
	226	#endif
	227
6d0f6bcf	228	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
3863585b WD	229	uchar addr[2];
	230
	231	blk_off = offset & 0xFF; /* block offset */
	232
	233	addr[0] = offset >> 8; /* block number */
	234	addr[1] = blk_off; /* block offset */
	235	alen = 2;
	236	#else
	237	uchar addr[3];
	238
	239	blk_off = offset & 0xFF; /* block offset */
	240
	241	addr[0] = offset >> 16; /* block number */
	242	addr[1] = offset >> 8; /* upper address octet */
	243	addr[2] = blk_off; /* lower address octet */
	244	alen = 3;
6d0f6bcf	245	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
3863585b WD	246
	247	addr[0] \|= dev_addr; /* insert device address */
	248
d4f5c728	249	len = end - offset;
	250
	251	/*
	252	* For a FRAM device there is no limit on the number of the
f9a78b8d	253	* bytes that can be accessed with the single read or write
d4f5c728	254	* operation.
d4f5c728	255	*/
6d0f6bcf	256	#if !defined(CONFIG_SYS_I2C_FRAM)
d4f5c728	257
6d0f6bcf	258	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
3863585b	259
6d0f6bcf	260	#define EEPROM_PAGE_SIZE (1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)
3863585b WD	261	#define EEPROM_PAGE_OFFSET(x) ((x) & (EEPROM_PAGE_SIZE - 1))
	262
	263	maxlen = EEPROM_PAGE_SIZE - EEPROM_PAGE_OFFSET(blk_off);
	264	#else
	265	maxlen = 0x100 - blk_off;
	266	#endif
	267	if (maxlen > I2C_RXTX_LEN)
	268	maxlen = I2C_RXTX_LEN;
	269
3863585b WD	270	if (len > maxlen)
3863585b WD	271	len = maxlen;
d4f5c728	272	#endif
d4f5c728	273
548738b4	274	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	275	spi_write (addr, alen, buffer, len);
3863585b WD	276	#else
6d0f6bcf	277	#if defined(CONFIG_SYS_EEPROM_X40430)
3863585b WD	278	/* Get the value of the control register.
	279	* Set current address (internal pointer in the x40430)
	280	* to 0x1ff.
	281	*/
	282	contr_r_addr[0] = 9;
	283	contr_r_addr[1] = 0xff;
	284	addr_void[0] = 0;
	285	addr_void[1] = addr[1];
6d0f6bcf JCPV	286	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
	287	contr_r_addr[0] \|= CONFIG_SYS_I2C_EEPROM_ADDR;
	288	addr_void[0] \|= CONFIG_SYS_I2C_EEPROM_ADDR;
3863585b WD	289	#endif
	290	contr_reg[0] = 0xff;
	291	if (i2c_read (contr_r_addr[0], contr_r_addr[1], 1, contr_reg, 1) != 0) {
	292	rcode = 1;
	293	}
	294	ctrl_reg_v = contr_reg[0];
	295
	296	/* Are any of the eeprom blocks write protected?
	297	*/
	298	if (ctrl_reg_v & 0x18) {
	299	ctrl_reg_v &= ~0x18; /* reset block protect bits */
	300	ctrl_reg_v \|= 0x02; /* set write enable latch */
	301	ctrl_reg_v &= ~0x04; /* clear RWEL */
	302
	303	/* Set write enable latch.
	304	*/
	305	contr_reg[0] = 0x02;
	306	if (i2c_write (contr_r_addr[0], 0xff, 1, contr_reg, 1) != 0) {
	307	rcode = 1;
	308	}
	309
	310	/* Set register write enable latch.
	311	*/
	312	contr_reg[0] = 0x06;
	313	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	314	rcode = 1;
	315	}
	316
	317	/* Modify ctrl register.
	318	*/
	319	contr_reg[0] = ctrl_reg_v;
	320	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	321	rcode = 1;
	322	}
	323
	324	/* The write (above) is an operation on NV memory.
	325	* These can take some time (~5ms), and the device
	326	* will not respond to further I2C messages till
	327	* it's completed the write.
	328	* So poll device for an I2C acknowledge.
	329	* When we get one we know we can continue with other
	330	* operations.
	331	*/
	332	contr_reg[0] = 0;
	333	for (i = 0; i < MAX_ACKNOWLEDGE_POLLS; i++) {
aacf9a49	334	if (i2c_read (addr_void[0], addr_void[1], 1, contr_reg, 1) == 0)
3863585b	335	break; /* got ack */
6d0f6bcf JCPV	336	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
6d0f6bcf JCPV	337	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
3863585b WD	338	#endif
	339	}
	340	if (i == MAX_ACKNOWLEDGE_POLLS) {
4b9206ed	341	puts ("EEPROM poll acknowledge failed\n");
3863585b WD	342	rcode = 1;
	343	}
	344	}
	345
	346	/* Is the write enable latch on?.
	347	*/
	348	else if (!(ctrl_reg_v & 0x02)) {
	349	/* Set write enable latch.
	350	*/
	351	contr_reg[0] = 0x02;
	352	if (i2c_write (contr_r_addr[0], 0xFF, 1, contr_reg, 1) != 0) {
	353	rcode = 1;
	354	}
	355	}
	356	/* Write is enabled ... now write eeprom value.
	357	*/
	358	#endif
	359	if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
	360	rcode = 1;
	361
	362	#endif
	363	buffer += len;
	364	offset += len;
	365
6d0f6bcf JCPV	366	#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
6d0f6bcf JCPV	367	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
3863585b WD	368	#endif
3863585b WD	369	}
6d0f6bcf	370	#if defined(CONFIG_SYS_EEPROM_WREN)
98f4a3df SR	371	eeprom_write_enable (dev_addr,0);
98f4a3df SR	372	#endif
3863585b WD	373	return rcode;
	374	}
	375
548738b4	376	#if !defined(CONFIG_SPI) \|\| defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
6dd652fa WD	377	int
	378	eeprom_probe (unsigned dev_addr, unsigned offset)
	379	{
	380	unsigned char chip;
	381
	382	/* Probe the chip address
	383	*/
6d0f6bcf	384	#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
6dd652fa WD	385	chip = offset >> 8; /* block number */
	386	#else
	387	chip = offset >> 16; /* block number */
6d0f6bcf	388	#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
6dd652fa WD	389
	390	chip \|= dev_addr; /* insert device address */
	391
	392	return (i2c_probe (chip));
	393	}
	394	#endif
	395
3863585b WD	396	/*-----------------------------------------------------------------------
	397	* Set default values
	398	*/
6d0f6bcf JCPV	399	#ifndef CONFIG_SYS_I2C_SPEED
6d0f6bcf JCPV	400	#define CONFIG_SYS_I2C_SPEED 50000
3863585b WD	401	#endif
3863585b WD	402
3863585b WD	403	void eeprom_init (void)
3863585b WD	404	{
548738b4 HS	405
548738b4 HS	406	#if defined(CONFIG_SPI) && !defined(CONFIG_ENV_EEPROM_IS_ON_I2C)
3863585b WD	407	spi_init_f ();
	408	#endif
	409	#if defined(CONFIG_HARD_I2C) \|\| \
	410	defined(CONFIG_SOFT_I2C)
6d0f6bcf	411	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
3863585b WD	412	#endif
3863585b WD	413	}
548738b4	414
3863585b WD	415	/*-----------------------------------------------------------------------
3863585b WD	416	*/
90253178	417
8bde7f77 WD	418	/***************************************************/
8bde7f77 WD	419
baa26db4	420	#if defined(CONFIG_CMD_EEPROM)
8bde7f77	421
6d0f6bcf	422	#ifdef CONFIG_SYS_I2C_MULTI_EEPROMS
0d498393 WD	423	U_BOOT_CMD(
0d498393 WD	424	eeprom, 6, 1, do_eeprom,
2fb2604d	425	"EEPROM sub-system",
8bde7f77 WD	426	"read devaddr addr off cnt\n"
8bde7f77 WD	427	"eeprom write devaddr addr off cnt\n"
a89c33db	428	" - read/write `cnt' bytes from `devaddr` EEPROM at offset `off'"
8bde7f77 WD	429	);
8bde7f77 WD	430	#else /* One EEPROM */
0d498393 WD	431	U_BOOT_CMD(
0d498393 WD	432	eeprom, 5, 1, do_eeprom,
2fb2604d	433	"EEPROM sub-system",
8bde7f77 WD	434	"read addr off cnt\n"
8bde7f77 WD	435	"eeprom write addr off cnt\n"
a89c33db	436	" - read/write `cnt' bytes at EEPROM offset `off'"
8bde7f77	437	);
6d0f6bcf	438	#endif /* CONFIG_SYS_I2C_MULTI_EEPROMS */
8bde7f77	439
90253178	440	#endif