[people/ms/u-boot.git] / cpu / mpc8xxx / ddr / ddr2_dimm_params.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * Version 2 as published by the Free Software Foundation.
 */

#include <common.h>
#include <asm/fsl_ddr_sdram.h>

#include "ddr.h"
/*
 * Calculate the Density of each Physical Rank.
 * Returned size is in bytes.
 *
 * Study these table from Byte 31 of JEDEC SPD Spec.
 *
 *		DDR I	DDR II
 *	Bit	Size	Size
 *	---	-----	------
 *	7 high	512MB	512MB
 *	6	256MB	256MB
 *	5	128MB	128MB
 *	4	 64MB	 16GB
 *	3	 32MB	  8GB
 *	2	 16MB	  4GB
 *	1	  2GB	  2GB
 *	0 low	  1GB	  1GB
 *
 * Reorder Table to be linear by stripping the bottom
 * 2 or 5 bits off and shifting them up to the top.
 *
 */
static phys_size_t
compute_ranksize(unsigned int mem_type, unsigned char row_dens)
{
	phys_size_t bsize;

	/* Bottom 5 bits up to the top. */
	bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
	bsize <<= 27ULL;
	debug("DDR: DDR II rank density = 0x%08x\n", bsize);

	return bsize;
}

/*
 * Convert a two-nibble BCD value into a cycle time.
 * While the spec calls for nano-seconds, picos are returned.
 *
 * This implements the tables for bytes 9, 23 and 25 for both
 * DDR I and II.  No allowance for distinguishing the invalid
 * fields absent for DDR I yet present in DDR II is made.
 * (That is, cycle times of .25, .33, .66 and .75 ns are
 * allowed for both DDR II and I.)
 */
static unsigned int
convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
{
	/* Table look up the lower nibble, allow DDR I & II. */
	unsigned int tenths_ps[16] = {
		0,
		100,
		200,
		300,
		400,
		500,
		600,
		700,
		800,
		900,
		250,	/* This and the next 3 entries valid ... */
		330,	/* ...  only for tCK calculations. */
		660,
		750,
		0,	/* undefined */
		0	/* undefined */
	};

	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
	unsigned int tenth_ns = spd_val & 0x0F;
	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];

	return ps;
}

static unsigned int
convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
{
	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
	unsigned int hundredth_ns = spd_val & 0x0F;
	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;

	return ps;
}

static unsigned int byte40_table_ps[8] = {
	0,
	250,
	330,
	500,
	660,
	750,
	0,	/* supposed to be RFC, but not sure what that means */
	0	/* Undefined */
};

static unsigned int
compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
{
	unsigned int trfc_ps;

	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
		+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];

	return trfc_ps;
}

static unsigned int
compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
{
	unsigned int trc_ps;

	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];

	return trc_ps;
}

/*
 * Determine Refresh Rate.  Ignore self refresh bit on DDR I.
 * Table from SPD Spec, Byte 12, converted to picoseconds and
 * filled in with "default" normal values.
 */
static unsigned int
determine_refresh_rate_ps(const unsigned int spd_refresh)
{
	unsigned int refresh_time_ps[8] = {
		15625000,	/* 0 Normal    1.00x */
		3900000,	/* 1 Reduced    .25x */
		7800000,	/* 2 Extended   .50x */
		31300000,	/* 3 Extended  2.00x */
		62500000,	/* 4 Extended  4.00x */
		125000000,	/* 5 Extended  8.00x */
		15625000,	/* 6 Normal    1.00x  filler */
		15625000,	/* 7 Normal    1.00x  filler */
	};

	return refresh_time_ps[spd_refresh & 0x7];
}

/*
 * The purpose of this function is to compute a suitable
 * CAS latency given the DRAM clock period.  The SPD only
 * defines at most 3 CAS latencies.  Typically the slower in
 * frequency the DIMM runs at, the shorter its CAS latency can.
 * be.  If the DIMM is operating at a sufficiently low frequency,
 * it may be able to run at a CAS latency shorter than the
 * shortest SPD-defined CAS latency.
 *
 * If a CAS latency is not found, 0 is returned.
 *
 * Do this by finding in the standard speed bin table the longest
 * tCKmin that doesn't exceed the value of mclk_ps (tCK).
 *
 * An assumption made is that the SDRAM device allows the
 * CL to be programmed for a value that is lower than those
 * advertised by the SPD.  This is not always the case,
 * as those modes not defined in the SPD are optional.
 *
 * CAS latency de-rating based upon values JEDEC Standard No. 79-2C
 * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS,
 * and tRC for corresponding bin"
 *
 * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
 * Not certain if any good value exists for CL=2
 */
				 /* CL2   CL3   CL4   CL5   CL6 */
unsigned short ddr2_speed_bins[] = {   0, 5000, 3750, 3000, 2500 };

unsigned int
compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
{
	const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
	unsigned int lowest_tCKmin_found = 0;
	unsigned int lowest_tCKmin_CL = 0;
	unsigned int i;

	debug("mclk_ps = %u\n", mclk_ps);

	for (i = 0; i < num_speed_bins; i++) {
		unsigned int x = ddr2_speed_bins[i];
		debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
		      i, x, lowest_tCKmin_found);
		if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) {
			lowest_tCKmin_found = x;
			lowest_tCKmin_CL = i + 2;
		}
	}

	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);

	return lowest_tCKmin_CL;
}

/*
 * ddr_compute_dimm_parameters for DDR2 SPD
 *
 * Compute DIMM parameters based upon the SPD information in spd.
 * Writes the results to the dimm_params_t structure pointed by pdimm.
 *
 * FIXME: use #define for the retvals
 */
unsigned int
ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
			     dimm_params_t *pdimm,
			     unsigned int dimm_number)
{
	unsigned int retval;

	if (spd->mem_type) {
		if (spd->mem_type != SPD_MEMTYPE_DDR2) {
			printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number);
			return 1;
		}
	} else {
		memset(pdimm, 0, sizeof(dimm_params_t));
		return 1;
	}

	retval = ddr2_spd_check(spd);
	if (retval) {
		printf("DIMM %u: failed checksum\n", dimm_number);
		return 2;
	}

	/*
	 * The part name in ASCII in the SPD EEPROM is not null terminated.
	 * Guarantee null termination here by presetting all bytes to 0
	 * and copying the part name in ASCII from the SPD onto it
	 */
	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);

	/* DIMM organization parameters */
	pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
	pdimm->data_width = spd->dataw;
	pdimm->primary_sdram_width = spd->primw;
	pdimm->ec_sdram_width = spd->ecw;

	/* FIXME: what about registered SO-DIMM? */
	switch (spd->dimm_type) {
	case 0x01:	/* RDIMM */
	case 0x10:	/* Mini-RDIMM */
		pdimm->registered_dimm = 1; /* register buffered */
		break;

	case 0x02:	/* UDIMM */
	case 0x04:	/* SO-DIMM */
	case 0x08:	/* Micro-DIMM */
	case 0x20:	/* Mini-UDIMM */
		pdimm->registered_dimm = 0;	/* unbuffered */
		break;

	default:
		printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
		return 1;
		break;
	}

	/* SDRAM device parameters */
	pdimm->n_row_addr = spd->nrow_addr;
	pdimm->n_col_addr = spd->ncol_addr;
	pdimm->n_banks_per_sdram_device = spd->nbanks;
	pdimm->edc_config = spd->config;
	pdimm->burst_lengths_bitmask = spd->burstl;
	pdimm->row_density = spd->rank_dens;

	/*
	 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
	 * nanoseconds and represented as BCD.
	 */
	pdimm->tCKmin_X_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
	pdimm->tCKmin_X_minus_1_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
	pdimm->tCKmin_X_minus_2_ps
		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);

	pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);

	/*
	 * Compute CAS latencies defined by SPD
	 * The SPD caslat_X should have at least 1 and at most 3 bits set.
	 *
	 * If cas_lat after masking is 0, the __ilog2 function returns
	 * 255 into the variable.   This behavior is abused once.
	 */
	pdimm->caslat_X  = __ilog2(spd->cas_lat);
	pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
					  & ~(1 << pdimm->caslat_X));
	pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
					  & ~(1 << pdimm->caslat_X)
					  & ~(1 << pdimm->caslat_X_minus_1));

	/* Compute CAS latencies below that defined by SPD */
	pdimm->caslat_lowest_derated
		= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());

	/* Compute timing parameters */
	pdimm->tRCD_ps = spd->trcd * 250;
	pdimm->tRP_ps = spd->trp * 250;
	pdimm->tRAS_ps = spd->tras * 1000;

	pdimm->tWR_ps = spd->twr * 250;
	pdimm->tWTR_ps = spd->twtr * 250;
	pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);

	pdimm->tRRD_ps = spd->trrd * 250;
	pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);

	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);

	pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
	pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
	pdimm->tDS_ps
		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
	pdimm->tDH_ps
		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);

	pdimm->tRTP_ps = spd->trtp * 250;
	pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
	pdimm->tQHS_ps = spd->tqhs * 10;

	return 0;
}
Commit	Line	Data
233fdd50 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* Version 2 as published by the Free Software Foundation.
	7	*/
	8
	9	#include <common.h>
	10	#include <asm/fsl_ddr_sdram.h>
	11
	12	#include "ddr.h"
	13	/*
	14	* Calculate the Density of each Physical Rank.
	15	* Returned size is in bytes.
	16	*
	17	* Study these table from Byte 31 of JEDEC SPD Spec.
	18	*
	19	* DDR I DDR II
	20	* Bit Size Size
	21	* --- ----- ------
	22	* 7 high 512MB 512MB
	23	* 6 256MB 256MB
	24	* 5 128MB 128MB
	25	* 4 64MB 16GB
	26	* 3 32MB 8GB
	27	* 2 16MB 4GB
	28	* 1 2GB 2GB
	29	* 0 low 1GB 1GB
	30	*
	31	* Reorder Table to be linear by stripping the bottom
	32	* 2 or 5 bits off and shifting them up to the top.
	33	*
	34	*/
	35	static phys_size_t
	36	compute_ranksize(unsigned int mem_type, unsigned char row_dens)
	37	{
	38	phys_size_t bsize;
	39
	40	/* Bottom 5 bits up to the top. */
	41	bsize = ((row_dens >> 5) \| ((row_dens & 31) << 3));
	42	bsize <<= 27ULL;
	43	debug("DDR: DDR II rank density = 0x%08x\n", bsize);
	44
	45	return bsize;
	46	}
	47
	48	/*
	49	* Convert a two-nibble BCD value into a cycle time.
	50	* While the spec calls for nano-seconds, picos are returned.
	51	*
	52	* This implements the tables for bytes 9, 23 and 25 for both
	53	* DDR I and II. No allowance for distinguishing the invalid
	54	* fields absent for DDR I yet present in DDR II is made.
	55	* (That is, cycle times of .25, .33, .66 and .75 ns are
	56	* allowed for both DDR II and I.)
	57	*/
	58	static unsigned int
	59	convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
	60	{
	61	/* Table look up the lower nibble, allow DDR I & II. */
	62	unsigned int tenths_ps[16] = {
	63	0,
	64	100,
65	200,
66	300,
67	400,
68	500,
69	600,
70	700,
71	800,
72	900,
73	250, /* This and the next 3 entries valid ... */
74	330, /* ... only for tCK calculations. */
75	660,
76	750,
77	0, /* undefined */
78	0 /* undefined */
79	};
80
81	unsigned int whole_ns = (spd_val & 0xF0) >> 4;
82	unsigned int tenth_ns = spd_val & 0x0F;
83	unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
84
85	return ps;
86	}
87
88	static unsigned int
89	convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
90	{
91	unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
92	unsigned int hundredth_ns = spd_val & 0x0F;
93	unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
94
95	return ps;
96	}
97
98	static unsigned int byte40_table_ps[8] = {
99	0,
100	250,
101	330,
102	500,
103	660,
104	750,
105	0, /* supposed to be RFC, but not sure what that means */
106	0 /* Undefined */
107	};
108
109	static unsigned int
110	compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
111	{
112	unsigned int trfc_ps;
113
114	trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
115	+ byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
116
117	return trfc_ps;
118	}
119
120	static unsigned int
121	compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
122	{
123	unsigned int trc_ps;
124
125	trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
126
127	return trc_ps;
128	}
129
130	/*
131	* Determine Refresh Rate. Ignore self refresh bit on DDR I.
132	* Table from SPD Spec, Byte 12, converted to picoseconds and
133	* filled in with "default" normal values.
134	*/
135	static unsigned int
136	determine_refresh_rate_ps(const unsigned int spd_refresh)
137	{
138	unsigned int refresh_time_ps[8] = {
139	15625000, /* 0 Normal 1.00x */
140	3900000, /* 1 Reduced .25x */
141	7800000, /* 2 Extended .50x */
142	31300000, /* 3 Extended 2.00x */
143	62500000, /* 4 Extended 4.00x */
144	125000000, /* 5 Extended 8.00x */
145	15625000, /* 6 Normal 1.00x filler */
146	15625000, /* 7 Normal 1.00x filler */
147	};
148
149	return refresh_time_ps[spd_refresh & 0x7];
150	}
151
152	/*
153	* The purpose of this function is to compute a suitable
154	* CAS latency given the DRAM clock period. The SPD only
155	* defines at most 3 CAS latencies. Typically the slower in
156	* frequency the DIMM runs at, the shorter its CAS latency can.
157	* be. If the DIMM is operating at a sufficiently low frequency,
158	* it may be able to run at a CAS latency shorter than the
159	* shortest SPD-defined CAS latency.
160	*
161	* If a CAS latency is not found, 0 is returned.
162	*
163	* Do this by finding in the standard speed bin table the longest
164	* tCKmin that doesn't exceed the value of mclk_ps (tCK).
165	*
166	* An assumption made is that the SDRAM device allows the
167	* CL to be programmed for a value that is lower than those
168	* advertised by the SPD. This is not always the case,
169	* as those modes not defined in the SPD are optional.
170	*
171	* CAS latency de-rating based upon values JEDEC Standard No. 79-2C
172	* Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS,
173	* and tRC for corresponding bin"
174	*
175	* ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
176	* Not certain if any good value exists for CL=2
177	*/
178	/* CL2 CL3 CL4 CL5 CL6 */
179	unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500 };
180
181	unsigned int
182	compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
183	{
184	const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
185	unsigned int lowest_tCKmin_found = 0;
186	unsigned int lowest_tCKmin_CL = 0;
187	unsigned int i;
188
189	debug("mclk_ps = %u\n", mclk_ps);
190
191	for (i = 0; i < num_speed_bins; i++) {
192	unsigned int x = ddr2_speed_bins[i];
193	debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
194	i, x, lowest_tCKmin_found);
195	if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) {
196	lowest_tCKmin_found = x;
197	lowest_tCKmin_CL = i + 2;
198	}
199	}
200
201	debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
202
203	return lowest_tCKmin_CL;
204	}
205
206	/*
207	* ddr_compute_dimm_parameters for DDR2 SPD
208	*
209	* Compute DIMM parameters based upon the SPD information in spd.
210	* Writes the results to the dimm_params_t structure pointed by pdimm.
211	*
212	* FIXME: use #define for the retvals
213	*/
214	unsigned int
215	ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
216	dimm_params_t *pdimm,
217	unsigned int dimm_number)
218	{
219	unsigned int retval;
220
221	if (spd->mem_type) {
222	if (spd->mem_type != SPD_MEMTYPE_DDR2) {
223	printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number);
224	return 1;
225	}
226	} else {
227	memset(pdimm, 0, sizeof(dimm_params_t));
228	return 1;
229	}
230
231	retval = ddr2_spd_check(spd);
232	if (retval) {
233	printf("DIMM %u: failed checksum\n", dimm_number);
234	return 2;
235	}
236
237	/*
238	* The part name in ASCII in the SPD EEPROM is not null terminated.
239	* Guarantee null termination here by presetting all bytes to 0
240	* and copying the part name in ASCII from the SPD onto it
241	*/
242	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
243	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
244
245	/* DIMM organization parameters */
246	pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
247	pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
248	pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
249	pdimm->data_width = spd->dataw;
250	pdimm->primary_sdram_width = spd->primw;
251	pdimm->ec_sdram_width = spd->ecw;
252
253	/* FIXME: what about registered SO-DIMM? */
254	switch (spd->dimm_type) {
255	case 0x01: /* RDIMM */
256	case 0x10: /* Mini-RDIMM */
257	pdimm->registered_dimm = 1; /* register buffered */
258	break;
259
260	case 0x02: /* UDIMM */
261	case 0x04: /* SO-DIMM */
262	case 0x08: /* Micro-DIMM */
263	case 0x20: /* Mini-UDIMM */
264	pdimm->registered_dimm = 0; /* unbuffered */
265	break;
266
267	default:
268	printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
269	return 1;
270	break;
271	}
272
273	/* SDRAM device parameters */
274	pdimm->n_row_addr = spd->nrow_addr;
275	pdimm->n_col_addr = spd->ncol_addr;
276	pdimm->n_banks_per_sdram_device = spd->nbanks;
277	pdimm->edc_config = spd->config;
278	pdimm->burst_lengths_bitmask = spd->burstl;
279	pdimm->row_density = spd->rank_dens;
280
281	/*
282	* Calculate the Maximum Data Rate based on the Minimum Cycle time.
283	* The SPD clk_cycle field (tCKmin) is measured in tenths of
284	* nanoseconds and represented as BCD.
285	*/
286	pdimm->tCKmin_X_ps
287	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
288	pdimm->tCKmin_X_minus_1_ps
289	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
290	pdimm->tCKmin_X_minus_2_ps
291	= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
292
293	pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
294
295	/*
296	* Compute CAS latencies defined by SPD
297	* The SPD caslat_X should have at least 1 and at most 3 bits set.
298	*
299	* If cas_lat after masking is 0, the __ilog2 function returns
300	* 255 into the variable. This behavior is abused once.
301	*/
302	pdimm->caslat_X = __ilog2(spd->cas_lat);
303	pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
304	& ~(1 << pdimm->caslat_X));
305	pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
306	& ~(1 << pdimm->caslat_X)
307	& ~(1 << pdimm->caslat_X_minus_1));
308
309	/* Compute CAS latencies below that defined by SPD */
310	pdimm->caslat_lowest_derated
311	= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
312
313	/* Compute timing parameters */
314	pdimm->tRCD_ps = spd->trcd * 250;
315	pdimm->tRP_ps = spd->trp * 250;
316	pdimm->tRAS_ps = spd->tras * 1000;
317
318	pdimm->tWR_ps = spd->twr * 250;
319	pdimm->tWTR_ps = spd->twtr * 250;
320	pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
321
322	pdimm->tRRD_ps = spd->trrd * 250;
323	pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
324
325	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
326
327	pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
328	pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
329	pdimm->tDS_ps
330	= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
331	pdimm->tDH_ps
332	= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
333
334	pdimm->tRTP_ps = spd->trtp * 250;
335	pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
336	pdimm->tQHS_ps = spd->tqhs * 10;
337
338	return 0;
339	}